CAMAC 064 Modules
Detailed Listing of Implemented Versions
28-April-2008

General Considerations

The CAMAC 064 module is a general-purpose gate and gating card that can be used in a variety of ways. Eight gates are provided. The first four gates can also modulate externally applied signals. Gate sets and resets are normally applied to the I/O. The module also has TCLK facility and provision for two PALs that can also provide set and reset functions. Discrete wire jumpers are necessary to implement the TCLK option. The TCLK decoder PALs are located at IC positions #18 and #22. The front panel and rear I/O gate outputs are driven by separate drivers. Upon power up or clear command, all gates are toggled to the off state.

There is also capability for directly outputting TCLK events.

CAUTION: Portions of this document may be inaccurate or incomplete.

INSTALLED MODULE DIRECTORY
Ver 0.0Miscellaneous and Test
Ver 0.1MI $E1 N10
Ver 1.5Obsolete
Ver 1.66MI $10 N12
Ver 2.2Obsolete
Ver 3.3Obsolete
Ver 4.5?
Ver 5.0BSTR $92 N5
Ver 6.0BSTR $92 N7
Ver 7.4MI $7E N9
Ver 7.5BSTR $92 N9
Ver 8.0?
Ver 9.1TEV $DF N6
Ver 10.0?
Ver 11.0SWYD $05 N1
Ver 12.0MI $93 N11
Ver 13.0BSTR $30 N23
Ver 14.0BSTR $90 N6
Ver 15.0PBAR $54 N13
Ver 16.0MI $90 N9
Ver 17.0TCLK $05 N6
Ver 18.0MI $12 N2
Ver 19.0BSTR $80 N5

Version 0.0: Basic Module without Modifications 2-22-93

This version is the basic version of the CAMAC 064 module without any modifications.

Module Location: $55 N3 (P-Bar) ARF1 Gates for Pete Seifrid. No TCLK or IC18.

Version 0.1: MiniBooNE Timing 3-13-03

This version is the basic version of the CAMAC 064 module with chip#19 changed from 74LS08 to 74LS00 in order to invert the final output. Gated Input 1 is C377 Ch5, Set 1 is C377 Ch6, Reset 1 is C377 Ch7. All inputs are 100ohm terminated.

Module Location:MI $E1 N10 (MiniBooNE)

No TCLK or IC18. Chip#19 is 74LS00

Version 1.5: MKS90 Permit Gate 3-15-96

This version has been created for Jim Lackey to control the firing of the MKS90 Main Ring Injection Kicker. PAL 06418K.ABL is utilized in IC position #18. No PAL is necessary at IC position #22. Gate 1 enables the two Programmable RF Delay Modules associated with MKS90 firing triggers. The gate is set by the "or" of TCLK event $20 $21 $29 $2A $2B $2D and $2E and is reset by events $17 or $22. This module was installed to prevent MKS90 firing during the pre-pulse associated with the Booster Beam Cycle marked by TCLK event $17.

The two terminating resistors at IC #9-8 and #9-9 should be removed. Discrete wires should be added from IC #18-19 to #9-8 (P1 to S1) and from #18-18 to #9-9 (P2 to S2). The I/O connector should be wired for TCLK Input and two Gate 1 Output connections.
Module Location:None Installed
Unique PAL(s): 06418K.ABL
NOTE: MKS90 needs to fire on at least one $12 cycle before a Booster beam cycle to operate properly. The developed enable gate can clearly inhibit or allow $12 cycle firings depending on their exact placement in the time line relative to the beginning of a Main Ring ramp.

Version 1.66: MI-10 Kicker PFL and Firing Permit Gate 6-18-02

This version has been created for Darren Qunell to control the firing of the MI-10 Injection Kickers K1A, K1B, and K1C. PAL 06418W.ABL is utilized in IC position #18. PAL 06418W.ABL is also utilized at IC position #22.

The kicker thyratron firing enables are provided by Gates 1, 2, 3 and 4. Gate 1 enables the Programmable RF Delay Module associated with the thyratron firing trigger for K1A. Gate 2 enables the Programmable RF Delay Module associated with the thyratron firing trigger for K1B. Gate 3 enables the Programmable RF Delay Module associated with the thyratron firing trigger for K1C. Gate 4 is available as a spare enable with the same functionality of Gates 1, 2 and 3.

All of the thyratron firing trigger gates are set by the OR of TCLK event $13 $14 $15 $16 $19 and $1C and are reset by the OR of events $12 $17 $1D and $22.

The PFL triggers for the MI-10 Kickers are provided by Gates 5, 6, 7, and 8.

Gate 5 supplies the PFN trigger for kicker K1A. Gate 6 supplies the PFN trigger for kicker K1B. Gate 7 supplies the PFN trigger for kicker K1C. Gate 8 is available as a spare PFN trigger with the same functionality of Gates 5, 6, and 7. The PFN triggers are pulses made from TCLK event $1F anded with the thyratron trigger gate.

This module was installed to prevent MI-10 kickers from firing on TCLK event $1F associated with the Booster Beam Cycle marked by TCLK event $17. This version additionally provides gating so that the PFNs aren't triggered by the TCLK event $1F associated with the TCLK event $17.

Construction Details

  1. Remove IC#16 is removed for this purpose.
  2. Wire P7 to 16-9
  3. Wire P8 to 16-7
  4. Wire P15 to 16-13
  5. Wire P16 to 16-4.

For IC#9,

  1. Wire P2 to R1
  2. Wire P1 to S1
  3. Wire P4 to R2
  4. Wire P3 to S2
  5. Wire P10 to R3
  6. Wire P9 to S3
  7. Wire P12 to R4
  8. Wire P11 to S4.

For IC#8

  1. Wire P2 to R5
  2. Wire P1 to S5
  3. Wire P4 to R6
  4. Wire P3 to S6
  5. Wire P10 to R7
  6. Wire P9 to S7
  7. Wire P12 to R8
  8. Wire P11 to S8.

The two terminating resistors at IC #9-8 and #9-9 should be removed. Discrete wires should be added from IC #18-19 to #9-8 (P1 to S1) and from #18-18 to #9-9 (P2 to S2). The I/O connector should be wired for TCLK Input and two Gate 1 Output connections.
Module Location: $10 N12 (Main Injector)
Unique PAL(s): 06418W.ABL (located at IC#18 and IC#22)
NOTE:The MI-10 kickers K1A, K1B, K1C may receive multiple triggers without having a tripped status. However, when they receive a PFN trigger a thyratron fire trigger must follow it.

Version 2.2 QXR Fast Digitizer Trigger 12-14-87

Two copies of this version have been created for Howie Pfeffer to facilitate the generation of triggers for a fast digitizer system using the DSP 2610 module at both A0 and D0 locations for analyzing QXR at a quench during Tevatron flat-top.

The unique features of these modules are as follows

  1. Digitizer Trigger Gate at Gate 1 and Gate 2 front panel outputs. These gates are normally high and go low at the occurrence of TCLK event $4E (Tevatron Quench) during Tevatron flat-top (as defined by TCLK events $45 and $46) or at the occurrence of an externally applied timing pulse. These gates are reset to the high level by the occurrence of a second externally applied timing channel or by a reset of the module.
  2. Gate 3 front panel output is the logical compliment of Gates 1 and 2.
  3. Gate 4 front panel output is turned on and off by TCLK events $45 and $46 respectively.
  4. Gates 5 and 6 front panel outputs are decoded TCLK event $07 (720 Hz).
  5. Gates 7 and 8 front panel outputs are decoded TCLK event $42 (start of Tevatron ramp).

Module Location: $1A N4 and $1D N6 (Tevatron)
Unique PAL(s): 06418A.ABL P1 = /$07 P2 = /$42 P3 = $45 P4 = $46 P5 = $4E

Construction Notes:

  1. Remove IC #16. Float pins 7 and 9 of IC #17.
  2. Wire 18-19 (P1) to IC #24 pins 5, 6, 8, & 9.
  3. Wire 18-18 (P2) to IC #24 pins 2, 3, 11, & 12.
  4. Remove 100-ohm resistors at IC #9 pins 2 and 3.
  5. Wire 18-17 (P3) to 9-2 (S4). Wire 18-16 (P4) to 9-3 (R4).
  6. Remove 100-ohm resistor at 11-1. Wire 18-15 (P5) to 11-1.
  7. Wire 8-18 to 19-1.
  8. Wire 23-1 to (Gated Output 4 on I/O 7R) to 9-4 (Set Gate 3 input on I/O 13L).
  9. Wire pin 13 of IC #21 or #25 to IC #25 pins 5, 6, 8, & 9.
  10. I/O Wiring: RG58s with Lemo termination:
    1R TCLK Input, 3L Ext Trig, 14L Ext Reset

Version 3.3 E760 High Voltage Inhibit 4-12-88

This version has been created for Mike Church as a facility to gate off the high voltage for the E760 experiment when beam is thought to be on its way from either Main Ring or Booster. All available gates are driven. The last four of the gates are complements of the first four since nobody is exactly sure of what they really want.

Gates 1 through 4 are set by TCLK event $52 (Permitted Beam) on a P-Bar scenario and are reset by event $53 (Inhibited Beam) on a P-Bar scenario. Gates 5 through 8 are the complements of Gates 1 through 4.

A P-Bar scenario is loosely defined as a $17 cycle preceded by an $8A, or by a $14 or $16 cycle preceded by a $29 or $2D or $2E Main Ring cycle. The Booster cycle flags are reset by $11. The Main Ring cycle flags are reset by $22.

All sixteen 100 ohm terminating resistors should be removed from the inputs of ICs #8 and #9.

Three wires are added between the PALs at locations #18 and #22 as follows: #18-12 to #22-14, #18-17 to #22-15, and #18-19 to #22-16.

Also add discrete wires as follows: IC #22-17 to #8-3,5,7,9 and #9-2,4,6,8; and IC #22-18 to #8-2,4,6,8 and #9-3,5,7,9.

Module Location:None Installed
Unique PAL(s): 06418G.ABL and 06422A.ABL

Version 4.5

This version has been created for Stan Tawzer and Phil Martin as a means of automatically selecting Mountain Range Box triggers for Main Ring and Tevatron beam displays. When both the local and remote TAB and TAC controls are false, control is facilitated by the 064 gates.

Gate 1 (TAB) serves as TAB control for the Main Ring display. This gate is set by TCLK event $8E during a Main Ring $29 cycle. They are normally reset by TCLK events $20,$21, $26, $2A, $2B, $2D, $2E, $8D, or $8F.

Gate 2 (TAC) serves as TAC control for the Main Ring display. This gate is set by TCLK event $8F during a Main Ring $29 cycle. They are normally reset by TCLK events $20, $21, $26, $2A, $2B, $2D, $2E, $8D, or $8E.

Gates 3 and 4 are similar to Gates 1 and 2 respectively.

Gate 5 is provided for the Sampled Bunch Display system built by Doug Howard. It is set by the wire-or of two 377 timing channels: T:SBDTRG from $85 N14 A(0), and T:SBDT20 from $85 N14 A(7). Gate 5 is reset by TCLK event $26.

All of the 100 ohm input terminating resistors should be removed from the gate set and reset inputs of IC #9 (pins 2 through 9) and from IC #8-9. Add discrete wires as follows: #18-19 to #9-4 and #9-8 (S3 and S1); #18-18 to #9-2 and #9-6 (S4 and S2); #18-17 to #9-5 and #9-9 (R1 and R3), #18-16 to #8-9 (R5); and #18-15 to #9-3 and #9-7 (R2 and R4).

The I/O connector should be wired for TCLK input and for all Gate Outputs.

Module Location:Locations unknown
Unique PAL(s): 06418H.ABL

Version 5.0 No Gates Used as of 8-10-92 per Mraz.

This version has been created for Barry Barnes to satisfy various gating requirements for the Booster Low Level System in the East Gallery. This is a stock card without any special modifications or unique PALs. The TCLK Decoder chip at IC position #14 and the PALs at IC positions #18 and #19 need not be installed at this time.

Four gates are utilized. Timing channels provide the gate sets and resets. Gates 3 and 5 and Gates 4 and 6 have shared sets and resets. This sharing is accomplished by cross-wiring the sets and resets for these gates on the IO connector.

Refer to [DUCAR.DOC]TIMING.BST for more detailed assignments of timing channels and Gate names.

Module Location: $92 N5 (Booster)
Unique PAL(s): none

Version 6.0

This version has been created for Barry Barnes to satisfy various gating requirements for the Booster Low Level System in the East Gallery. This is a stock card without any special modifications or unique PALs. The TCLK Decoder chip at IC position #14 and the PALs at IC positions #18 and #19 need not be installed at this time.

Only Gate 1 is utilized. Timing channels provide the gate sets and resets.

Refer to [DUCAR.DOC]TIMING.BST for more detailed assignments of timing channels and Gate names.

Module Location: $92 N7 (Booster)
Unique PAL(s): none

Version 7.3 Booster LLRF & HLRF Gates 3-15-96

This version has been created for Barry Barnes to satisfy various gating requirements for the Booster Low Level System in the East Gallery.

Two gates are utilized. Timing channels are used to provide the set and reset for Gate 3. Gates 1 and 2 are set and reset by TCLK events.

Gated Outputs #1 and #2 are used to provide certain TCLK events to a rf switch module which determines which rf signal (Booster rf or Main Ring rf) is applied to the BBDLY module. The rf switch and BBDLY modules are both located in a NIM bin in Rack BLLRF-3.

Refer to [DUCAR.DOC]TIMING.BST for more detailed assignments of timing channels and Gate names.

Remove the 100-ohm terminating resistors from the Gate 1 and 2 Set and Reset inputs - IC #9 pins 6, 7, 8, and 9.

Add discrete wires as follows:

  1. IC #18-19 to #9-9 and #9-7 (P1 to R1 and R2);
  2. IC #18-18 to #9-8 (P2 to S1);
  3. IC #18-17 to #9-6 (P3 to S2).
  4. IC #18-16 to #19-10 (P4 to GO1),
  5. IC #18-15 to #19-4 (P5 to GO2).

Module Location: $92 N9 (Booster)
Unique PAL(s): 06418L.ABL

Version 7.4 ?

Module Location:MI $7E N9
Unique PAL(s): 06418M.ABL

Version 7.5 Booster High Level RF Programs

This version updates Version 7.3

Gate 1 is for Anode and Cascode curves and comes on at the 2nd $12 event.

Gate 2, for the Bias Supplies, comes on early with $08.

It also generates certain TCLK events which drive Gated Outputs #1 and #2 to control the applied rf to the BBDLY NIM module.

Module Location:BSTR $92 N9
Unique PAL(s): 06418U.ABL

Version 8.0

This version has been created for Bill Miller to satisfy gating requirements for the MRRF Control Room area. Four gates are utilized. Gates 1 and 2 are set and reset by TCLK events $2A and $26 respectively. Gates 3 and 4 are set and reset by TCLK events $2B and $26 respectively. Gate #1 is used by a NIM module to switch a beam pick-up signal from protons to p-bars on a $2A cycle. This is really the only Gate used at this time. The other gates are provided for convenience.

Remove the 100-ohm terminating resistors from the Gate 1, 2, 3 and 4 Set and Reset inputs - IC #9 pins 2 through 9. Add discrete wires as follows:

  1. IC #18-19 to #9-8 and #9-6 (P1 to S1and S2)
  2. IC #18-18 to #9-4 and #9-2 (P2 to S3 and S4)
  3. IC #18-17 to #9-9, #9-7, #9-5, and #9-3 (P3 to R1, R2, R3, and R4).

Module Location: $85 N9 (DEC-R)
Unique PAL(s): 06418E.ABL

Version 9.1 Main Control Room VCR Video Mux 6-8-88

This version has been created for Dave Johnson to satisfy the need of multiplexing video signals to a VCR in the Main Control Room at the library console. Gates 1 through 4 are used to control mux address lines valued at 1, 2, 4, and 8. At this time, only three video channels are switched. The truth table is as follows:
G4G3G2G1ChanDescription
00000Accumulator "Jello" Display
00011AP-10 Mountain Range - P-Bar Extraction
00102MR/TEV Mountain Range - Misc Displays

Chan 0 is set by TCLK events $9A or $2A which occur during a $C1 to $42 Flag.

Chan 1 is set by TCLK event $94 (MRBS $7A) which occurs during a $C1 to $42 Flag.

Chan 2 is set by TCLK event $25 which occurs during both a $C1 to $42 Flag and a $2A to $26 Flag. Chan 2 is also set by event $2B - but not if the $2B occurs while a $9A to $2A Flag is asserted. Additionally, Chan 2 will remain selected when the $C1 to $42 flag is unasserted.

The Gate 8 front panel LED has also been wired to the complement of the $C1 to $42 Flag to indicate its presence (LED ON when Flag is asserted).

Remove the 100 ohm terminating resistors from the Gate 1 thru Gate 4 Set and Reset inputs at IC #9 - Except for the Set input for Gate 3 (#9-4).

Add discrete wires as follows:

  1. IC #18-19 to #9-8 (P1 to S1)
  2. IC #18-18 to #9-9 (P2 to R1)
  3. IC #18-17 to #9-6 (P3 to S2)
  4. IC #18-16 to #9-7 (P4 to R2)
  5. IC #18-14 to #9-5 (P6 to R3)
  6. IC #18-13 to #22-13 (C142F)
  7. IC #18-12 to #22-12 (2A26F)
  8. IC #22-17 to #9-2 (P11 to S4)
  9. IC #22-19 (P9) to floated #26-2 (Gate 8 LED driver)
  10. IC #22-16 to #9-3 (P12 to R4).

Jim Engelbrecht has details of connector wiring of the video multiplexer.

Module Location: $DF N6 (Tevatron)
Unique PAL(s): 06418I.ABL 06422B.ABL

Version 10.0 Main Ring Damper Gates 6-25-90

This version has been created for Jim Crisp to provide gates for the Main Ring Slow and Super Dampers at MRRF. This is a stock card without any special modifications or unique PALs. The TCLK Decoder chip at IC position #14 should be installed nonetheless. PALs at IC positions #18 and #22 are not to be installed at this time.

Four gates have sets and resets wired to two adjacent 377 timing modules. Gate 1 is assigned to the Main Ring Horizontal Slow Damper. Gate 2 is assigned to the Main Ring Vertical Slow Damper. Gate 3 is assigned to the Main Ring Super Damper. Gate 4 is wired to timing channels but is currently not assigned. Each of these gates has two timing channels outputs wired-or'd to the set input, and two timing channels wire-or'd to the reset input.

Module Location:Locations unknown
Unique PAL(s): none

Version 11.0

This version has been created to replace the gating functions of the LBOE module. Gates 1 and 2 control the throughput of BES to generate requests for TCLK $1E and $1F respectively. Gate 3 uses a signal from the BSSB to control the throughput of the $79 trigger in generating the $79 request.

Module Location: $05 N1 (Switchyard)
Unique PAL(s): 06418T

Construction Notes:

  1. Float pins 7 and 9 of IC #16.
  2. Float pin 13 of IC #17.
  3. Remove 100-ohm resistors at IC #9 pins 6,7,8 & 9.
  4. Remove 100-ohm resistor at IC #11 pin 3
  5. Wire 17-14 (S3) to 17-13 (Gate 3 out)
  6. Wire 18-19 (P1) to 9-8 (S1).
  7. Wire 18-18 (P2) to 9-9 (R1).
  8. Wire 18-17 (P3) to 9-6 (S2).
  9. Wire 18-16 (P4) to 9-7 (R2).
  10. Wire 18-14 (P6) to 24-8 (Gate 5 out)
  11. Wire 18-12 (P8) to 24-5 (Gate 6 out)
  12. Wire 11-3 (Gated input 1) to 11-11 (Gated input 2)

I/O Wiring: RG58s with Lemo termination:
1RTCLK Input
4R$79 Trigger Input
6RBES Input
8R$79 Request Output
9R$1F Request Output
10R$1E Request Output
13R$28 Request Output
14R$0E Request Output
13LBSSB $79 Permit Input

Version 12.0 3-25-02

This version has been created for John Reid. Gate 1 is set by TCLK $2D and reset by MI reset events $20, 21, 23, 29, 2A, 2B, or $2E.
Module Location:MI $93 N11
Unique PAL(s):06418V.ABL
  1. Pull input terminating 100ohm resistors for S1 and R1(IC9 pins 8,9).
  2. Wire P1 to 9-8.
  3. Wire P2 to 9-9.

Version 13.0 5-08-03

This version has been created for Eric Prebys. Gates 1 and 2 are set by TCLK $11 or $12 and reset by a $53 event qualified by a $1D to $1F interval.
Module Location: BSTR $30 N23
Unique PAL(s):06418X.ABL
  1. Pull input terminating 100ohm resistors for S1 and R1(IC9 pins 8,9).
  2. Wire P1 to R1.
  3. Wire P2 to S1.
  4. Pull pin 7 IC #17
  5. Add jumper wire from ICs 15-5;21-5,6;25-5,6;4-8;26-8 to ICs 15-9;21-8,9; 25-8,9;4-9;26-9.

Version 14.0 2-23-05

This version was created at the request of John Reid to provide control for both Injection Paraphasing and 8-GeV Bunch Rotation in the Booster. While Injection Paraphasing is required on all booster beam cycles, bunch rotation is expected to only be used on cycles intended for slip stacking in the Main Injector (presently $14 & $19).

Gate 1 provides the Injection Paraphase trigger for the Booster rf system (input C377 timers referenced to $10).

Gate 2 provides the 8-GeV Bunch Rotation trigger for the rf.

These two signals are combined and output to the rf hardware via the Gate 4 out.

Gate 3 provides a control gate to the rf system to allow/inhibit the bunch rotation on a given booster cycle.

Three gates have sets and resets wired to two adjacent C377 timing modules. Gate 4 is the ‘or’ of Gate 1 and Gate 2. Gate 3 is set by Ch4-7 of a C377 and reset by Ch3 of the same timer.

Modifications include pulling pin 4 of chip 17 and removing chip 15. Remove pull-up on 19-10. Wire 15-9 to 15-8. Wire 15-5 to 19-10. Wire 19-8 to 15-2.

Module Location:$90 N6 (Booster)
Unique PAL(s):none

Version 15.0 5-25-05

This version was created at the request of Dave Vander Meulen to provide control for DRF1. Set1 is wired (on I/O connector)to all Sets and is sourced from a C377 in $54 N Chan... 8 Resets are wired individually to a C377 in $54 N Chan... 8 outputs are cabled to Nim modules at the top of rack... Modifications include 100ohm terminations removed from all Reset inputs.

Module Location: $54 N13 (Pbar)
Unique PAL(s): none

Version 16.0 10-Nov-2005

This version was created at the request of Jim Crisp to provide a scope trigger for recycler instrumentation. Four gates are utilized. Timing channels provide the gate sets and resets. The four gate outputs are wire-ored on the card and buffered using gated output 1. 4 Sets and resets are wired individually to a C377 in $90 N8.

377 Channel064 Input
0Set 1
1Reset1
2Set 2
3Reset 2
4Set 3
5Reset 3
6Set 4
7Reset 4

Module Location: $90 N9 (Main Injector)
Unique PAL(s): none
Modifications:Remove U7, U10, U14 & U15.
Remove pullups from U19 pins 4, 10 & 13.
Connect U17 pin 9 to U19 pin 9.
Connect U17 pin 7 to U19 pin 10.
Connect U17 pin 13 to U19 pin 12.
Connect U17 pin 4 to U19 pin 13.
Connect U19 pin 8 to U19 pin 5.
Connect U19 pin 11 to U19 pin 4.
Pull U19 pin 6 and U11 pin 9 and connect the floating pins together.
Connect U11 pin 8 and U23 pins 5&6.

Use Gated Output 2 (9R) for output to scope.

Version 17.0 21-Jun-2006

This version has been created for NuMI for generation of the TCLK $AE event. Gate 1 is set by TCLK $8D and reset by a $25, $26 or $AE. Gated in 1 is a C377 channel and Gated out 1 is the $AE event request.

Module Location: $05 N6 (TCLK)
Unique PAL(s): 06418Y
Modifications:Connect P7 to S1
Connect P8 to R1

Version 18.0 10-30-07

This version has been created at the request of Chris Jensen for generation of timing pulses for the MI injection gap clearing kicker (I:KPS1D).

Module Location: $05 N6 (TCLK)
Unique PAL(s): none
Modifications: Pull input terminating 100ohm resistors for S2, S3, R2 &R3 (IC9 pins 4,5,6,7).
Wire S1 to S2 and S3.
Wire R1 to R2 and R3
Remove ICs at locations 7,10,14
There is no need for TCLK to this module.

Version 19.0 5-28-08

This version has been created for Kent Triplett. Gate 1 is set by TCLK $11, $12 or $1D and reset by a $53 event qualified by a $0E to $1F interval. It is used to drop the Booster permit during a series of booster events when there is no beam in the first cycle.

Module Location:$80 N5 (Booster)
Unique PAL(s): 06418Z2
Modifications: Pull input terminating 100ohm resistors for S1 and R1(IC9 pins 8,9).
Wire P1 to R1.
Wire P2 to S1.

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