The CAMAC 064 module is a general-purpose gate and gating card that can be used in a variety of ways. Eight gates are provided. The first four gates can also modulate externally applied signals. Gate sets and resets are normally applied to the I/O. The module also has TCLK facility and provision for two PALs that can also provide set and reset functions. Discrete wire jumpers are necessary to implement the TCLK option. The TCLK decoder PALs are located at IC positions #18 and #22. The front panel and rear I/O gate outputs are driven by separate drivers. Upon power up or clear command, all gates are toggled to the off state.
There is also capability for directly outputting TCLK events.
Ver 0.0 | PBAR $13 N8
PBAR $55 N3 TCLK $01 N3 MI $72 N14 MI $7F N7 MI $90 N18 MI $92 N15 MI $92 N17 MI $93 N10 MI $93 N12 MI $93 N21 MI $F3 N18 |
Ver 0.1 | MI $E1 N10 |
Ver 1.0 | MI $13 N15 |
Ver 1.7 | MI $10 N12 |
Ver 5.0 | BSTR $92 N5 |
Ver 6.0 | BSTR $92 N7 |
Ver 7.4 | MI $7E N4 |
Ver 7.5 | BSTR $92 N9 |
Ver 10.0 | PBAR $1D N21 |
Ver 11.0 | TCLK $05 N1 |
Ver 11.1 | TCLK $05 N7 |
Ver 12.0 | MI $93 N11 |
Ver 13.0 | BSTR $30 N23 |
Ver 14.0 | BSTR $90 N1 |
Ver 15.0 | BSTR $90 N5 |
Ver 16.0 | MI $7F N9 MI $90 N9 |
Ver 19.2 | BSTR $80 N5 |
Ver 21.0 | TCLK $05 N6 |
Ver 22.0 | MI $92 N14 LLRF Test Stand |
Ver 22.1 | MI $1B N4 MI $3B N7 |
Ver 23.0 | MI $5C N21 |
Ver 24.1 | MI $94 N5 |
Module Location: | Many (list to follow) |
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Module Location: | MI $E1 N10 (MiniBooNE) |
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No TCLK or IC18. Chip#19 is 74LS00
Module Location: | MI $13 N15 |
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The two terminating resistors at IC #9-8 and #9-9 should be removed. Discrete wires should be added from IC #18-19 to #9-8 (P1 to S1) and from #18-18 to #9-9 (P2 to S2). The I/O connector should be wired for TCLK Input and two Gate 1 Output connections.
Module Location: | None Installed |
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Unique PAL(s): | 06418K.ABL |
NOTE: | MKS90 needs to fire on at least one $12 cycle before a Booster beam cycle to operate properly. The developed enable gate can clearly inhibit or allow $12 cycle firings depending on their exact placement in the time line relative to the beginning of a Main Ring ramp. |
The kicker thyratron firing enables are provided by Gates 1, 2, 3 and 4. Gate 1 enables the Programmable RF Delay Module associated with the thyratron firing trigger for K1A. Gate 2 enables the Programmable RF Delay Module associated with the thyratron firing trigger for K1B. Gate 3 enables the Programmable RF Delay Module associated with the thyratron firing trigger for K1C. Gate 4 is available as a spare enable with the same functionality of Gates 1, 2 and 3.
All of the thyratron firing trigger gates are set by the OR of TCLK event $13 $14 $15 $16 $19 and $1C and are reset by the OR of events $12 $17 $1D and $22.
The PFL triggers for the MI-10 Kickers are provided by Gates 5, 6, 7, and 8.
Gate 5 supplies the PFN trigger for kicker K1A. Gate 6 supplies the PFN trigger for kicker K1B. Gate 7 supplies the PFN trigger for kicker K1C. Gate 8 is available as a spare PFN trigger with the same functionality of Gates 5, 6, and 7. The PFN triggers are pulses made from TCLK event $1F anded with the thyratron trigger gate.
This module was installed to prevent MI-10 kickers from firing on TCLK event $1F associated with the Booster Beam Cycle marked by TCLK event $17. This version additionally provides gating so that the PFNs aren't triggered by the TCLK event $1F associated with the TCLK event $17.
Module Location: | None Installed |
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Unique PAL(s): | 06418W.ABL (located at IC#18 and IC#22) |
NOTE: | The MI-10 kickers K1A, K1B, K1C may receive multiple triggers without having a tripped status. However, when they receive a PFN trigger a thyratron fire trigger must follow it. |
Construction Details
For IC#9,
For IC#8
The two terminating resistors at IC #9-8 and #9-9 should be removed. Discrete wires should be added from IC #18-19 to #9-8 (P1 to S1) and from #18-18 to #9-9 (P2 to S2). The I/O connector should be wired for TCLK Input and two Gate 1 Output connections.
The RRBS $A7 request is generated by Gate 8 out.
The MIBS $77 request is generated by Gate 7 out.
Gated output 1 is used to send BES to the fiber repeaters.
Module Location: | MI $94 N5 |
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Unique PAL(s): | 06418W.ABL ,06422C.ABL |
Construction Details
For IC#9, (this is a leftover from V1.66,MI10 Kickers)
For IC#8, (this is a leftover from V1.66,MI10 Kickers)
The two terminating resistors at IC #9-8 and #9-9 should be removed. Discrete wires should be added from IC #18-19 to #9-8 (P1 to S1) and from #18-18 to #9-9 (P2 to R1). The I/O connector should be wired for TCLK Input and two Gate 1 Output connections.
The kicker thyratron firing enables are provided by Gates 1, 2, 3 and 4. Gate 1 enables the Programmable RF Delay Module associated with the thyratron firing trigger for K1A. Gate 2 enables the Programmable RF Delay Module associated with the thyratron firing trigger for K1B. Gate 3 enables the Programmable RF Delay Module associated with the thyratron firing trigger for K1C. Gate 4 is available as a spare enable with the same functionality of Gates 1, 2 and 3.
All of the thyratron firing trigger gates are set by a $BF followed by the OR of TCLK event $13 $14 $15 $16 $19 and $1C and are reset by the OR of events $12 $17 $1D $22 and $BE.
The PFL triggers for the MI-10 Kickers are provided by Gates 5, 6, 7, and 8.
Gate 5 supplies the PFN trigger for kicker K1A. Gate 6 supplies the PFN trigger for kicker K1B. Gate 7 supplies the PFN trigger for kicker K1C. Gate 8 is available as a spare PFN trigger with the same functionality of Gates 5, 6, and 7. The PFN triggers are pulses made from TCLK event $1F anded with the thyratron trigger gate.
This module was installed to prevent MI-10 kickers from firing on TCLK event $1F associated with the Booster Beam Cycle marked by TCLK events $17 and $1D or Booster transfers to Recycler.
Module Location: | MI $10 N12 |
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Unique PAL(s): | 06418EE.ABL (located at IC#18 and IC#22) |
NOTE: | The MI-10 kickers K1A, K1B, K1C may receive multiple triggers without having a tripped status. However, when they receive a PFN trigger a thyratron fire trigger must follow it. |
Construction Details
For IC#9,
For IC#8
The two terminating resistors at IC #9-8 and #9-9 should be removed. Discrete wires should be added from IC #18-19 to #9-8 (P1 to S1) and from #18-18 to #9-9 (P2 to S2). The I/O connector should be wired for TCLK Input and two Gate 1 Output connections.
Two copies of this version have been created for Howie Pfeffer to facilitate the generation of triggers for a fast digitizer system using the DSP 2610 module at both A0 and D0 locations for analyzing QXR at a quench during Tevatron flat-top.
The unique features of these modules are as follows
Module Location: | $1A N4 and $1D N6 (Tevatron) |
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Unique PAL(s): | 06418A.ABL P1 = /$07 P2 = /$42 P3 = $45 P4 = $46 P5 = $4E |
Construction Notes:
This version has been created for Mike Church as a facility to gate off the high voltage for the E760 experiment when beam is thought to be on its way from either Main Ring or Booster. All available gates are driven. The last four of the gates are complements of the first four since nobody is exactly sure of what they really want.
Gates 1 through 4 are set by TCLK event $52 (Permitted Beam) on a P-Bar scenario and are reset by event $53 (Inhibited Beam) on a P-Bar scenario. Gates 5 through 8 are the complements of Gates 1 through 4.
A P-Bar scenario is loosely defined as a $17 cycle preceded by an $8A, or by a $14 or $16 cycle preceded by a $29 or $2D or $2E Main Ring cycle. The Booster cycle flags are reset by $11. The Main Ring cycle flags are reset by $22.
All sixteen 100 ohm terminating resistors should be removed from the inputs of ICs #8 and #9.
Three wires are added between the PALs at locations #18 and #22 as follows: #18-12 to #22-14, #18-17 to #22-15, and #18-19 to #22-16.
Also add discrete wires as follows: IC #22-17 to #8-3,5,7,9 and #9-2,4,6,8; and IC #22-18 to #8-2,4,6,8 and #9-3,5,7,9.
Module Location: | None Installed |
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Unique PAL(s): | 06418G.ABL and 06422A.ABL |
This version has been created for Stan Tawzer and Phil Martin as a means of automatically selecting Mountain Range Box triggers for Main Ring and Tevatron beam displays. When both the local and remote TAB and TAC controls are false, control is facilitated by the 064 gates.
Gate 1 (TAB) serves as TAB control for the Main Ring display. This gate is set by TCLK event $8E during a Main Ring $29 cycle. They are normally reset by TCLK events $20,$21, $26, $2A, $2B, $2D, $2E, $8D, or $8F.
Gate 2 (TAC) serves as TAC control for the Main Ring display. This gate is set by TCLK event $8F during a Main Ring $29 cycle. They are normally reset by TCLK events $20, $21, $26, $2A, $2B, $2D, $2E, $8D, or $8E.
Gates 3 and 4 are similar to Gates 1 and 2 respectively.
Gate 5 is provided for the Sampled Bunch Display system built by Doug Howard. It is set by the wire-or of two 377 timing channels: T:SBDTRG from $85 N14 A(0), and T:SBDT20 from $85 N14 A(7). Gate 5 is reset by TCLK event $26.
All of the 100 ohm input terminating resistors should be removed from the gate set and reset inputs of IC #9 (pins 2 through 9) and from IC #8-9. Add discrete wires as follows: #18-19 to #9-4 and #9-8 (S3 and S1); #18-18 to #9-2 and #9-6 (S4 and S2); #18-17 to #9-5 and #9-9 (R1 and R3), #18-16 to #8-9 (R5); and #18-15 to #9-3 and #9-7 (R2 and R4).
The I/O connector should be wired for TCLK input and for all Gate Outputs.
Module Location: | None Installed |
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Unique PAL(s): | 06418H.ABL |
This version has been created for Barry Barnes to satisfy various gating requirements for the Booster Low Level System in the East Gallery. This is a stock card without any special modifications or unique PALs. The TCLK Decoder chip at IC position #14 and the PALs at IC positions #18 and #19 need not be installed at this time.
Four gates are utilized. Timing channels provide the gate sets and resets. Gates 3 and 5 and Gates 4 and 6 have shared sets and resets. This sharing is accomplished by cross-wiring the sets and resets for these gates on the IO connector.
Module Location: | BSTR $92 N5 |
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Unique PAL(s): | none |
This version has been created for Barry Barnes to satisfy various gating requirements for the Booster Low Level System in the East Gallery. This is a stock card without any special modifications or unique PALs. The TCLK Decoder chip at IC position #14 and the PALs at IC positions #18 and #19 need not be installed at this time.
Only Gate 1 is utilized. Timing channels provide the gate sets and resets.
Module Location: | BSTR $92 N7 |
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Unique PAL(s): | none |
This version has been created for Barry Barnes to satisfy various gating requirements for the Booster Low Level System in the East Gallery.
Two gates are utilized. Timing channels are used to provide the set and reset for Gate 3. Gates 1 and 2 are set and reset by TCLK events.
Gated Outputs #1 and #2 are used to provide certain TCLK events to a rf switch module which determines which rf signal (Booster rf or Main Ring rf) is applied to the BBDLY module. The rf switch and BBDLY modules are both located in a NIM bin in Rack BLLRF-3.
Remove the 100-ohm terminating resistors from the Gate 1 and 2 Set and Reset inputs - IC #9 pins 6, 7, 8, and 9.
Add discrete wires as follows:
Module Location: | None Installed |
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Unique PAL(s): | 06418L.ABL |
Module Location: | MI $7E N9 |
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Unique PAL(s): | 06418M.ABL |
This version updates Version 7.3
Gate 1 is for Anode and Cascode curves and comes on at the 2nd $12 event.
Gate 2, for the Bias Supplies, comes on early with $08.
It also generates certain TCLK events which drive Gated Outputs #1 and #2 to control the applied rf to the BBDLY NIM module.
Module Location: | BSTR $92 N9 |
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Unique PAL(s): | 06418U.ABL |
This version has been created for Bill Miller to satisfy gating requirements for the MRRF Control Room area. Four gates are utilized. Gates 1 and 2 are set and reset by TCLK events $2A and $26 respectively. Gates 3 and 4 are set and reset by TCLK events $2B and $26 respectively. Gate #1 is used by a NIM module to switch a beam pick-up signal from protons to p-bars on a $2A cycle. This is really the only Gate used at this time. The other gates are provided for convenience.
Remove the 100-ohm terminating resistors from the Gate 1, 2, 3 and 4 Set and Reset inputs - IC #9 pins 2 through 9. Add discrete wires as follows:
Module Location: | None Installed |
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Unique PAL(s): | 06418E.ABL |
This version has been created for Dave Johnson to satisfy the need of multiplexing video signals to a VCR in the Main Control Room at the library console. Gates 1 through 4 are used to control mux address lines valued at 1, 2, 4, and 8. At this time, only three video channels are switched. The truth table is as follows:
G4 | G3 | G2 | G1 | Chan | Description |
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0 | 0 | 0 | 0 | 0 | Accumulator "Jello" Display |
0 | 0 | 0 | 1 | 1 | AP-10 Mountain Range - P-Bar Extraction |
0 | 0 | 1 | 0 | 2 | MR/TEV Mountain Range - Misc Displays |
Chan 0 is set by TCLK events $9A or $2A which occur during a $C1 to $42 Flag.
Chan 1 is set by TCLK event $94 (MRBS $7A) which occurs during a $C1 to $42 Flag.
Chan 2 is set by TCLK event $25 which occurs during both a $C1 to $42 Flag and a $2A to $26 Flag. Chan 2 is also set by event $2B - but not if the $2B occurs while a $9A to $2A Flag is asserted. Additionally, Chan 2 will remain selected when the $C1 to $42 flag is unasserted.
The Gate 8 front panel LED has also been wired to the complement of the $C1 to $42 Flag to indicate its presence (LED ON when Flag is asserted).
Remove the 100 ohm terminating resistors from the Gate 1 thru Gate 4 Set and Reset inputs at IC #9 - Except for the Set input for Gate 3 (#9-4).
Add discrete wires as follows:
Jim Engelbrecht has details of connector wiring of the video multiplexer.
Module Location: | None Installed |
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Unique PAL(s): | 06418I.ABL 06422B.ABL |
This version has been created for Jim Crisp to provide gates for the Main Ring Slow and Super Dampers at MRRF. This is a stock card without any special modifications or unique PALs. The TCLK Decoder chip at IC position #14 should be installed nonetheless. PALs at IC positions #18 and #22 are not to be installed at this time.
Four gates have sets and resets wired to two adjacent 377 timing modules. Gate 1 is assigned to the Main Ring Horizontal Slow Damper. Gate 2 is assigned to the Main Ring Vertical Slow Damper. Gate 3 is assigned to the Main Ring Super Damper. Gate 4 is wired to timing channels but is currently not assigned. Each of these gates has two timing channels outputs wired-or'd to the set input, and two timing channels wire-or'd to the reset input.
Module Location: | None Installed |
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Unique PAL(s): | none |
This version has been created to replace the gating functions of
the LBOE module. Gates 1 and 2 control the throughput of BES to
generate requests for TCLK $1E and $1F respectively. iGate 3 uses
the Main Injector permit to control the throughput of the $79 trigger
in generating the $79 request.
Gate 5 was used to generate the $0E request.
Gate 6 was used to generate the $28 request.
Gate 1 ($1E generation) is set by a $12 and reset by any booster
reset, $11 or $1E.
Gate 2 ($1F generation) is set by any booster reset and cleared by $11, $12
or $1F.
Module Location: | TCLK $05 N1 |
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Unique PAL(s): | 06418T |
Construction Notes:
I/O Wiring: RG58s with Lemo termination:
1R | TCLK Input |
4R | $79 Trigger Input |
6R | BES Input |
8R | $79 Request Output |
9R | $1F Request Output |
10R | $1E Request Output |
13R | $28 Request Output (No longer used) |
14R | $0E Request Output (No longer used) |
13L | MI Beam Permit Input |
This version has been created to generate requests for TCLK $28 AND $E4. The wiring is the same as version 11.0. Gates 1 and 2 are unused Gate 3 uses the Recycler permit to control the throughput of the $B2 trigger in generating the $B2 request.
Module Location: | TCLK $05 N7 |
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Unique PAL(s): | 06418CC |
Construction Notes:
I/O Wiring: RG58s with Lemo termination:
1R | TCLK Input |
4R | $B2 Trigger Input |
8R | $B2 Request Output |
13R | $28 Request Output |
14R | $E4 Request Output |
13L | RR Beam Permit Input |
Module Location: | MI $93 N11 |
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Unique PAL(s): | 06418V.ABL |
Module Location: | BSTR $30 N23 |
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Unique PAL(s): | 06418X.ABL |
Gate 1 provides the Injection Paraphase trigger for the Booster rf system (input C377 timers referenced to $10).
Gate 2 provides the 8-GeV Bunch Rotation trigger for the rf.
These two signals are combined and output to the rf hardware via the Gate 4 out.
Gate 3 provides a control gate to the rf system to allow/inhibit the bunch rotation on a given booster cycle.
Three gates have sets and resets wired to two adjacent C377 timing modules. Gate 4 is the or of Gate 1 and Gate 2. Gate 3 is set by Ch4-7 of a C377 and reset by Ch3 of the same timer.
Modifications include pulling pin 4 of chip 17 and removing chip 15. Remove pull-up on 19-10. Wire 15-9 to 15-8. Wire 15-5 to 19-10. Wire 19-8 to 15-2.
Module Location: | BSTR $90 N1 |
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Unique PAL(s): | none |
Module Location: | None Installed |
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Unique PAL(s): | none |
377 Channel | 064 Input |
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0 | Set 1 |
1 | Reset1 |
2 | Set 2 |
3 | Reset 2 |
4 | Set 3 |
5 | Reset 3 |
6 | Set 4 |
7 | Reset 4 |
Module Location: | MI $7F N9 MI $90 N9 |
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Unique PAL(s): | none |
Modifications: | Remove U7, U10, U14 & U15.
Remove pullups from U19 pins 4, 10 & 13. Connect U17 pin 9 to U19 pin 9. Connect U17 pin 7 to U19 pin 10. Connect U17 pin 13 to U19 pin 12. Connect U17 pin 4 to U19 pin 13. Connect U19 pin 8 to U19 pin 5. Connect U19 pin 11 to U19 pin 4. Pull U19 pin 6 and U11 pin 9 and connect the floating pins together. Connect U11 pin 8 and U23 pins 5&6. Use Gated Output 2 (9R) for output to scope. |
Module Location: | None Installed |
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Unique PAL(s): | 06418Y |
Modifications: | Connect P7 to S1 Connect P8 to R1 |
Module Location: | None Installed |
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Unique PAL(s): | none |
Modifications: | Pull input terminating 100ohm resistors for S2, S3, R2 & R3 (IC9 pins 4,5,6,7).
Wire S1 to S2 and S3. Wire R1 to R2 and R3 Remove ICs at locations 7,10,14 There is no need for TCLK to this module. |
Module Location: | Replaced with V19.2 |
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Unique PAL(s): | 06418Z3 |
Modifications: | Pull input terminating 100ohm resistors for S1 and R1(IC9 pins 8,9).
Wire P1 to R1. Wire P2 to S1. |
This module replaces version 19.1.
Module Location: | BSTR $80 N5 |
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Unique PAL(s): | 06418Z3 |
Modifications: | Pull input terminating 100ohm resistor for R1 (IC9 pin 9).
Wire P1 to R1. |
Module Location: | None Installed |
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Unique PAL(s): | none |
Modifications: | Pull input terminating 100ohm resistors for S2, S3, S4, R2, R3 & R4 (IC9 pins 2,3,4,5,6,7).
Wire S1 to S2, S3 & S4 (17L, 15L, 13L & 11L) Wire R1 to R2, R3 & R4 (18L, 16L, 14L & 12L) Cut traces going to U15 pin 4 & 13 Connect U15 pins 4, 10 & 13 Remove ICs at locations U7, U10 & U14 Connect U5 pin 11 to ground There is no need for TCLK to this module. |
Module Location: | TCLK $05 N6 |
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Unique PAL(s): | 06418AA |
Modifications: | Wire P1 to Gated Out 1
Wire P2 to Gated Out 2 |
Module Location: | MI $92 N14 LLRF Test Stand (Transfer Gallery Upstairs) |
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Unique PAL(s): | 06418BB |
Modifications: | Wire P1 to S1
Wire P2 to R1 Wire P3 to S2 Wire P4 to R2 |
Module Locations: | MI $1B N4 MI $3B N7 |
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Unique PAL(s): | 06418DD |
Modifications: | Wire P1 to S1
Wire P2 to R1 Wire P3 to S2 Wire P4 to R2 |
Module Location: | MI $5C N21 |
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Unique PAL(s): | None |
Modifications: | Wire U21 pin 10 to U11 pin 3 (Gate 1 out to Gated in 2) |
The RRBS $A7 request is generated by Gate 8 out.
The MIBS $77 request is generated by Gate 7 out.
Gated output 1 is used to send BES to the fiber repeaters.
Module Location: | MI $94 N5 |
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Unique PAL(s): | 06418W2.ABL ,06422C.ABL |
Construction Details
The I/O connector should be wired for TCLK and BES Input and REQ-MIM77 REQ-RRA7 and BES out
The RRBS $A7 request is generated by Gate 8 out.
The MIBS $77 request is generated by Gate 7 out.
Gated output 1 is used to send BES to the fiber repeaters.
Module Location: | MI $94 N5 (Not yet) |
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Unique PAL(s): | 06418W2.ABL ,06422D.ABL |
Construction Details
The I/O connector should be wired for TCLK and BES Input and REQ-MIM77 REQ-RRA7 and BES out