The first 16 memory locations (000-00F) are allocated to data table starting addresses. Memory location 000 is assigned to the INITIALIZE cycle data table and 001-00F to SEQUENCE cycle data tables. The minimum starting address for any data table is 010.
The generator's program address register is always reset to a starting address at the occurence of the INITIALIZE or SEQUENCE input.
| F(20)A(0) | Load CAMAC R/W address reg W16=0: Allow inc W16=1: Inhibit inc W10-1: MSB-LSB Address (1K) |
|---|---|
| F(16)A(0) | Load CAMAC write register with Data W24-1 Initiate memory write from indicated address, inc R/W adr reg at end of write if allowed. |
| F(0)A(0) | Read CAMAC read register Initiate memory rad from indicated address, inc R/W adr reg at end of read if allowed. |
| F(4)A(0) | Read module status R1=1: Generator on R2=1: Clock overflowed (070 only) |
| F(6)A(0) | Read module number 070 or 071 |
| F(9)A(0) | Clear module, Immediate off |
| F(24)A(0) | Synchronous off Generator off at next INIT or SEQ |
| F(26)A(0) | Synchronous on Generator on at next INIT or SEQ |
Note: For doing sequential reads (F(0)'s) from the R/W reg allowed to increment, the first 2 F(0) operations subsequent to an F(20) operation will both transfer memory data from the address indicated by the F(20) operationi. Subsequent F(0) operations will transfer normally incremented data.
| 1L | D24 | 1R | D12 |
|---|---|---|---|
| 2L | D23 | 2R | D11 |
| 3L | D22 | 3R | D10 |
| 4L | D21 | 4R | D9 |
| 5L | D20 | 5R | D8 |
| 6L | D19 | 6R | D7 |
| 7L | D18 | 7R | D6 |
| 8L | D17 | 8R | D5 |
| 9L | D16 | 9R | D4 |
| 10L | D15 | 10R | D3 |
| 11L | D14 | 11R | D2 |
| 12L | D13 | 12R | D1 |
| 13L | 13R | ||
| 14L | 14R | ||
| 15L | Analog 1 | 15R | Analog 2 |
| 16L | /Update Data | 16R | /Update Data |
| 17L | /Output Enable | 17R | /Output Enable |
| 18L | GND | 18R | GND |