CAMAC 080 Module - PIO Interface

R.J. Ducar
July 1, 1980

Table of Contents

• Description
• CAMAC Function Codes
• Details of the 080 Module
• I/O Connector Assignments
• External Cable Assignment

^Description

The primary function of the 080 Module is to provide interface from the CAMAC environment to the ZILOG parallel interface controller (PIO). The PIO is operated in the bi-directional mode (Mode 2). Data are one byte wide (8 bits) and are wired to the A port. Port B must be set to the bit mode (Mode 3). The A handshake lines are used for data transfers from the PIO to the CAMAC module. The B lines are used for data transfers from the CAMAC module.

In addition to facilitating communications with a PIO, the module also provides one byte of static control lines and capability of reading one byte of external static input status. Four of the control lines are assigned to block transfer, on, enable, and time-out functions.

Communications with the PIO are initiated only by the host computer via the CAMAC facility. All communications are preceded by the transmission of a four byte header to the PIO which serves to classify the transaction and to verify the integrity of the data path.

Data transmissions to the PIO are buffered by a 192 byte FIFO. Data transmissions from the PIO are buffered by a separate 64 byte FIFO. All data transmissions are in multiples of there bytes, thus using the full capability of the CAMAC data path.

The LAM line is restrictively used to indicate device associated fault conditions. One on-board fault condition is wired to the LAM generator. Additional fault conditions may be wire to to the LAM generator from the external static input status.

The full potential of the 080 module is probably best realized by connections to two separate PIOs.

^CAMAC Function Codes

The following CAMAC function codes are accepted by the module. All of these codes return X. Return of Q is conditional for some of the codes.

C080 Function Codes

F(0)A(0)	Read output register, non block transfer reads. Q is conditional
F(1)A(0)	Read module status. Always Q
F(4)A(0)	Read output register, block transfer reads. Q is conditional
F(6)A(0)	Read module number: $50 hex Always Q
F(9)A(0)	Clear module EXPHDR is set true Always Q
F(16)A(0)	Write data to FIFO Q is conditional
F(17)A(0)	Writes bottom nibble of the control register. Always Q
F(20)A(0)	Write header register and initiate a four byte transfer to the PIO. Also clears FIFOs Q is conditional
F(22)A(0)	Writes additional header information to the PIO in groups of three bytes. Q is conditional
F(24)A(0)	Resets control register bit 5 (Disable Mode). Always Q
F(26)A(0)	Sets control register bit 5 (Enable Mode). Always Q
F(28)A(0)	Resets control register bit 6 (Off Mode). Always Q
F(30)A(0)	Sets control register bit 6 (On Mode) Always Q>

^Details of the 080 Module

1. Status. The following is a breakdown of status returned by the F(1)A(0) operation:
   MODULE STATUS R24-R17:

   R24: TTO (Transaction Time Out)

   This line is true ("1") if any one of three transactions serviced by the module took longer than 20 mSec to complete. In particular the three transactions are:

   1. Transmission of the four byte header transfer.
   2. Transmission of three bytes of write data to the PIO.
   3. Transmission of three bytes of read data to the output register.

   TTO becoming true generates a LAM

   R23: EXPHDR (EXPecting a HeaDeR)

   This line is true after a module clear or power-up sequence. It is reset by the proper receipt of an F(20) operation which will initiate a header transmission.

   R22: HDRSEQ (HeaDeR SEQuence)

   HDRSEQ is true when the transmission of a four byte header to the PIO is pending or is in progress.

   R21: FIFOWIP (write FIFO Write In Progress)

   This line true indicates that data are in the process of being transferred from the FIFO to the PIO. This signal has a natural falling latency of a few microseconds.

   R20: ORSEQ (Output Register SEQuence)

   This line true indicates that the loading of three bytes of read data from the PIO into the output register is in progress.

   R19: FIFOIR (write FIFO Input Ready)

   This line true indicates that the 192 byte write IFFO is not full and is able to accept F(22) or F(16) data for subsequent transmission to the PIO.

   R18: FIFOIR (read FIFO Input Ready)

   This line true indicates that the 64 byte read FIFO is not full and is able to accept additional data from the PIO.

   R17: ORRDY (Output Register ReaDY)

   This line true indicates that the output register has been loaded with three bytes of data and is ready to be read by the appropriate F(0) or F(4) function.

   
   External Status R16-R9:

   R16:	ES7	These static status lines from the associated PIO subsystem are assigned by the user.
   R15:	ES6
   R14:	ES5
   R13:	ES4
   R12:	ES3	The convention of good status=1 should be maintained. Any of these lines can be switched into the LAM generator
   R11:	ES2
   R10:	ES1
   R9:	ES0

   
   Control Register Status R8-R1:

   R8: CR7 = Block transfer operation mode status

   This line being true ("1") indicates that a block transfer read is anticipated or is in progress with attendant user of F(4) operations.

   R7: CR6 = On/Off Mode Status

   This line, when true, indicates the "ON" mode.

   R6: CR5 = Enable/Disable Mode Status

   This line, when true, indicates the "ENABLE" mode.

   R5: CR4 = TTO Status

   This line, when true, indicates that a transaction between the CAMAC module and the PIO subsystem has timed out.

   R4-R1: CR3-CR0 = User Defined

   These lines of the Control Register are to be assigned by the user.

2. The CR7 Bit. The CR7 bit of the Control Register, as previously mentioned, is the indication of Block Transfer active. The control of this bit is by the F(20) function with the set and reset operations being generated as follows:

   Set CR7:	F(20)A(0)*W24. In other words, values of HR byte 1 from $80 to $FF hex will set CR7.
   Reset CR7:	F(20)A(0)*!W24. In other words, values of HR byte 1 from $00 to $7F hex will reset CR7. Also reset by module CLEAR

3. Conditional Q Responses. The responses for certain CAMAC operations are conditional as follows:

   F(0) Operation:	The F(0) operation receives a Q response iff ORRDY is true and CR7 and TTO are false.
   F(4) Operation:	The F(4) operation receives a Q response iff ORRDY and CR7 are true and TTO is false.
   F(16) Operation:	The F(16) operation receives a Q response iff TTO, ORRDY, ORSEQ, and CR7 are false. Additionally FIFOIR must be true and EXPHDR must be false.
   F(20) Operation:	The F(20) operation receives a Q response iff the logic states are false for TPEND, TTO, and ORRDY.
   F(22) Operation:	The F(22) operation is subject to the same conditions as the F(16) operation, except that the state or CR7 is not checked.

4. LAM Generation
   The TTO line going true generates a module LAM. Additional conditions from the static status lines (ES7-ES0) may be wired to the LAM generator. TTO is reset only by module CLEAR.
5. Module CLEAR
   The generated CLEAR signal appropriately clears all critical circuits on the modules as well as the FIFO memories. FIFO memories are also cleared by an F(20) operation. Additionally, CLEAR will set the EXPHDR line true.
6. Additional Available Signals
   The following two signals are made available at the I/O connector of the module:

   HINT:

   Hint is either a 2uSec pulse or a level indicating the module's acceptance of the F(20) operation which loads the header register. /HINTACK is an active low signal which resets the HINT level. If /HINTACK is grounded, HINT will always be a 2uSec pulse. An onboard patching option allows the transfer of the first byte of the four byte header 2uSec after the rising edge of HINT or at the falling edge of HINT. Transmission of the 4th byte of the header will always cause HINT to be reset.

   /AIP

   A static line buffered from patch line P1 of the CAMAC dataway. A logic 1 state indicates that a machine abort is not in progress.

7. Additional Comments
   The ARDY line from the PIO is always masked out after a module reset. The mask is removed after transmission of the first 4 bytes of the header. Users should take precautions to assure that the ARDY line of the PIO is reset before the complete receipt of the header transmission. This can be accomplished by momentarily reconfiguring port A of the PIO to the bit control mode.
   The hand-wired prototypes of the 080 do not provide the F(22) function. F(16) functions must be used for transmission of additional header information, though be cautious of the "CR7 Block Transfer" gotcha. The prototypes also provide for overwriting the top nibble of the control register.

^I/O Connector Assignments

This module uses a 36 pin VIKING card-edge connector. Position allocations are as follows:

C080 I/O Assignments

1L	BP/!AIP		1R	COMMON
2L	BTR		2R	ARDY
3L	ON		3R	COMMON
4L	ENABLE		4R	!ASTR
5L	TRANS TO		5R	COMMON
6L	CR3		6R	BRDY
7L	CR2		7R	COMMON
8L	CR1		8R	!BSTR
9L	CR0		9R	COMMON
10L	HINT		10R	!HINTACK
11L	D7		11R	ES7
12L	D6		12R	ES6
13L	D5		13R	ES5
14L	D4		14R	ES4
15L	D3		15R	ES3
16L	D2		16R	ES2
17L	D1		17R	ES1
18L	D0		18R	ES0

^External Cable Assignment