Hardware Design Note xx.0

Specification for the C1045 Motor Controller Interface

M. Larwill, R. Flood

Introduction

The C1045 is a CAMAC module which is used to interface between the control system and 1 Motion Controller. This allows the C1045 to control 2 motors. Through the use of a predefined set of F and A codes the C1045 can control motors or monitor motor status. The C1045 maintains a local data pool which allows it to response to status and position reads from CAMAC within 20us.

When not responding to CAMAC interrupts or status/position interrupts from the Motion Controller the C1045 requests parameter information from the Motion Controller. A dummy parameter request is sent after every 10 parameter requests for a communications link check.

The C1045 contains a Z8002 microprocessor with 32k of RAM, 32K ROM, Z8036 CIO, ARCnet interface, and 2681j DUART. The CAMAC interface uses a 50C32 EPLD for sequencing and a PROM to select the FNA response codes. The C1045 uses a 32 data bit serial block transfer protocol to communicate with the motion controller.

C1045 Memory Configuration Table

Address	Function
0002	Z8002 initial FCW
0004	Z8002 initial PC
0006	Jump addr for ctl-c
0400	Length of NVRAM in longwords
0E0E	Machine code for breakpoint instruction
4000	Initial fcw
6802	Start of non-volatile RAM (byte-size)
8300	Start of ROM based PSAREA
8600	Start of system variables
F3FE	Top of system stack
F400	ARCnet RAM
FC00	ARCnet Com
FD00	Iobase
FD01	Cio Z8036 base
FD81	Duart base
FDCE	Camacw
FDD0	Camacl
FDE1	High speed serial link
FDF1	Tclk fifo (byte address)
FE01	Start of tclk mask ram

Memory map for the C1045 implementation:

          +-----------------------------+
   0000-- |     Code Segment            | 
          |                             | 
          |     EPROM                   | 
   7FFF-- |                             | 
          |-----------------------------| 
   8000-- |     PSAREA                  | 
          |                             | 
   8600-- |     RAM- Variable Storage   | 
          |                             | 
   F3FE-- |     System Stack            | 
          |-----------------------------| 
   F400-- |     ARCnet Ram              | 
   FBFF-- |                             | 
          |-----------------------------| 
   FC00-- |     ARCnet COM              | 
   FCFF-- |                             | 
          |-----------------------------| 
   FD00-- |     8036 CIO                | 
   FD7F-- |                             | 
          |-----------------------------| 
   FD80-- |     2681 DUART              | 
   FDBF-- |                             | 
          |-----------------------------| 
   FDC0-- |     CAMAC low word          | 
          |-----------------------------| 
   FDD0-- |     R/W CAMAC high byte     | 
          |-----------------------------| 
   FDE0-- |     R/W block transfer      | 
          |-----------------------------| 
   FDF0-- |     RD Tclk Fifo            | 
          |-----------------------------| 
   FE00-- |     R/W TCLK mask           | 
          |                             | 
   FFFF-- |  256 bytes (word boundary)  | 
          +-----------------------------+

1 RS-232 Interface

The 2681 communications chip is configured by firmware for 8 data bits, 1 stop bit, no parity, 9600 baud, no CTS/RTS handshaking. The DUART generates a non-vectored interrupt. Both channels of RS-232 are available at the rear Viking connector. RS-232 channel 1 is available at a front panel lemo. Both channels are buffered with a MAX232 interface chip. Only the transmit and recieve signals are present. The NAK/ACK protocol is handled in software.

The following table shows the allocated address space for Signetics 2681 Dual Asynchronous Transceiver(DUART)

RS-232 Address Allocation Table

Adress Function

fd81 Port A Mode registers(MR1A,MR2A)
fd83 Port A Status Register (read)
Clock Select Register (write)
fd85 Port A command register (write)
fd87 Port A RX/TX holding registers
fd89 Aux control register (write)
fd89 Input Port Change Register (read)
fd8b Interrupt mask register
fd8d Counter/Timer Upper Register
fd8f Counter/Timer Lower Register
fd91 Port B mode registers(MR1B,MR2B)
fd93 Port B status(SRB)/clock select(CSRB)registers
fd95 Port B command register
fd97 Port B Rx/Tx holding registers
reserved - duart + 24
fd9b Output Port Config. Reg.
fd9d Set Output Port Bits command (write)
Start Counter Command (read)
fd9f Reset Output Port Bits command (write)
Stop Counter Command (read)

RS-232 Address Allocation Table
Adress	Function
fd81	Port A Mode registers(MR1A,MR2A)
fd83	Port A Status Register (read) Clock Select Register (write)
fd85	Port A command register (write)
fd87	Port A RX/TX holding registers
fd89	Aux control register (write)
fd89	Input Port Change Register (read)
fd8b	Interrupt mask register
fd8d	Counter/Timer Upper Register
fd8f	Counter/Timer Lower Register
fd91	Port B mode registers(MR1B,MR2B)
fd93	Port B status(SRB)/clock select(CSRB)registers
fd95	Port B command register
fd97	Port B Rx/Tx holding registers
	reserved - duart + 24
fd9b	Output Port Config. Reg.
fd9d	Set Output Port Bits command (write) Start Counter Command (read)
fd9f	Reset Output Port Bits command (write) Stop Counter Command (read)

Z8036 CIO Counter/timer

The Z8036 is a multifunction chip which provides system counters, status and interrupt handling. The following tables show the address space allocated to the Z8036 CIO Counter/Timer and PIO Unit.

Z8036 Main Control Registers for the CIO

Address Function

fd01 Master Interrupt Control Register
fd03 Master Configuration Register
fd05 Interrupt Vector, Port A
fd07 Interrupt Vector, Port B
fd09 Interrupt Vector, Counters/Timers
fd0b Data Path Polarity, Port C
fd0d Data Direction, Port C
fd0f Special I/O Control, Port C

Z8036 Main Control Registers for the CIO
Address	Function
fd01	Master Interrupt Control Register
fd03	Master Configuration Register
fd05	Interrupt Vector, Port A
fd07	Interrupt Vector, Port B
fd09	Interrupt Vector, Counters/Timers
fd0b	Data Path Polarity, Port C
fd0d	Data Direction, Port C
fd0f	Special I/O Control, Port C

Z8036 Command, Status and Data Registers

Address Function

fd11 Command/Status, Port A
fd13 Command/Status, Port B
fd15 Command/status, Counter/Timer 1
fd17 Command/status, Counter/Timer 2
fd19 Command/status, Counter/Timer 3
fd1b Data Register, Port A
fd1d Data Register, Port B
fd1f Data Register, Port C

Z8036 Command, Status and Data Registers
Address	Function
fd11	Command/Status, Port A
fd13	Command/Status, Port B
fd15	Command/status, Counter/Timer 1
fd17	Command/status, Counter/Timer 2
fd19	Command/status, Counter/Timer 3
fd1b	Data Register, Port A
fd1d	Data Register, Port B
fd1f	Data Register, Port C

Z8036 Counter/Timer Registers

Address Function

fd21 Current Count - MSB's for CT1
fd23 Current Count - LSB's for CT1
fd25 Current Count - MSB's for CT2
fd27 Current Count - LSB's for CT2
fd29 Current Count - MSB's for CT3
fd2b Current Count - LSB's for CT3
fd2d Time Constont - MSB's for CT1
fd2f Time Constont - LSB's for CT1
fd31 Time Constont - MSB's for CT2
fd33 Time Constont - LSB's for CT2
fd35 Time Constont - MSB's for CT3
fd37 Time Constont - LSB's for CT3
fd39 Mode Specification for CT1
fd3b Mode Specification for CT2
fd3d Mode Specification for CT3
fd3f Current Vector Register

Z8036 Counter/Timer Registers
Address	Function
fd21	Current Count - MSB's for CT1
fd23	Current Count - LSB's for CT1
fd25	Current Count - MSB's for CT2
fd27	Current Count - LSB's for CT2
fd29	Current Count - MSB's for CT3
fd2b	Current Count - LSB's for CT3
fd2d	Time Constont - MSB's for CT1
fd2f	Time Constont - LSB's for CT1
fd31	Time Constont - MSB's for CT2
fd33	Time Constont - LSB's for CT2
fd35	Time Constont - MSB's for CT3
fd37	Time Constont - LSB's for CT3
fd39	Mode Specification for CT1
fd3b	Mode Specification for CT2
fd3d	Mode Specification for CT3
fd3f	Current Vector Register

Z8036 Port A Specification Register

Address Function

fd41 Mode Specification
fd43 Handshake Specification
fd45 Data Path Polarity
fd47 Data Direction
fd49 Special I/O Control
fd4b Pattern Polarity
fd4d Pattern Transition
fd4f Pattern Mask

Z8036 Port A Specification Register
Address	Function
fd41	Mode Specification
fd43	Handshake Specification
fd45	Data Path Polarity
fd47	Data Direction
fd49	Special I/O Control
fd4b	Pattern Polarity
fd4d	Pattern Transition
fd4f	Pattern Mask

Z8036 Port B Specification Register

Address Function

fd51 Mode Specification
fd53 Handshake Specification
fd55 Data Path Polarity
fd57 Data Direction
fd59 Special I/O Control
fd5b Pattern Polarity
fd5d Pattern Transition
fd5f Pattern Mask

Z8036 Port B Specification Register
Address	Function
fd51	Mode Specification
fd53	Handshake Specification
fd55	Data Path Polarity
fd57	Data Direction
fd59	Special I/O Control
fd5b	Pattern Polarity
fd5d	Pattern Transition
fd5f	Pattern Mask

CIO Ports Signal Names

Port A Port B Port C
Signal Pin Signal Pin Signal Pin

LANIRQ PA0 HRTBT PB0 RCVRES PC0
SERDY PA1 TCLK PB1 MODE32 PC1
SERDAV PA2 LAMEN PB2 TXHF PC2
CLKINT PA3 LAMREQ PB3 TXAFE PC3
CAMDIS PB4
TREQIN PB5
RXHF PB6
RXAFE PB7

CIO Ports Signal Names
Port A	Port B	Port C
LANIRQ	PA0	HRTBT	PB0	RCVRES	PC0
SERDY	PA1	TCLK	PB1	MODE32	PC1
SERDAV	PA2	LAMEN	PB2	TXHF	PC2
CLKINT	PA3	LAMREQ	PB3	TXAFE	PC3
		CAMDIS	PB4
		TREQIN	PB5
		RXHF	PB6
		RXAFE	PB7

Z8036 CIO Initialization

The Z8036 is initialized to the following settings upon reset and power on. The PCLOCK input is 5MHz. CT1 is set for 1KHz repetitive one-shot mode. It is only used to trigger CT2 which then divides CT1 by 100 to get a 10Hz vectored interrupt on vector #2 with Vector Base = 00.

CIO PORT BIT FUNCTIONS

PORT BIT SIGNAL FUNCTION

PORTC bit 3 TXAF high = transmit fifo almost full or empty (input)
bit 2 TXHF high = transmit fifo half full (input)
bit 1 MODE32 high = 32 bit block transfer mode (output)
bit 0 /RCVRES low = reset fifos (output)
PORTB bit 7 RXAFE high = rcv fifo almost full or empty (input)
bit 6 RXHF high = rcv fifo half full (input)
bit 5 /TREQIN high = ok to xmit (input)
bit 4 CAMDIS high = camac ints disabled (output)
bit 3 /LAMREQ low = request a LAM (output)
bit 2 /LAMEN low = enable LAMs (output)
bit 1 TCLK low = led on events have happened (output)
bit 0 HRTBT low = led on (output)
PORTA bit 7 /TBEB (unused) (input) Port A bit 7 high is the Tev clock input. Tev clock high generates an interrupt on vector 31
bit 6 /TBEA (unused) (input)
bit 5 /DAVB (unused) (input)
bit 4 /DAVA (unused) (input)
bit 3 CLKINT high = tev clk int (vector 16) (input)
bit 2 SERDAV high = rcv fifo int (vector 14) (input)
bit 1 SERDY high = xmt fifo has data in it (status) (input) port A bit 1 is the data available from the Motion Controller input. data available generates an interrupt on vector 18
bit 0 LANIRQ (unused) (input)

CIO PORT BIT FUNCTIONS
PORT	BIT	SIGNAL	FUNCTION
PORTC	bit 3	TXAF	high = transmit fifo almost full or empty (input)
bit 2	TXHF	high = transmit fifo half full (input)
bit 1	MODE32	high = 32 bit block transfer mode (output)
bit 0	/RCVRES	low = reset fifos (output)
PORTB	bit 7	RXAFE	high = rcv fifo almost full or empty (input)
bit 6	RXHF	high = rcv fifo half full (input)
bit 5	/TREQIN	high = ok to xmit (input)
bit 4	CAMDIS	high = camac ints disabled (output)
bit 3	/LAMREQ	low = request a LAM (output)
bit 2	/LAMEN	low = enable LAMs (output)
bit 1	TCLK	low = led on events have happened (output)
bit 0	HRTBT	low = led on (output)
PORTA	bit 7	/TBEB	(unused) (input) Port A bit 7 high is the Tev clock input. Tev clock high generates an interrupt on vector 31
bit 6	/TBEA	(unused) (input)
bit 5	/DAVB	(unused) (input)
bit 4	/DAVA	(unused) (input)
bit 3	CLKINT	high = tev clk int (vector 16) (input)
bit 2	SERDAV	high = rcv fifo int (vector 14) (input)
bit 1	SERDY	high = xmt fifo has data in it (status) (input) port A bit 1 is the data available from the Motion Controller input. data available generates an interrupt on vector 18
bit 0	LANIRQ	(unused) (input)

Timer error will generate vector 6 (because base=0)

Background Debugger

The debugger implements the following commands

HE	display help menu
SB n	set breakpoint at n
RB n	remove breakpoint at n
LB	list breakpoints
DB/W/L m n	display bytes/words/long words from m to n
MB/W/L m	modify e/word/long at location m
GO m	execute program at m
MR n	modify register n
DR	display register contents
HL	hex load (intel format)
TD	set/display time of day clock
CK	display TCLK events
EI,DI	enable/disable vectored interrupts
EC,DC	enable/disable CAMAC interrupts
32,16	32 or 16 bit serial (def=32)
R	Repeat last command

Timer Interrupt

The timer is set to interrupt at a 10Hz rate. The timer interrupt is used to perform several low-priority tasks:

Increment the time of day clock
If the previous 10Hz interrupt is not finished, return
Enable interrupts
Do heartbeat LED
If either FIFO is full, LAM
Process any data received from Motion Controller
Request next data pool item from Motion Controller
Update LAM

Any time the LAM source or mask register is changed through CAMAC, as well as every time the 10Hz timer interrupt occurs, LAM will be set or not set according to whether LAM is enabled, and the contents of the source and mask registers.

CAMAC Slave Operation

The CAMAC slave interface is implemented using a Prom for encoding the FNA code and generation of the X response combined with a 50C32 EPLD for control of the operation. The CAMAC operations are as follows.

CAMAC Timing diagrams

This module conforms to the ANSI 583-1982 spec. for dataway cycle timing as described in the standard and as shown in figures 9 and 10 on page 54.

CAMAC Write Functions

F10A0

clear bit 0 in LAM source word

F10A1

clear bit 1 in LAM source word

F10A2

clear bit 2 in LAM source word

F10A15

clear all LAM source word bits

F7A0

read LAM source register

BIT0: serial link down
BIT1: receive FIFO from Motion Controller almost full
BIT2: transmit FIFO to Motion Controller not emptying

F7A1

read LAM mask register

F16 A(X)

Set Analog Position

F17 A(X)

Set Digital Position

F18 A(X) W24-17=0-15

Set Preset Position

F18 A(X) W24-17=127

Request Readback of a Preset Position

F19 A(X) W24-17=0-8 Normal Mode

Set Motor Controller Parameters

PARAMETER	NAME
0	Motor set up value
1	Motor hold current
2	Motor run current
3	Initial velocity
4	Maximimum velocity
5	Acceleration value
6	Slow down
7	Waveform select
8	Error band

F19 A(X) W24-17=0-8 Preset Mode

Set Motor Controller Parameters

F19 A(X) W24-17=9-13

Mode Control

PARAMETER	NAME	COMMENTS
9	Operational Mode	BIT0 - normal mode
		BIT1 - preset mode
		BIT2 - slaved operation
		BIT3 - slaved operation with presets
10	Positional Mode	BIT0 - LVDT analog position
		BIT1 - external analog position
		BIT2 - steps (internal counter)
		BIT3 - shaft encoder (external counter)
11	Control Bit	1 = high speed,0 = low speed
12	# attempts	Number of attempts at desired position.
13	Averages	Number of averages for analog position.

F19 A(X) W24-17=125

Target Position Readback Request

F19 A(X) W24-17=126

Waveform Readback Request

F19 A(X) W24-17=127, PARAM#=0-8 Normal Mode

Parameter Readback Request

F19 A(X) W24-17=127,PARAM#=0-8 Preset Mode

Parameter Readback Request

F19 A(X) W24-17=127, PARAM#=9-13

Mode Control Readback Request

F20 A(X) Not Restore Mode

Set Custom Waveforms

F20 A(X) Restore Mode

Dump Next Word to Box

F21 A(X)

Set Control Word

BIT	Command
0	Stop motor immediately
1	Go to reference
2	Go to limit switch 1
3	Go to limit switch 2
4	Reset save pointer
5	Request next save value (for readback)
6	Restore mode (if set will reset pointer)
7	Save mode (if set will reset pointer)
8-15	Unused

F22A0

write LAM source register

F22A1

write LAM mask register

F24A0

disable LAM in software

F26A0

enable LAM in software

CAMAC Read Functions

F0 A(X)

Read Current Device Analog Position

F1 A(X)

Read Current Device Digital Position

F2 A(X)

Read Preset Positions

F3

an Introduction

F3 A(X)

Read Last Requested Position to Seek

F3 A(X)

Read Waveform Values

F3 A(X)

Read Motor Control Parameters

F3 A(X)

Read Mode Control Parameters

F4 A(X)

Read Status Word

BIT	Function
0	Motor stopped: 1=stopped
1	1=motor stopped at desired position
2	1=motor is at limit switch 1
3	1=motor is at limit switch 2
4	1=motor is moving toward limit switch 1
5	1=motor is moving toward limit switch 1
6	Local/Remote: 1=Remote 0=Local
7	Motor enabled: 1=enabled 0=disabled
8	Normal/Preset: 1=Preset 0=Normal
9	Slaved/Not Slaved: 1=Slaved 0=Not Slaved
10	Internal/External: 1=External 0=Internal
11	Analog/Digital: 1=Digital 0=Analog
12	not used
13	Serial link down: 1=down 0=up
14	Reset routine: 1=in reset routine 0=out of reset routine
15	Error band exceeded: 1=exceeded 0=ok

F5 A(X)

CAMAC Control Functions

F9 A(0): Activate Reset Output
Causes C1045 to be reset and assert its reset output.

C1045 to Motion Controller Protocol

The C1045 module communicates with the Motion Controller by sending it 32 bits at a time. The first byte sent generally contains a function code and a motor number. The function code tells the Motion Controller what to do with the 24 bits of data that will follow, and the motor number tells the Motion Controller to which motor the data applies. Byte 2 (the second byte received in the 32 bit packet) corresponds to CAMAC W8-W1 in the CAMAC write functions. Byte 3 corresponds to CAMAC W16-W9 in the CAMAC write functions. Byte 4 corresponds to CAMAC W24-W17 in the CAMAC write functions.

Code 8: Set Analog Position
Code 9: Set Digital Position
Code A Byte4=0-15: Set Preset Position
Code A Byte4=127: Request Readback of a Preset Position
Code B Byte4=0-8: Normal mode: Set Motor Controller Parameters
Code B Byte4=0-8: Preset mode: Set Motor Controller Parameters
Code B Byte4=9-13: Mode Control
Code B Byte4=125: Target Position Readback Request
Code B Byte4=126: Waveform Readback Request
Code B Byte4=127: Param#=0-8 Normal Mode: Parameter Readback Request
Code B Byte4=127: Param#=0-8 Preset Mode: Parameter Readback Request
Code B Byte4=127: Param#=9-13: Mode Control Readback Request
Code C Not Restore Mode: Set Custom Waveforms
Code C Restore Mode: Dump Next Word to Box
Code D: Set Control Word
Code 6: Request Motor Box Firmware Version Number
Code 69: Test Link Code

Motion Controller to C1045 Protocol

The Motion Controller communicates with the C1045 module by sending it 32 bits of data at a time. The first byte sent generally contains a function code and a motor number. The function code tells the C1045 what to do with the 24 bits of data that will follow, and the motor number tells the C1045 to which motor the data applies. Byte 2 (the second byte received in the 32 bit packet) corresponds to CAMAC W8-W1 in the CAMAC write functions. Byte 3 corresponds to CAMAC W16-W9 in the CAMAC write functions. Byte 4 corresponds to CAMAC W24-W17 in the CAMAC write functions. The following is a list of the Codes and thier use.

Code 0: Transfer Current Device Analog Position to C1045
Code 1: Transfer Current Device Digital Position to C1045
Code 2: Transfer Preset Positions to C1045
Code 3 Preset Mode: Transfer Motor Control Parameters to C1045
Code 3 Normal Mode: Transfer Motor Control Parameters to C1045
Code 3: Transfer Mode Control Parameters to C1045
Code 4: Transfer Status Word to C1045
Code 5: Transfer Next Save Word to C1045
Code 62: Transfer Firmware Version to C1045
Code 69: Test Link Response to C1045
Code 7: Transfer Last Requested Position to Seek to C1045
Code E: Transfer Waveform Values to C1045

BROADCAST DATA LINK (LAN)

This data link is capable of supporting at least 200 nodes. The network will support a length limit of not less than one mile. Nodes are able to interconnect by way of a single coax cable running from node to node. The link will use the ARCnet protocol and will employ an ARCnet Bridge to connect the Intrahouse LAN to the Interhouse network.

CONTROLLER FOR LAN

Details of the ARCnet controller can be found in the COM9026 specification but a brief description of the ARCnet follows. The ARCnet controller has access to a data buffer which appears to be 2Kx8 bits but is addressable by the Z8002 CAMAC processor in 16-bit words. The processor arbitrates with the COM chip for access to the ARCnet data buffer which is mapped into the memory space of the processor. The ARCnet controller registers are also memory mapped.

The ARCnet connects to the C1045 via a front panel lemo which must be adapted to the ARCNET RG59 coax. The 8-bit node address is jumper selectable and is frequently scanned by the COM9026.

When enabled, the COM9026 will generate an interrupt (LANIRQ*) to indicate the receipt of a message or the completion of sending a message. The COM chip will pass and receive tokens transparently to the processor. When a token is received the COM chip is allowed to transmit messages.

Reconfiguration is also transparent to the processor. If the COM chip has undergone reconfiguration, it will set the LAN status register (FC00H). The reconfiguration time and response time are jumper selectable using the ET1, ET2 lines. An ARCnet hybrid contains the cable interface discrete logic. This hybrid is protected from cable transients by an RC network.

COM Registers

The COM9026 LAN status register (FC00H)

The LAN status register bits are as follows

D7 D6 D5 D4 D3 D2 D1 D0
RI ETS2 ETS1 POR TEST RECON TMA TA

BIT READ FUNCTION
0 TA Transmitter available
1 TMA Transmit message acknowledge
2 RECON Reconfiguration occurred
3 TEST
4 POR Power on reset occurred
5 ETS1 current value of the ET1 jumper
6 ETS2 current value of the ET2 jumper
7 RI Receive Inhibited, packet received

BIT	READ FUNCTION
0	TA Transmitter available
1	TMA Transmit message acknowledge
2	RECON Reconfiguration occurred
3	TEST
4	POR Power on reset occurred
5	ETS1 current value of the ET1 jumper
6	ETS2 current value of the ET2 jumper
7	RI Receive Inhibited, packet received

COM9026 LAN Interrupt mask register (FC00H)

The LAN interrupt mask register bits are defined as follows

D7 D6-D3 D2 D1 D0
RI Unused RECON Unused TA

BIT WRITE FUNCTION
0 Transmiter Available (TA) Interrupt mask
1 Not used
2 Reconfigure (RECON) Interrupt mask
3 Not used
4 Not used
5 Not used
6 Not used
7 Recieve Inhibit (RI) interrupt mask

BIT	WRITE FUNCTION
0	Transmiter Available (TA) Interrupt mask
1	Not used
2	Reconfigure (RECON) Interrupt mask
3	Not used
4	Not used
5	Not used
6	Not used
7	Recieve Inhibit (RI) interrupt mask

The COM9026 LAN Control register (FC01H)

The COM9026 LAN control register bits are defined as follows

D7-D0
COMMAND ( see following table)

The COM9026 LAN control register accepts the following commands

WRITTEN DATA COMMAND
00000000 RESERVED
00000001 Disable Transmitter
000nn011 Enable transmit from page nn
b00nn100 Enable receive to page nn (b=1 enables broadcasts)
0000c101 Define configuration (c=1 enables long packets)
000rp110 Clear flags (p=1 clears POR r=1 clears RECON)

WRITTEN DATA	COMMAND
00000000	RESERVED
00000001	Disable Transmitter
000nn011	Enable transmit from page nn
b00nn100	Enable receive to page nn (b=1 enables broadcasts)
0000c101	Define configuration (c=1 enables long packets)
000rp110	Clear flags (p=1 clears POR r=1 clears RECON)

FRONT PANEL

LEDS

The following is a list of the front panel leds.

N

This led will be lit when the CAMAC N line is asserted for this module.

LEN

When lit indicates that LAMs are enabled.

LAM

When lit indicates that a LAM is asserted.

TCLK

This led will be lit if the TCLK is present on the CAMAC backplane.

TREQ

When the C1045 is ready to recieve data from the Serial Block transfer, this led will be lit.

RRDY

When lit indicates that the C1045 is recieving a ready signal on the RRDY input and the attached module is ready to recieve data on the serial block transfer TDATA line.

+5 POWER

Will be lit when there is +5 volt power to the module.

-5 POWER

Will be lit when there is -5 volt power to the module.

ARCNET ADDRESS

These 8 led indicate the ARCnet address of this C1045. The leds are configured as follows.

D7	D3
D6	D2
D5	D1
D4	D0

USER DEFINED

There are 4 user defined led, which are connected to the CIO chip and can be read and writen.

HEARTBEAT

This led will blink when the heartbeat routine is running.

ARCnet DSYNC active

Will be on continuously if the ARCnet has tokens passing. It will be blinking if reconfigures are ocurring. It will be off if no signal is recieved from another device.

LEMOS

Broadcast data Link: The broadcast data link (ARCnet) shall connect to the C1045 through this front panel lemo which must then be adapted to the coax.
TRANSMIT REQUEST (TREQ): Is used to indicate readiness to recieve data on the block transfer serial link.
TRANSMIT DATA (TDATA): This is the serial block transfer output data connector, which should be connected to the RDATA of another module.
RECIEVE DATA (RDATA): Normally connected to another modules TDATA to provide an input for serial block transfer data.
RECIEVE READY (RRDY): The Serial block transfer fifo is ready to recieve data.

CABLES and CONNECTORS

CAMAC contact allocation

This module conforms to the ANSI/IEEE STD 583-1982 spec. table 2 page 19 for CAMAC contact allocations of a normal station. No connection is made to the +12,-12,+24,-24,C,I,B,or Z lines.

SWITCHES and Jumpers

The module shall contain the following switches and jumpers.

LAN jumpers

The ARCnet controller logic requires the following jumpers.

ET2 ET1 RESPONSE TIME (us) RECONFIG TIME (ms)
1 1 74.7 840
1 0 283.4 1680
0 1 561.8 1680
0 0 1118.6 1680

ET2	ET1	RESPONSE TIME (us)	RECONFIG TIME (ms)
1	1	74.7	840
1	0	283.4	1680
0	1	561.8	1680
0	0	1118.6	1680

The ARCnet controller also has a jumper for ECHO loop back control; when enabled this causes the module to echo any message sent to it.

MECHANICAL SPEC

TYPICAL DATAWAY CONNECTOR

As described in Fig K4.2.2 of ANSI Std 583-1982 page 16.

CAMAC board spec.

This module complies with ANSI Std 583-1982 Mechanical specs. as shown in Fig.4 page 48 and Fig.8 page 53.

CAMAC board layout

The parts selected fit on a single wide CAMAC module. The CAMAC board has 6.57in x 11in (72 sq. in.) of usable space. The P.C. card is a 6 layer board with separate power and ground layers and 4 signal layers.

ELECTRICAL SPEC.

CAMAC dataway

This module complies with all the CAMAC signal requirements as specified in the ANSI Std 583-1982 page 39 Table 6 and all specifications as stated in the standard under section 7. Signal Standards.

Power requirements

This module conforms to ANSI Std 583-1982 as stated in section 8 Power line standards. This board needs +6 power connection and is fused at 2A. The input power connection also has bypass caps and tranzorbs for transient protection.

APPENDIX A

A.1 INITIALIZATION

A preliminary initialization program can be examined by referring to Warner::USR$DISKS:[HDWDOCS.C1045.SOFT] files C1045.Z8K, C1045.lis

A.2 INSTALLATION

This module usually should be connected to a Motor Controller box. The C1045 module must have its jumpers configured according to its specification. Note that the rear Viking connector is used for RS232 local control and may need a connector attached on the rear of the CAMAC crate.

The front panel lemos must have cables connected to the Motor controller box and one connection to the ARCnet. See the previous discription of connectors for details of how to make the interconnection.

After turning on the power the +5 power LEDs should be lit indicating that the fuses are intact and there is power on the modules. At this time the module should also have reset and performed its initialization routines. The Heart beat led should be blinking.

APPENDIX B

B.1 ELECTRONIC DRAWINGS

See Warner::USR$DISKS:[HDWDOCS.C1045]*.SCH for the PC CAPS schematics of the design. Copy all *.sch and *.sym to your area then use SYSTEM.SCH as the top level drawing.

B.2 MECHANICAL DRAWINGS

See Warner::USR$DISKS:[HDWDOCS.C1045] for available P.C. board layout and front panel drawings. The layout was done using PC CARDS.

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