The C1151 module is a single width CAMAC module which provides a precision reference voltage, control signals, and status readbacks for external devices such as power supplies.
Ramp generation is accomplished by periodic updates of the on-board D/A converter by a module-resident microprocessor executing specific software routines. Access to the module is through standard CAMAC functions across the dataway or via one of two serial ports. The serial interface consists of an RS232 port on the front panel accessible through a four-pin LEMO connector and a port on the Viking connector which can be hardware-configured as RS232 or RS485, thus allowing data rates of up to one megabits per second.
CAMAC functions use a 16-bit wide data path (R1-R16, W1-W16) on the dataway to transfer data to and from the module.
All interface signals to external devices are available on a standard CAMAC 36 pin Viking I/O connector at the rear of the module. See Appendix C for pin connections.
All peripheral devices are controlled by a 16-bit general purpose microprocessor (Zilog Z8002) at a 10 MHz clock rate. Memory support consists of jumper selectable 16/64 kbyte of EPROM and 16/64 kbyte of static RAM. A 2K x 8 bytewide non-volatile RAM provides storage of parameters for power-up conditions. Timer interrupts, bitsize I/O ports, and vector generation for other interrupt sources are supported by a Peripheral Controller (Zilog Z8036 CIO). See Appendix A for memory and peripheral devices address mapping.
The reference voltage is generated by a 16-bit D/A converter (BB-DAC703), buffered to the I/O connector through a voltage follower buffer amplifier (PMI BUF-03).
As an option, analog signals can be read back through a 12-bit, left justified A/D converter (AD574). The signal to the A/D is buffered through an input op-amp (BB-INA117).
Four control outputs are isolated through the use of reed relays (Gordos 831C-1). These provide for the power supply control functions ON, OFF, RESET, and POLARITY.
Eight sense input bits for status read are TTL inputs with 220 Ohm pull-up resistors.
Tevatron Clock decoding circuitry allows for interrupt generation by software selectable clock events. A 256 x 1 mask memory allows for enabling or disabling of events by writing a `1' or `0', respectively, to the corresponding location. All unmasked events are buffered through a 64 x 8 FIFO to prevent loss of events due to processor latency. Note that the module accepts the Tevatron Clock as decoded clock and data signals on dataway lines P1 and P2, respectively, thus requiring the presence of the new version of the Crate Controller. If not used, jumper J5 should be removed and jumper J4 set to the pull-up position.
The CAMAC dataway interface consists of two 16-bit data latches, one each for read and write functions. All valid functions requiring processor intervention generate vectored interrupts with a unique vector provided for each function. See Appendix B for interrupt vector assignments.
To ensure software execution integrity, a hardware heartbeat/reset feature is provided. Bit number one of port B (Z8036) must be toggled at a periodic rate to generate an edge which retriggers a time-out counter in the micromonitor I.C. (Dallas DS1232). Upon timing out, this chip asserts the hardware reset line.
Note: When using an in-circuit emulator to single step this module, the retrigger signal has to be moved via a jumper to the `MEMREQ' signal to prevent the occurrence of continuous resets.
The first version of the firmware emulates the C150 module as closely as possible.
Diagnostic commands may be directly input to the module by connecting a computer terminal to the front panel RS232 port. A HELP menu displays the commands which are available to assist in trouble shooting. The following commands can be executed at a terminal:
|F(0) A(0..7)||Read Level 0..7|
|F(0) A(8..15)||Read Slope 0..7|
|F(1) A(2)||Read ADC|
|F(1) A(3)||Read current T-Time|
|F(6) A(0)||Read module ID (1151)|
|F(6) A(1)||Read software version (HHLL)|
|F(6) A(3)||Read FOP status|
|F(6) A(4)||Read FOP data|
|F(6) A(5)||Read module serial number|
|F(8) A(0)||Test LAM|
|F(9) A(0)||Reset module|
|F(10) A(0)||Clear LAM|
|F(12) A(0)||Power supply reset|
|F(16) A(0..7)||Write Level 0..7|
|F(16) A(8..15)||Write Slope 0..7|
|F(17) A(0)||Write polarity relay (D=1 for reverse)|
|F(17) A(1)||Write segment switch|
|F(17) A(13)||Write LAM register|
|F(19) A(2)||Write FOP command|
|F(19) A(3)||Write FOP data|
|F(24) A(0)||Disable ramp|
|F(24) A(15)||Disable LAM|
|F(26) A(0)||Enable ramp|
|F(26) A(15)||Enable LAM|
|F(28) A(0)||Power supply off|
|F(30) A(0)||Power supply on|
Click here for endrack wiring
|3L||Reset relay||3R||Reset relay|
|6L||On relay||6R||Off relay|
|7L||On relay||7R||Off relay|
|13L||Status 5||13R||Polarity relay|
|14L||Status 2||14R||Polarity relay|
|16L||Status 1||16R||Status 0|
|17L||ADC +||17R||DAC +|
|T-Time||TCLK Event||TCLK Event Description|
|T1||$30||Switchyard Reset for Long Spill 120 GeV Extracted Beam|
|T2||$A2||Triggered off $00, used to keep module in ramp mode|
|T4||$31||Switchyard Reset for Extracted Beam Cycle|
|T5||$39||TCLK reflection of MIBS $75: 120 GeV proton extraction from MI to SWYD|
|T6||$36||Switchyard Post-Beam Sample Time|
|T7||$A7||No Beam to Experimental Areas|