Epicure Design Note 107.4
C1200 Tevatron Clock Generator
I. General Description.
The Tevatron Clock Generator (TCG) is a CAMAC resident module that provides (as the name implies) serial timing generation, using the same encoding as the Accelerator Division's Tevatron Clock Generator and most of the features of the Tevatron Clock Master source module - the Time Line Generator (TLG). The C1200 module's serial output is clocked at 10 Mbits/sec., using modified Manchester code; In the idle state continuous bits of 'zero' are transmitted to maintain phase lock in receivers using phase locked loop circuits. Each clock event consists of a single 8 bit byte, preceded by a start bit and followed by a parity bit, thus providing a potential 256 unique events. One single C1200 module will be the source for all clock signals in the beam lines and experimental areas, with multiple repeater modules distributing and restructuring the clock throughout the system.The C1200 module has two modes of operation,
a) L O C A L and
b) R E M O T E .
The C1200 Module Will Perform the Following tasks, Regardless of which mode is selected.
* Will Maintain the last cycle length in microseconds, and allow for Epicure readback. Previous Cycle time represents the total time in microseconds from one reset event to the past reset event.
* Allow readback for Current Cycle time. Current time is in micro-seconds since the previous reset event.
* Restore all Current Setup information after a power-up or a Reset. Uses a 32K x 8 bit Battery Backed RAM as the restore device.
* Store selected transmitted Events, and their Cycle times into a RAM buffer area. Will support a Maximum of 16 K. Events per Cycle. The C1200 will allow setting/resetting of a log bit. Only events which have their log bits set on (1) will be stored into this buffer table. There will be two such tables, Buffer #1 and Buffer #2, the C1200 module will toggle between these tables on alternating machine cycles. Bit 5 of the Status Register Displays which buffer is currently active, (Being written into). See Page 13 !
* A Cycle Counter will be Broadcast over Arcnet at every Reset Event. This will allow for Cycle Stamping to be implemented in the future.
* Set the LAM bit when either the Local or Remote event table becomes full.
(512 Maximum Events for Local mode, 16 Maximum Events for Remote mode.)
The C-1200 module will perform the following tasks.
* Allow the Sys-op to place the C-1200 module into the LOCAL mode, and provide a status readback. (DEFAULT/Power-Up = REMOTE.)
* Will accept all encoded Tev Clock Events using the Main ring Tev Clock as the master source.
* Programmable REMOTE Reset event. Will use any event from T-0 thru T-253.
Allow for the readback of the Remote Reset Event.
* Will re-transmit all events through a REMOTE event translation table so incoming events can be converted to other event numbers from 0 thru 255. Allow for the readback and setting of the entire translation table.
* Allow the operator to Disable/Enable the passing of any Remote TEV clock EVENTS.
* Super Impose Fake Clock Events onto the existing TEV clock from a user programmable REMOTE event table. Delay times will be in microseconds from reset. (The maximum number of REMOTE events allowed into this table will be 16).
* Sorts all Fake TEV Clock event delays into a FIFO in ascending order. FIFO will be a circular buffer Which will be reset to its beginning after every reset event.
* Allow readback of current LOCAL time in cycle. Time will be micro-seconds since last reset event.
* There will be Two REMOTE Fake TEV clock event FIFO's, One will be Active while the other will be Idle. When a request is received to either add or delete a REMOTE Fake TEV event, the idle buffer will be resorted as per the request and if the module is in the REMOTE mode a (1) will be written to register 0xB000012A. After the next Reset Event occurs the Idle buffer will become active and the active buffer will become Idle. All new changes will be performed in the current Idle FIFO.
Bit# 8 in the Status Register will Display which buffer is currently Active while Bit#0 will Display which mode is currently is selected. (See Page 13 For Status Register Info.)
The C-1200 module will perform the following tasks.
* Allow the SYS-op to place the module into the REMOTE mode.
* Generate Fake TEV clock Events from a programmable LOCAL event table with delay times in microseconds from reset. (The maximum number of LOCAL events stored into this table will be 512). The last event in this table must be a Reset event.
* There will be Two LOCAL Fake TEV clock event FIFO's, One will be Active while the other will be Idle. When a request is received to either add or delete a LOCAL Fake TEV event, the idle buffer will be resorted as per the request and if the module is in the LOCAL mode a (1) will be written into register 0xB000012A. After the next Reset Event occurs the Idle buffer will become active and the active buffer will become Idle. All new changes will be performed in the current Idle FIFO.
Bit# 8 in the Status Register will Display which buffer is currently Active, while Bit#0 will Display which mode is currently is selected. (See Page 13 For Status Register Info.)
* Programmable LOCAL Reset event. Can use any event from T-0 thru T-253. Allow for the readback of the Reset Event. NOTE: (This event number must match the final event number in the TEV clock Local event table.)
* Sorts all FAKE event delays into a FIFO in ascending order. FIFO will be a circular buffer with the last event on the stack being the reset event.
* Restore all Events delays and event numbers and event translations after power-up or Reset. Use data stored in Battery Backed RAM.
a) Processor - Intel I960CF
b) INPUTS -- 2 types of inputs.
Optical (fiber) and Cable. The module will default to the optical input. If the clock signal is removed from the optical input, the logic will detect this and automatically switch to the cable input. If both inputs are missing, the module will enable the LAM status. A Status register will be provided to inform the operator of which input is being utilized.
c) OUTPUTS -- This module will contain 2 Types of outputs, Optical (fiber) and Cable. Outputs will be connected in parallel so both signals will contain the same TEV events.
d) Front Panel LEDS
N -- Module Select
LAM -- Look at Me
LAMEN -- LAM Enable.
MODE -- Local / Remote
INPUT SELECT -- Optical / Cable
PARITY ERROR -- Parity Error
15 Hz -- 15 Hz. present
720 Hz -- 720 Hz. present
HEART BEAT -- Heart Beat
TEVCLK -- TEV Ck Present
e) Front Panel Connectors
SERIAL I/O -- RS232 serial input
CLOCK OUTPUT -- Buffered TEV clock output
f) Front Panel Push-button
RESET -- System Reset
g) Battery Backed RAM
32 K-bytes of Battery Backed RAM will be provided for downloading of previously stored events after power outage or system reset.
h) Epicure I/O
All Epicure Communications (reading & writing) will be sent as CAMAC function codes. This module will support enough CAMAC functions and sub-addresses to perform all tasks.
II. Local Mode of Operation.
This mode allows for stand alone clock generation (independent of the Accelerator Division's Tevatron Clock) from a table of times and associated clock events. Total cycle time from reset event to the following reset event is remotely programmable, as well as all other clock events as a function of time after reset.
Timing resolution in this mode shall be 1 usec with a range of 0 to 232-1, resulting in a maximum master cycle of ~ 71.582 minutes. The source for all timing generation shall be chosen and to be derived from one of two sources:
TevClock signal (preferred) 10 MHz free running oscillator.
Local oscillator; the 15 Hz event is synchronized to the line frequency via a zero crossing detector, and the 720 Hz is a function of the 15 Hz clock plus a cycle counter.
Because the 15 Hz and 720 Hz TEV events are a function of a zero crossing detector we have provided this module with the ability to disable / enable these Two LOCAL Tev events. All other Local events are generated by adding or subtracting them from the LOCAL event FIFO.
The C-1200 module will contain its own local event translation table with event delay from a pre-programmed reset event (T-0 thru T-253). This module will contain a 32-bit counter clocked at 1 MHz. This mode will utilize a circulating FIFO of sorted times and events. The FIFO will be large enough to contain a maximum of 512 different events per machine cycle. There will be two sets of FIFO's, one active and one idle. The active FIFO will contain the events which are currently being transmitted and the idle FIFO will contain new times and events which are waiting to be changed. The new events will be sorted and stored in ascending order into the idle FIFO. At the next reset event (or a forced reset) the idle FIFO will automatically switch to the Active mode, and the Active FIFO will be placed in the IDLE mode, the 32-bit cycle counter will reset to '0', and the new TEV events will begin being transmitted. If there are No new events requested when a reset event occurs the Active Buffer pointer will be reset and all previous events will be regenerated.
III. Remote Mode of Operation.
This mode is software selected. (default = Remote.)
In this mode the TCG MUST receive an external Tevatron Clock input to be functional. All decoded (received) clock events are re transmitted after passing through an event translation table. The Event Translation table allows for the suppression of Events as well as the converting of any given event into another event. This table is maintained in non-volatile memory and is remotely programmable.
Hardware timing signals such as the 15 Hz (event 0x0f) and 720 Hz (event 0x07) will be passed without modifications. Locally generated events derived from a resident timing/event state machine (see local mode) can be OR'ed with the output of the translation table, thus allowing FAKE events to be superimposed onto the Tevatron Clock. (A Maximum of 16 Remote Fake TEV clock events are allowed.)
The event translation table will be automatically loaded at power-up or reset, from previously stored events located in the Battery Backed RAM.
C1200 Memory Map
FFFE0000-FFFFFFFF : EPROM
E0000000-E007FFFF : 32 BIT S-RAM
D0000000-D001FFFF : 8 BIT S-RAM
B0000006 : 16 BIT - CAMAC Interrupt Acknowledge
B0000004 : 16 BIT - LAM ENABLE
B0000002 : 16 BIT - LAM
B0000000 : 16 BIT - CAMAC Data Buffers
B0000100-B00001FE : 16 BIT - TEV I/O REGISTERS
B0000200-B000021E : 16 BIT - FIFO COMMAND REGISTER CONTROL
B0000300 : Local 15 Hz Tev Event Enable / Disable Register
B0000302 : Local 720 Hz TEV Event Enable / Disable Register
B0008000-B000BFFE : 16 BIT - FIFO SARAM
A0000000-A0007FFF : 8 BIT - NVRAM
A0008000-A00081FF : 8 BIT - DPRAM1 - Remote TEV Translation / Enable.
A0008800-A00088FF : 8 BIT - DPRAM2 - Event Logging Enable Buffer.
A0008300-A0008307 : 8 BIT - COM20020 Arcnet Interface
A0008400-A000840F : 8 BIT - DUART
I/O Connector Definitions
The I/O connector used is of the 36-pin Viking type.
Left(L) and Right(R) are viewed from the front of the crate.
C1200 VIKING I/O SIGNAL ASSIGNMENT
VL1 - GND VR1 - GND
VL2 - TEVIN1+ VR2 - TEVIN2+
VL3 - TEVOUT SIGNAL VR3 - TEVOUT SHIELD
VL4 - N.C. VR4 - N.C.
VL5 - 5VAC VR5 - 5VAC
VL6 - N.C. VR6 - N.C.
VL7 - N.C. VR7 - N.C.
VL8 - N.C. VR8 - N.C.
VL9 - N.C. VR9 - N.C.
VL10 - N.C. VR10 - N.C.
VL11 - N.C. VR11 - N.C.
VL12 - N.C. VR12 - N.C.
VL13 - N.C. VR13 - N.C.
VL14 - N.C. VR14 - N.C.
VL15 - N.C. VR15 - N.C.
VL16 - N.C. VR16 - N.C.
VL17 - N.C. VR17 - N.C.
VL18 - ARC+ VR18 - ARC-
The RS-232 connection allows an external terminal to interface with the C1200 module. Pinouts, viewed from front, are as follows:
GND -1 | 4- GND
TX -2 | 3- RX
JP4 - FLASH ROM Program Enable/Disable
JP5 - FLASH ROM Program Enable/Disable
JP4 Installed: FLASH Programming Enabled (Default)
JP5 Installed: FLASH Programming Disabled
JP6 - 80960 Clock Mode Select
Installed: 1X clock
Removed: 2X clock (Default)
JP8 - Watchdog timer input select
Position A: Heartbeat output (Default)
Position B: 3.6864MHz clock. (Watchdog Disable)
13. PAL SOURCE FILES
The PAL source files can be found on the WARNER cluster in the [HDWDOCS.C1200.PALS] directory. The files for the CAMAC decoder chip (U5) can be found in the [HDWDOCS.C1200.PALS.CAMDEC] directory in the file C1200CAM.ZIP.
The C1200 schematic drawingS (XXXX-ED-XXXXXX / XXXX-ED-XXXXXX) can be found on the WARNER cluster in the [HDWDOCS.C1200.PCAD] directory in the file C1200A.SCH & C1200B.SCH.
1.0 PROCESSOR SECTION
Address decoding is accomplished by two chips: a 22V10 (U38) for upper address decoding, and part of an EPM5128 (U5). The 22V10 generates the select lines for the RAM and ROM banks, external I/O, and select lines for the 8 and 16 bit peripherals. The EPM5128 uses the IO8 and IO16 lines to generate select lines for the NVRAM, ARCNET interface, TEV16REG, RS232 controller, DPRAM1, DPRAM2, SARAM Chip Select, SARAM Command Chip Select and the CAMAC interface.
Address lines A23..00 are buffered with 74ALS573 transparent latches (U40, U43, U44) before they are sent to the peripherals on the board. D31..00 are likewise buffered with 74ALS645s (U27, U28, U30, U34). Write strobes for the 32bit wide RAM banks (U19, U23, U26, U29, U31, U35, U37 & U39), are generated from byte enables BE3..0 in another 22V10 (U36). This chip also generates read and write strobes for the other peripherals.
RS-232 communication is handled by a Signetics 2692 DUART (U41) and a Maxim MAX233 RS-232 interface chip (U46). The MAX233 chip converts the TTL level signals from the 2692 to +-10V signals. The 2692 is also used for front panel LED (HeartBeat) and generates a 1Khz scheduling interrupt for the processor. The 2692 communications chip is configured for 9600 baud, 8 data bits, 1 stop bit, and no parity.
ARCNET communication is via SMGs COM20200 ARCNET controller (U14) and via high level signals using the HYC9068 level shifter (U21).
The C1200 has 32Kb of Non Volatile RAM (U16). This RAM can be used to keep all setup information pertaining to this module.
1.4 TCLK Decoder
TCLK decoding is accomplished by using an EP5032 (U23) to decode the TCLK clock and data lines from the I/O Viking Connector. When the EP5032 detects a valid TCLK event, it sets the CLKDAV signal high for one TCLK cycle (50nS?) and outputs the event on TDAT7..0. The DAV signal is sent to a EPM7160 (U2) which checks if the event has been enabled. Enabling is done by setting the corresponding bit in a 256bit DPRAM memory (U17). If the event is enabled, the ACT1280 Actel EPLD writes it to a FIFO (U24). The FIFO's output ready line is connected a GAL6001 PLD which Regenerates the TEV event out to a Serial Line.
1.5 CAMAC Interface
The CAMAC interface consists of a 16bit data buffer (U6) and the CAMDEC section of the EPM5128 (U5).
1.6 External I/O
The C1200 interfaces to the outside world via the 36 pin Viking I/O connector.
1.7 FIRMWARE OVERVIEW
The FLASH EPROM in the C1200 contains two separate routines, the LOADER and the regular C1200 BSP (board support package) code. The source code for both routines can be found on the WARNER cluster in the [HDWDOCS.C1200.CODE] sub-directory.
On startup, the LOADER checks a flag in the NVRAM to determine if there is a valid C1200 program stored in the lower section of EPROM. If a valid program is found, it is loaded to RAM and executed. If no valid program is found, the LOADER continues into a load/program routine which is used to load and program new C1200 code into the FLASH EPROM. The LOADER can be invoked by writing 0x4D4B to the CAMAC write registers (F19A3) before resetting the module (F9A0).
2.0 LOAD/PROGRAM ROUTINE
The load/program routine (LOADER) implements the following commands:
D: Download Download data to be programmed
E: Erase Erase FLASH EPROM
H: Help Display this help information
P: Program Program from downloaded data
R: Run Mark EPROM as programmed, and execute
V: Version Display LOADER Version number
2.1 RS-232 INTERRUPT
The RS-232 interrupt reads a character from the UART and places it in a buffer.
2.2 ARCNET INTERRUPT
The ARCNET interrupt routine is only used to transmit / broadcast a 32bit Time value whenever a TEV reset event occures. This can be used to Time stamp machine cycles.
2.3 TICKER INTERRUPT
The ticker interrupt routine flashes the LEDs, keeps the watchdog chip from resetting the module.
2.4 DOWNLOADED CODE FORMAT
Programs downloaded and programmed into the C1200 via the LOADER must be loaded to 0xE0040000, start execution at 0xE0020000 and be in the Microtec INITDATA format, which is as follows:
0x53 - Start byte
0x43 - Copy flag
LWORD - Byte count
LWORD - Destination address
BYTE(S) - Data
0x43... - Extra program sections
0x45 - End flag
See the Microtec linker manual for information on creating an INITDATA section.
3.0 C1200 FIRMWARE OVERVIEW
The background task is an 80960 debugger. Other tasks are entered via interrupts.
On startup, the C1200 code initializes the system peripherals and sends out an ARCNET request for initialization. This request uses NTI=0x28.
3.1 BACKGROUND DEBUGGER
The debugger implements the following commands:
COMMAND ARGUMENTS DESCRIPTION.
CLS Clear Screen
DISPLAY start [end][;mode] Display Memory
DOWNLOAD [offset] Download Hex files
FILL start end value [;mode] Fill Memory block
HELP Show help
MODIFY address[;mode] Modify Memory
NODE [new value] Dsp/Set ARCNET node
RESET Reset Module
RUN [start address] Run loaded file
STATUS Display status
VERSION Show s/w version
WRITE address value [;mode] Write to memory
LORESET Lo Reset Event Value Write Local Reset
REMRESET Rem. Reset Event Value Write Rem Reset
SETMODE 1=LOCAL / 0=REMOTE Set Local remote
LOGEVENT Event #(0-255) 1=set Enable Log Event
TEVEVENT Event #(0-255) 1=set Enable Mapped Event
MAP Event # /Set to # Map Events
RDMAP Read all Rem Mapping
RDENABLE Read Event Enable
RDLOG Read Log Event Enable
SWBUF Change Active Event buffer,After Reset Event.
SWBUFI Change Active Event Buffer, (Immediately)
Available data modes:
L - Longword (32 bits) (default)
W - Word (16 bits)
B - Byte (8 bits)
While in the Modify Memory routine, the following options exist instead of entering a new value.
1. . or CR. exits
2. - backs up one address
3. = stays at current address
4. / skips to next address
3.2 RS-232 INTERRUPT
The RS-232 interrupt routine reads a character from the DUART and places it in a buffer.
3.3 CAMAC INTERRUPT
The CAMAC interrupt routine handles read operations over the CAMAC dataway for the RDMADC system as well as other read, write and control functions. A typical CAMAC interrupt does the following:
1) Read the CAMINT chip to determine the type of operation to be performed.
2) Use this value to look up the address of its routine in a lookup table.
3) Execute routine.
3.4 1KHz (TICKER) INTERRUPT
The 1KHz ticker interrupt routine does the following:
1) Toggles HEARTBEAT.
4.0 SUMMARY OF SUPPORTED CAMAC FUNCTIONS
Function Code Description
F00-A00 - Read Stored Event Times Low Word , Buffer #1.
F00-A01 - Read Stored Event Times High Word , Buffer #1.
F00-A02 - Read Stored Event Number, Buffer #1 / Increment Pointer.
F00-A03 - Read Maximum Number of Stored Events, Buffer #1.
F00-A04 - Read Stored Event Times Low Word , Buffer #2.
F00-A05 - Read Stored Event Times High Word , Buffer #2.
F00-A06 - Read Stored Event Number, Buffer #2 / Increment Pointer.
F00-A07 - Read Maximum Number of Stored Events, Buffer #2.
F00-A08 - Read Local Event Table, Time Low Word.
F00-A09 - Read Local Event Table, Time High Word.
F00-A10 - Read Local Event Table, Event Number. / Increment Pointer.
F00-A11 - Read Maximum Number of Local Events Stored (0-512).
F00-A12 - Read Remote Event Table - Low Word.
F00-A13 - Read Remote Event Table - High Word.
F00-A14 - Read Remote Event Number, / Increment Pointer.
F00-A15 - Read Maximum Number of Remote Events Stored (0-15).
F01-A00 - Read Module Status (i.e. local/remote, heartbeat.)
F01-A01 - Read Previous Cycle Time (Local / Remote) Low Word.
F01-A02 - Read Previous Cycle Time (Local / Remote) High Word.
F01-A03 - Read Current Cycle Time (Local / Remote) Low Word.
F01-A04 - Read Current Cycle Time (Local / Remote) High Word.
F01-A05 - Read Current Reset Event Value
F01-A06 - Read Remote Reset Event Setting.
F01-A07 - Read Local Reset Event Setting.
F01-A08 - Read Cycle Counter (Low Word).
F01-A09 - Read Cycle Counter (High Word).
F01-A10 - Read Event storage, LOG bit / Increment Pointer
F01-A11 - Read Remote Event Translation Table / Increment Pointer.
F01-A12 - Read Remote Event Enable / Disable Status / Increment Pointer.
F02-A00 - Read 15 Hz / 720 Hz / Arcnet Broadcast Register
F06-A00 - Read Module Number.
F06-A01 - Read Software Version Number.
F06-A02 - Read FOP Status
F06-A03 - Read FOP Data
F06-A05 - Read Serial Number.
F06-A06 - Read Broadcast Enable/Disable Register
F06-A13 - Read LAM Mask.
F06-A14 - Read LAM Request Register.
F06-A15 - Read Arcnet Node Number
F08-A00 - Test LAM.
F09-A00 - Reset Module.
F10-A00 - Clear LAM.
F16-A00 - Write Cycle Counter Low Word
F16-A01 - Write Cycle Counter High Word
F16-A06 - Write Remote Reset Event Value.
F16-A07 - Write Local Reset Event Value.
F16-A08 - Add Local Event Time Low Word.
F16-A09 - Add Local Event Time High Word.
F16-A10 - Add Local Event Number (0-255) / Execute.
F16-A11 - Write Remote Translation Table Event / Increment Pointer.
F16-A12 - Add Remote Event Time Low Word.
F16-A13 - Add Remote Event Time High Word.
F16-A14 - Add Remote Event Number. (0-255)
F17-A00 - Set Pointer to Read Stored Events, Idle Buffer only.
F17-A01 - Set Pointer to Read Local Event Table (0-512)..
F17-A02 - Set Pointer to Read Remote Event Table. (0-15).
F17-A03 - Set Pointer to Read / Write Remote Translation Table
F17-A04 - Set Pointer to Read Event Storage LOG bit.
F17-A05 - Set Pointer to Read Remote Event Enable.
F18-A00 - Set event storage, LOG bit. (Event# 0 - 255)
F18-A01 - Clear event storage, LOG bit. (Event# 0 - 255)
F18-A02 - Set Remote Event Enable Bit (Event# 0 - 255).
F19-A02 - Write FOP Command
F19-A03 - Write FOP Data
F19-A06 - Set Arcnet Address
F19-A12 - Clear LAM Select Bits.
F19-A13 - Write LAM Mask.
F19-A14 - Write LAM Request Register.
F24-A00 - Enable Arcnet Broadcast Cycle Counter
F24-A01 - Disable Arcnet Broadcast Cycle Counter
F24-A02 - Enable 15 Hz Tev Event
F24-A03 - Disable 15 HZ Tev Event
F24-A04 - Enable 720 Hz Tev Event
F24-A05 - Disable 720 Hz Tev Event
F24-A15 - Disable LAM.
F26-A01 - Set To Local Mode.
F26-A02 - Set to Remote Mode.
F26-A03 - Generate Local Reset (IMMEDIATELY)
F26-A04 - Reset Cycle Counter
F26-A05 - Toggle Fake TEV Event Active Buffer
F26-A15 - Enable LAM.
5.0 DETAILED EXPLANATION OF FUNCTION CODES
Read Stored Events from Buffer #1
F17-A00 - Set Pointer to read stored events from Idle Buffer.
F00-A00 - Read Stored Event Time Low Byte
F00-A01 - Read Stored Event Time High Byte
F00-A02 - Read Stored Event Number and increment pointer
F00-A03 - Read Maximum Number of Stored Events in Idle Buffer.
Read Previous and Current Cycle Times
F01-A01 - Read Previous Cycle time. Low Word. - Total time of previous Super-Cycle
F01-A02 - Read Previous Cycle time. High Word. - Total time of previous Super-Cycle
F01-A03 - Read Current Cycle Time. Low Word. - Elapsed time from last reset event.
F01-A04 - Read Current Cycle Time. High Word. - Elapsed time from last reset event.
F24-A00 - Enable Arcnet Cycle Broadcast
F24-A01 - Disable Arcnet Cycle Broadcast
F24-A02 - Enable 15 Hz Local TEV Event
F24-A03 - Disable 15 Hz Local TEV Event
F24-A04 - Enable 720 Hz Local TEV Event
F24-A05 - Disable 720 Hz Local TEV Event
F26-A01 - Set to Local Mode.
F26-A02 - Set to Remote Mode.
F26-A03 - Send Local Reset Event.
F26-A04 - Reset Cycle Counter.
F26-A05 - Toggle Fake TEV Event Active Buffer. (Both Local and Remote Modes)
F01-A00 - Read Status. i.e. local/remote, heartbeat, input connector source.
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 * Bit 0
CounterOverflow LAMEnabled Active Logging Buffer Remote Input Missing Cable Input Active Fiber Input Active Active Event Table Full Local/Remote
1=Overflow 0=Enabled 1=Buf#2 1= Missing 1=Active 1= Active 1=Full 1=Local
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
Spare Spare Spare Spare Spare SA-RAM BufferEOB2 SA-RAM BufferEOB1 SA-RAM Buffer Select
------- ------- ------- ------- ------- 1=EOB 1=EOB 1= buffer #2
* Read/Write Register
Hardware Status Register
Returned Via F01A00
Arcnet Broadcast / 15 Hz / 720 Hz Status Register
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Broadcast 720 Hz Tev 15 Hz Tev
1 = Enable 1 = Enable 1 = Enable
BBRAM En/Dis Status Register
Returned Via F02-A00
F01-A05 - Read Current Reset Event Value.
F16-A06 - Write Remote Reset Event Number
F16-A07 - Write Local Reset Event Number
F01-A06 - Read Remote Reset Event Number
F01-A07 - Read Local Reset Event Number
Remote Translation Table
F17-A05 - Set Pointer for Reading Remote event enable bit.
F17-A03 - Set Pointer for Reading / Writing Remote translation table, Select Channel.
F16-A11 - Write Remote Translation Table Event Number and Increment Pointer.
F18-A02 - Set Remote Event Enable Bit. (Events 0 - 255)
F18-A03 - Clear Remote Event Enable Bit (Events 0 - 255)
F01-A11 - Read Remote Translation Table and increment Pointer.
F01-A12 - Read Remote Event Enable Bit and increment pointer.
Remote Event Table
F17-A02 - Set Remote Event Table Pointer for reading only. (0-15)
F00-A12 - Read Remote Event Table Time. Low Byte.
F00-A13 - Read Remote Event Table Time. High Byte.
F00-A14 - Read Remote Event Table, Event Number and increment pointer.
F00-A15 - Read Maximum Number of Remote events in Table. (0-15).
Add Remote Event From Event Table
F16-A12 - Add Remote Event Time Low Word
F16-A13 - Add Remote Event Time High Word
F16-A14 - Add Remote Event Number (0-255) / Execute
Local Event Table
F17-A01 - Set Local Event Table Pointer for reading only. (0-512)
F00-A08 - Read Local Event Table Time. Low Byte.
F00-A09 - Read Local Event Table Time. High Byte.
F00-A10 - Read Local Event Table, Event Number and increment pointer.
F00-A11 - Read Maximum Number of Local events in Table. (0-512)
Add Local Event Into Idle Event Table
F16-A08 - Add Local Event Time Low Word
F16-A09 - Add Local Event Time High Word
F16-A10 - Add Local Event Number (0-255) / Execute
Event Storage LOG bit.
F17-A04 - Set pointer for Event Storage LOG bit .
F01-A10 - Read Event Storage LOG bit, / Increment Pointer.
F18-A00 - Set Event Storage LOG bit. (Event Number 0 - 255)
F18-A01 - Clear Event Storage LOG bit. (Event Number 0 - 255)
F01-A08 - Read Cycle Counter (Low Word).
F01-A09 - Read Cycle Counter (High Word).
F16-A00 - Write Cycle Counter (Low Word)
F16-A01 - Write Cycle Counter (High Word)
5.1 F6 A0 : READ MODULE ID
Returns a value of 1200 for this module.
5.2 F6 A1 : READ SOFTWARE VERSION
D15:D08 - Major Rev
D07:D00 - Minor Rev
5.3 F6 A5 : READ MODULE SERIAL NO
5.4 F6 A13 : Read LAM Mask
Status when bit set:
D15 - Set LAM Bit
D14:D08 - Unused
* D07 - FAKE TEV clock event End of BUFFER #2 Reached
* D06 - FAKE TEV clock event End of BUFFER #1 Reached
* D05 - Active FAKE TEV Clock Event Table FULL
* D04 - Both Remote TCLK Signals are Missing
D03 - Bad Arcnet Node
D02 - Arcnet Transmit Timeout
D01 - Arcnet Excessive NAK received
D00 - Arcnet NO Token
* - Denotes Non-Maskable LAM bits.
5.5 F6 A14 : READ LAM REQUEST REGISTER
See section 5.4 for bit definitions.
Latched bits must be cleared by the host.
5.6 F6 A6 : READ ARCNET ADDRESS
D07:D00 - ARCNET node address
5.7 F8 A0 : Check LAM
Returns Q if LAM is set.
5.8 F9 A0 : HARDWARE RESET
5.9 F10 A0 : CLEAR LAM
Clears the LAM request register.
5.10 F19 A13: WRITE LAM MASK REGISTER
See section 5.4 for bit definitions.
5.11 F19 A14: WRITE LAM REQUEST REGISTER
See section 5.4 for bit definitions.
5.12 F19 A6 : SET ARCNET ADDRESS
D07:D00 - New node number
5.13 F24 A15 : DISABLE LAM
5.14 F26 A15 : ENABLE LAM
6.0 FAKE TEV EVENT BUFFER
The C1200 Module has the ability to generate Fake TEV events from a table of times (32 bit) and Event values (8 bits). (Ref. to Fig.#1 on page 33).
The Maximum number of REMOTE Fake (Super-imposed) TEV events allowed will be 15. The Maximum Number of LOCAL Fake TEV events allowed will be 512.
There are two seperate buffers for each mode (i.e. Local / Remote) one of the buffers will be active during each mode while other buffer will be IDLE. When new Fake TEV request are loaded into the module they will be automatically stored into the idle buffer. When all request are sent and sorted in assending order by times, a write ( any data) to address 0xB000012a (or F26-A05) will toggle the buffers at the next reset event. If an immediate toggle is to be requested, a write (any data) to address 0x0b0000122 (or F26-A03) must also be performed. This will cause the newly stored events to become active immediately.
The firmware will determine which buffer is IDLE by reading the status register at address 0xb0000106 (refer to page 19) bit #8 is the SARAM buffer select bit. This will show which buffer is currently active. All Newly stored events must be written into the IDLE buffer, refer to page 32 for all buffer table addresses.
8.0 ARCNET NTIs
All communication via the ARCNET interface is done using EADNET protocol. This protocol defines a packet header consisting of 12 bytes.
0,1 System Code (Defined by ARCNET dudes) 0x8201
2 Destination House
3 Destination Node
4 Destination NTI
5 Pad count
6 Source House
7 Source Node
8 Source NTI
9 Source message sequence #
A Max. packets: This packet (8 bits each)
B Data type code (See EADNET description)
After the EADNET header, up to 497 bytes of data may follow. The data size is NTI specific.
The C1200 module responds to the following NTIs:
0x00 - Display configuration
0x01 - Echo attached message
0x04 - Broadcast Cycle Counter
0x08 - Console interface
0x0A - Reset module
8.1 0x00 : DISPLAY CONFIGURATION
Returns an array of strings with keywords as follows:
8.2 0x01 : ECHO ATTACHED MESSAGE
Returns a copy of the data following the EADNET header.
8.3 0x04 : BROADCAST CYCLE COUNTER
When enabled this Module will Broadcast its cycle counter, (a 32 bit value.)
8.4 0x08: CONSOLE INTERFACE
Console Interface used for downloading new code or operating modules debugger routines.
8.3 0x0A : RESET MODULE
Causes hardware reset.
9.0 FRONT PANEL
N indicates that the crate controller has initiated a dataway cycle addressed to this module. This LED is stretched to 10 ms to aid viewing.
LAM indicates that the module is asserting the dataway LAM signal for this slot. The host must read the LAM request register F6A14 in order to identify the nature of the request.
LAMEN indicates that any unmasked bits in the LAM request register may cause the module LAM to be asserted. When off, module LAM will never be asserted. LAM source bits which are set by module firmware will be latched and may cause LAM to be asserted when the LAM is enabled at some later time. F24A15 and F26A15 are provided to set the state of the LAM enable gate. After power-up or reset, LAM is disabled.
HEARTBT indicates, when blinking, that the module is running and accepting interrupts. This line is also tied to the DS1232 micromonitor chip which will reset the module if this signal does not occur for 600mS. This LED is stretched to 10mS to aid viewing.
TCLK indicates that the module is receiving Remote T-CLK event.
PERROR Indicates that a Parity Error has occured while receiving Remote TEV Clock Event.
FAIL indicates that a failure has occurred in the 80960 processor. This LED will light after restart when the 80960 is performing its self test, and then go out if the module is running properly.
INPUT1/INPUT2 Indicates which inputs the REMOTE TEV Event signal is active on. If both are LEDs are on then INPUT 1 is the active input and Input 2 is the backup input.
15HZ Indicates if the local 15Hz tev event is functioning.
720HZ Indicates if the local 720Hz tev event is functioning.
9.2 RESET PUSH-BUTTON
The RESET push-button, when pressed, resets the processor, peripheral chips and other circuits. The CAMAC function F9A0 activates the same sequence.
APPENDIX A - ACRONYMS USED
ARCNET - Attached Resource Computer NETwork
CAMAC - Computer Automated Measurement And Control
CAMINT - CAMac INTerrupt
DUART - Dual Universal Asynchronous Receiver/Transmitter
EPROM - Erasable Programmable ROM
LAM - Look At Me
LAMEN - LAM ENable
MADC - Multiplexed Analog to Digital Converter
NVRAM - Non-Volatile RAM
PAL - Programmable Array Logic
FPGA - Field Programmable Gate Array
RAM - Random Access Memory
RD - Research Division
ROM - Read Only Memory
TCLK - Tevatron CLocK
TEV - Tevatron
DPRAM - Dual Ported RAM
SARAM - Sequential/Random Access Dual Ported RAM
APPENDIX B - TRADEMARKS
ARCNET is a trademark of Datapoint Corp.
SMC is a trademark of Standard Microsystems Corp.
SIGNETICS is a trademark of North American Phillips Corp.
MICROTEC is a trademark of Microtec Research Inc.