RD Controls Hardware Release 41.0
C1300 8-by-4 Serial Link Multiplexer
Paul A. Kasley
30 Sept 1993
All connectors and card dimensions are compatible with the 4-by-4 linkmux. The C1300 occupies a double wide CAMAC slot. Signal pinouts, signal functions, and signal levels are fully compatible with the 4-by-4 device. Additional signals needed to support the additional front ends are on connector pins that are unused by both the 4-by-4 version and the card slot into which it plugs. Backward compatibility with the 4-by-4 version is maintained and it can be used should the 8-by-4 device fail.
The C1300 has 59 LED diagnostic indicators grouped for ease of use. LEDs show channel requests, grants, and addresses as well as transmit and receive data and internal status and setup bits.
All front-end channel inputs and outputs are
TTL. The inputs are terminated with 330 ohms to 5 volts and 470 ohms to
ground. The phase reverse serial link inputs and outputs are transformer
coupled. The receive data inputs are terminated in 75 ohms.
The counters monitor one of four conditions: link grant (Summation of CNL_GRANTn*LINK_ADRS), channel grant (CNL_GRANT), channel request (CNL_REQ), and test count (VCC). Two software control bits select the variable that all eight counters monitor for their respective channels. When "link grant" is selected the counters for channels A through D monitor the link activity while the counters for channels E through H perform "test count". The counter gate period is software settable to either one second or one minute. When the one second gate is selected the counters accumlate link activity in one microsecond increments. With the one minute gate selected the granularity of the counters is 4 microseconds.
Each counter is double buffered. At the end of
every count period the content of each counter is transferred to its respective
holding register. At the same time the counter is reset and a new accumulation
begins. A status bit is provided via the CAMAC "Q" signal to indicate to
software if the current content of the holding register for a particular
counter was previously read. All counter status bits are set at the end
of a gate period. A read of a holding register will reset the status bit
after the read operation has completed.
The mechanical layout of the module is organized
to accomodate the large number of discrete LED signal indicators. Size
T-1 LEDs are stacked on the component side of the LED board. Legends and
key-lines to the indicators are placed on the right half of the faceplate.
The boards are mechanically secured to each other by 4-40 threaded standoffs.
Branch addresses for channels A through D are terminated and buffered by U1 on the multiplexer board. Addresses for channels E through H are buffered by U1 on the LED board. All branch addresses are applied to arbitration EPLD U24, transmit multiplexer EPLD U25, and receive multiplexer EPLD U20. The request lines are received and sampled by latch U4 before being applied to U24. Note that the input latches for the branch addresses are coded into U24.
Arbitration occurs within U24 at a 10 Mhz rate. On the IRCLK phase of the 100 nsec arbitration cycle all inputs (BRA0-BRH1, /REQA-/REQH) are sampled. The sampled signals propagate through U24. On the GNTCLK phase, 50 nsec later, the grant signals are latched. To perform the arbitration, channels have a fixed priority with channel A having the highest and channel H the lowest. A channel is granted access to the addressed link if the requested link is not being requested by a higher priority channel and if the requested link in not already in use by another channel. These determinations are made using the branch addresses and request and grant lines. The logic within U24 accomplishes this by first comparing all sets of addresses for equivalence (A=B, A=C, A=D, A=E, A=F, A=G, A=H, B=C, B=E, etc.). The outputs of 28 2-bit address comparators then go to decoding logic which drives the D input of a particular channel grant flop low if the address equals that of a higher priority request or if the address equals that of a lower priority grant. Note that because of the prioritization of the channels, there is no need to explicitly track which links are currently assigned to which channel. Once asserted, the channel grant remains active until the corresponding request line is negated.
The grants are routed to U25 and U20 which then set up the transmit and receive data connections between the channels and the links. Transmit multiplexer U25 consists of an array of one-of-four decoders driving two sets of four each of "eight-wide and-or" gates. Serial data and clock from each channel goes to one input of each and-or. The branch address for each channel is decoded into an enable for the corresponding data input to the and-or gates. The decoder is enabled only if the corresponding grant is active.
The receive multiplexer U20 is comprised of an array of two sets of eight each of four-to-one selector blocks. Incoming normal and inverted data from the four CAMAC links are applied to one input of all eight selectors. The output of each selector drives the receive line of a DAE front-end. Branch address is decoded to determine which selector input to gate to the output. Again, the corresponding grant line enables and disables the selector.
U25 and U20 have some additional functions not
directly related to their primary purpose. Extra pins and logic in U25
are used to decode the CAMAC dataway function codes for the utilization
monitor. U20 takes a 20 Mhz clock from oscillator U14 and generates IRCLK
and GNTCLK. The output clocks are 180 degrees out of phase and de-skewed.
U20 also has gating that decodes branch addresses and channel grants to
produce an activity signal for each of the four links.
The control register within U21 selects the integration time of the counters and chooses one of four variables for the counters to integrate. The MIN/SEC bit when high selects a one minute integration period and when low selects a one second period. The FCNSEL0 and FCNSEL1 bits set the counters to accumlate link grant, channel grant, channel request, or test count (VCC).
One counter section (1/2 U22) with one frontend section and a flag register (1/8 U21) constitute a complete activity counter. A one-of-four selector connects one side of an "and" gate to "link active", "channel grant", "channel request", or logic "1". The other side of the gate receives a 1 Mhz clock. For the one second integration selection, the output of the "and" gate drives the 24-bit counter directly. Thus the counter accumulates activity in one microsecond increments. For the 1 minute selection, the prescaler is inserted between the "and" gate and the counter so that activity is logged in 4 microsecond increments. At the end of a count cycle the content of the counter is broadside loaded into a holding register, the counter is reset, and the status flag is set. The status flag is reset when the counter holding register is read by the dataway. Thus the CAMAC controller can know if the particular counter value is "stale". The flag is returned via the /Q line.
The end-of-cycle pulse is derived from the overflow of a divider chain in U21. Rather than attempt to count synchronously through 30-odd stages, the divider is a ripple counter. The overflow is re-synchronized to the 10 Mhz input clock. A separate state machine at the end of the chain ensures that count reset and register transfer occur outside of any CAMAC read operations.
U22, 23, 26, and 27 drive a common bus, Q0-Q23,
to a set of drivers, U13, 11, and 9. These drivers gate the Q bus onto
the CAMAC /R lines when a read cycle is executed. U12, U10, U8, and U19
drive the Q bus when a read of the serial number, status, or module ID
registers is executed.
U6 through U9 are GAL6001 LED flashers. Except for the pinout, the flasher PAL source file is identical to that from the 4-by-4 design. The flashers use the 100 Hz clock from the multiplexer board. A 74LS390 dual decade counter, U10, divides the 100 Hz signal to 1 Hz for a heartbeat indicator.
Rather than add a seventh GAL6001 for a single indicator, one-shot U13 is used as a pulse stretcher on the COUNTER RESET signal.
U11 decodes the two function selects to a one-of-four indication of the utilization monitor mode.
|1||+TXDTA||CHAN A DATA||1||GND||GROUND|
|2||+BRA0||CHAN A ADR 0||2||-TXCLA||CHAN A CLK|
|3||-RXAA||CHAN A RCV DATA||3||BRA1||CHAN A ADR 1|
|4||-REQA||CHAN A REQUEST||4||+RXBA||CHAN A RCV DATA|
|5||GND||GROUND||5||-GNTA||CHAN A GRANT|
|6||-TXCLB||CHAN B CLK||6||+TXDTB||CHAN B DATA|
|7||+BRB1||CHAN B ADR 1||7||+BRB0||CHAN B ADR 1|
|8||+RXBB||CHAN B RCV DATA||8||-RXAB||CHAN B RCV DATA|
|9||-GNTB||CHAN B GRANT||9||-REQB||CHAN B REQUEST|
|10||+TXDTC||CHAN C DATA||10||GND||GROUND|
|11||+BRC0||CHAN C ADRS 0||11||-TXCLC||CHAN C CLK|
|12||-RXAC||CHAN C RCV DATA||12||+BRC1||CHAN C ADR 1|
|13||-REQC||CHAN C REQUEST||13||+RXBC||CHAN C RCV DATA|
|14||GND||GROUND||14||-GRANTC||CHAN C GRANT|
|15||-TXCLD||CHAN D CLK||15||+TXDTD||CHAN D DATA|
|16||+BRD1||CHAN D ADR 1||16||+BRD0||CHAN D ADR 0|
|17||+RXBD||CHAN D RCV DATA||17||-RXAD||CHAN D RCV DATA|
|18||-GNTD||CHAN D GRANT||18||-REQD||CHAN D REQUEST|
|1||+TXDTE||CHAN E DATA||1||GND||GROUND|
|2||+BRE0||CHAN E ADR 0||2||-TXCLE||CHAN E CLK|
|3||-RXAE||CHAN E RCV DATA||3||BRE1||CHAN E ADR 1|
|4||-REQE||CHAN E REQUEST||4||+RXBE||CHAN E RCV DATA|
|5||GND||GROUND||5||-GNTE||CHAN E GRANT|
|6||-TXCLF||CHAN F CLK||6||+TXDTF||CHAN F DATA|
|7||+BRF1||CHAN F ADR 1||7||+BRF0||CHAN F ADR 1|
|8||+RXBF||CHAN F RCV DATA||8||-RXAF||CHAN F RCV DATA|
|9||-GNTF||CHAN F GRANT||9||-REQF||CHAN F REQUEST|
|10||+TXDTG||CHAN G DATA||10||GND||GROUND|
|11||+BRG0||CHAN G ADRS 0||11||-TXCLG||CHAN G CLK|
|12||-RXAG||CHAN G RCV DATA||12||+BRG1||CHAN G ADR 1|
|13||-REQG||CHAN G REQUEST||13||+RXBG||CHAN G RCV DATA|
|14||GND||GROUND||14||-GRANTG||CHAN G GRANT|
|15||-TXCLH||CHAN H CLK||15||+TXDTH||CHAN H DATA|
|16||+BRH1||CHAN H ADR 1||16||+BRH0||CHAN H ADR 0|
|17||+RXBH||CHAN H RCV DATA||17||-RXAH||CHAN H RCV DATA|
|18||-GNTH||CHAN H GRANT||18||-REQH||CHAN H REQUEST|
There is no board level calibration. The only
setup consists of programming the board serial number into the four jumpers
JU1 through JU4. JU1 is the LSB and JU4 is the MSB. A shorted jumper is
a logic 0.