Controls Hardware Release No. 70.2
(Firmware Version # 1.50)
CAMAC 145 Module
Vacuum Readback Interface
K. C. Seino and B. S. Hendricks
January 15, 1990
TABLE OF CONTENTS
INTRODUCTION
The CAMAC 145 module does what the CC45 used to do, i.e.,
- It converts incoming serial data words to parallel data words,and
- It stores them in memory until the front end computer reads them.
In addition to the above mentioned functions, the C145 performs
- Conversion of the special BCD data format of the vacuum scanner
to the IEEE standard floating point format,
- Averaging of the readback values from a number of ion gauges in
each service building, and
- Local alarm scanning.
The C145 was designed with the Motorola MC68000 microprocessor and
MC68881 floating point coprocessor. The serial to parallel conversion
and its support circuits were implemented in the Altera EPM5128
(erasable PLD). The CAMAC interface circuits were designed with the
same philosophy as the one for the C193, i.e.,
- Read module status without interrupting the CPU
- direct F to vector conversion is done in a single PROM and
- Clear-cut synchronization between CAMAC and the CPU is done in
two sets of tandem flip flops.
The C145 returns data in the IEEE standard floating point format to
the front end computer, and it allows Main Ring vacuum devices to be
placed on Parameter Pages and Datalogger Lists.
- CPU: Motorola MC68000 microprocessor clocked at 8 MHz
- Memory: 64K bytes of RAM, 64K bytes of EPROM, 2K bytes of NVR
(Nonvolatile RAM)
- Interrupt controller: AMD Am9519A
- Timer: AMD Am9513A (five timing channels)
- TCLK event source: Programmable with PLS153
- RS232 port: Signetics 2681 communication interface
- CAMAC interface: Command decoder (providing up to 192 interrupt
vectors), 16 bit read and write registers, command managing circuits
and LAM circuit
- Vacuum readback interface: Incoming line is coupled with transformer
and terminated into 51 ohms.
- Serial to parallel conversion: Conversion circuit is implemented in
Altera EPM5128 (erasable PLD), which includes parity check, time-out
detection, clear synchronization as well as serial to parallel
conversion.
- Floating point conversion: Done with Motorola MC68881, full
confirmation to IEEE P754 standard, capable of handling seven data
types (byte, word and long word integers; single, double and extended
precision real numbers; and packed BCD real numbers)
- Vacuum data: Module acquires up to 63 channels of vacuum data,
converts it from BCD format to IEEE floating point format and stores
it in memory. Data is delivered to module at rate of one channel per
second.
- Averaging: Module averages up to 63 channels of vacuum data
approximately once a minute, excluding bad readings.
- Alarm scanning: Module alarms when average vacuum value is out of
limits or when 15 or more pumps are returning bad readings. Bypass
bits are provided.
The C145 firmware consists of three software modules, i.e., ENVIRON
C145 and FLTRP. These software modules are linked together along with
the 68 floating point library.
The ENVIRON module creates an environment for a C program running on
the MC68000 microprocessor. The module does the following
- Switch off the PROM from the lowest memory locations
- Disable interrupts
- Initialize the stack pointer
- Initialize the frame pointer and
- Call 'main' in the C program.
The C145 program consists of global variable declarations, the main
program (initialization and background processing), error exception
handlers, a heart beat interrupt routine, CAMAC interrupt routines,
an FPC reset routine, a vacuum interrupt routine, a vacuum time-out
interrupt routine and a routine to calculate average vacuum value.
The MC68000 does not execute the MC68881 Floating Point Coprocessor
(FPC op codes. However, if it detects or traps them, it forces itself
into an exception state. While it is in the exception state, the CPU
transfers control to the FLTRP (F-Line Trap) routine which decodes
the FPC op code and emulates it with a series of 68000 instructions
that control the 68881. The FLTRP module consists of a general
instruction handler, an external operand to register instruction
handler and a register to external destination instruction handler.
CAMAC commands, the vacuum interface and its time-out, the serial I/O
the Clock Event 1, and the heart beat gain attention from the CPU as a
vectored interrupt request. The priority of vectored interrupts is
determined with PLD6 and the Am9519A (UIC). The C145 has the
following priority scheme for vectored interrupts.
| PRIORITY | EVENT | NOTE
|
|---|
| 0 (highest) | CAMAC command |
|
|---|
| 1 | Vacuum interface interrupt | UIC, level 0
|
|---|
| 2 | Vacuum time-out interrupt | UIC, level 1
|
|---|
| 3 | Serial I/O interrupt | UIC, level 2
|
|---|
| 4 | Clock event 1 | UIC, level 3
|
|---|
| 5 | | UIC, level 4
|
|---|
| 6 | | UIC, level 5
|
|---|
| 7 | | UIC, level 6
|
|---|
| 8 (lowest) | Heart beat | UIC, level 7
|
|---|
The combined interrupt request (CAMAC command and UIC request) is fed
to the CPU as the Level-6 interrupt request. When more than one
interrupt request is pending, the one with the highest priority is
honored. Once an interrupt is acknowledged, other interrupts are
disabled until the acknowledged interrupt is completely serviced due
to the fact that the MC68000 inhibits interrupts for all priority
levels less than or equal to the current priority. This prevents
multiple interrupt acknowledgment. One has to remember that other
exceptions (reset, errors, traps and nonmaskable interrupt) are still
honored by the CPU while a vectored interrupt is being serviced. In
exiting from the service routine, the previous status register is
restored (Level-0 is restored), and interrupts are thus enabled.
When a CAMAC command arrives at the C145, it generates an interrupt
request if there is no other command pending. When the CPU
acknowledges the request, it clears the request in the interrupt
service routine. The software has control over when to clear and does
not allow the next command to come in before it reads the data. The
reader is suggested to read (5.3.1) in HARDWARE DESCRIPTION.
The identification of the last serviced CAMAC read command is stored
in a variable. The identification of the current service routine is
compared with the previous one, and a proper action is taken based
upon the comparison result.
When the vacuum interface has data, it interrupts the CPU. The CPU
then reads and stores the vacuum channel and data. The vacuum data is
first converted to an PDR (Packed Decimal Real) before it is further
processed in the FPC (Floating Point Coprocessor). The data is
converted from PDR to SPBR (Single Precision Binary Real) by the FPC,
and it is stored into the vacuum data buffer. The interrupt routine
performs the following.
- Read the channel number and the raw vacuum data.
- If the interrupt is the first after the interface has been reset,
discard the data and return.
- If there is a parity error, discard the data and return.
- Check the channel number to see
- if the channel data has already been processed for averaging, and
if true, discard the data and return,
- if the same channel has been read less than 3 times in a row, and
if true, discard the data and return,
- if the same channel has been read 3 times in a row, and if true,
go to (5).
- If the pump for the channel is out of service, decrement the bad
pump count (if it has been marked as a bad pump) and return.
- Extract the error status, the exponent, the M part of the
mantissa and the N part of the mantissa.
- Check to see if it is a bad reading or not.
- If not, build up an PDR for the data, use the FPC to convert the
PDR to an SPBR, decrement the bad pump count (if it had been
previously marked as a bad pump), do the averaging routine and return.
- If yes, increment the bad pump count, check it for alarm and return.
The vacuum data word arrives at the C145 module at a rate of
approximately 1 KHz. The data is repeated for one channel for a
duration of about 1 sec and then it moves on to the next channel.
Therefore, if there are 63 channels for a building, it takes about 63
seconds to complete updating for the building. In order to
efficiently deal with a fast word rate and slow channel updating, the
vacuum interface interrupt routine was written so that it takes one
reading per channel for averaging and discards the other readings.
The latest channel number is first checked against channel numbers in
the averaging pool to see if it is repeated. If it is repeated, this
means that all the channels have been read since last averaging and
that it is a time to do another averaging.
If it is not already in the averaging pool, the current channel
number and vacuum value are saved, the averaging sum is updated. The
pool index is incremented, and control is returned to the vacuum
interrupt routine.
If it is in the pool, the averaging LED is turned on, and the average
vacuum value is calculated. The average value is then checked against
the alarm limits. If it exceeds the limits, the alarm retry count is
incremented. If the retry count reaches the retry limit, an alarm is
generated. If it does not exceed the limits, the alarm retry count is
reset to zero. In either case, the averaging sum is cleared, and the
averaging LED is then turned off. The current channel number and
vacuum value are saved, and the averaging sum is updated. The pool
index is then incremented, and control is returned to the vacuum
interrupt routine.
Read vacuum data as specified with F16A0. A starting channel and a
number of channels are specified with F16A0. The data is in the IEEE
floating point format requiring two word reads per channel.
Read module status (implemented in hardware, Q is always returned).
The status word is organized as follows.
| Bit-0 | Heart beat OK
|
| Bit-1 | Vacuum data reception in progress,
|
| Bit-2 | Vacuum interface time-out error.
|
Read LAM source register. The word is organized as follows.
| Bit-0 | Average vacuum reading is out of tolerance,
|
| Bit-1 | Fifteen or more pumps are returning bad readings.
|
Read LAM mask register. The word format is identical to the LAM source
register. A bit which is set in the mask register will permit
generation of a module LAM due to that LAM source. Other bits will
not generate LAM unless they are set. At module reset, the LAM mask
register is initialized to FFFF (hex).
Read average vacuum data. The data is in the IEEE floating point
format requiring two word reads.
Read vacuum alarm limit. The data is in the IEEE floating point format
requiring two word reads.
Read the number of pumps currently returning bad readings.
Read the number of vacuum interface time-outs that have occurred.
Read the number of FPC errors that have occurred.
Read the system timer for diagnostic purposes. The data is two words
in length. The timer is clocked at 15 Hz.
Read the alarm retry limit (number of times out of tolerance before
generating an alarm).
Read the current alarm retry count.
Read the number of pumps in the most recent average.
Read the vacuum interface reset count.
Read the parity error count.
Read the status of pumps (or channels) specified with F17A0. A
starting channel and a number of channels are specified with F17A0.
The data format is organized as follows.
+---+---+---+---+---+---+---+---+
| 7 | 6 | 5 | x | x | x | 1 | 0 |
+---+---+---+---+---+---+---+---+
Bit-0: pump equipped if set
Bit-1: pump in service if set
Bit-5: bad reading (invalid digit)
Bit-6: parity error
Bit-7: time-out error
Read diagnostic counter registers specified with F17A1. A starting
counter and a number of counters are specified with F17A1.
Read the averaging pool index data (a record of which pumps have been
used for averaging). A starting data point is specified with F17A3.
Read the high word of the average vacuum reading and save the low
word for a subsequent read with an F2A1 command ( the data is in the
IEEE floating point format requiring two words).
Read the low word of the average vacuum reading. (See F2A0 for the
high word.)
Read the high word of the system timer (the data is two words in
length).
Read the low word of the system timer. (See F2A2 for the high word.)
Read the high word of the vacuum alarm limit (the data is in the IEEE
floating point format requiring two words).
Read the low word of the vacuum alarm limit. (See F2A4 for the high
word.)
Read the high word of the average vacuum reading and save the low
word for a subsequent read with an F2A7 command. (F2A6 is an
auxiliary command for F2A0, the data is in the IEEE floating point
format requiring two words).
Read the low word of the average vacuum reading (F2A7 is an auxiliary
command for F2A1). (See F2A6 for the high word.)
Read the high word of the vacuum averaging sum (the data is in the
IEEE floating point format requiring two words).
Read the low word of the vacuum averaging sum. (See F2A8 for the high
word.)
Read module ID number. The number 145 (91 in hex) is returned.
Read module firmware version number. A 16 bit value is returned. The
most significant byte is the major version number, and the least
significant byte is the minor version number.
Make a diagnostic memory read from the address specified with F17A2.
This command keeps reading one memory location.
Make diagnostic block memory reads from the address specified with
F17A2. This command allows you to read consecutive memory locations.
Read hardware debugging value. This value increments each time an
F6A7 is done, and it is reset to zero when an F16A15 is done. The
amount of time that this command uses is determined by the delay
value written with F16A15.
Test module LAM. The Q response indicates whether the module is
requesting LAM (Q = true) or not (Q = false). This command is
implemented entirely in the hardware and does not interrupt the
module CPU. Consequently, No-Q retries are not required. A single
access always returns the proper status.
Reset module. This command always returns Q. This command is
implemented entirely in the hardware and is equivalent to pressing
the reset button on the module front panel. It causes the module CPU
to be reset, and the ensuing module initialization may take as much
as 100 msec. Attempts at communication before reset is complete will
result in No-Q.
Write a starting channel and a number of channels to read vacuum data
with F0A0. The data format is as follows.
| Bits 15:8 | Starting channel (0 to 63)
|
| Bits 7:0 | Number of channels (1 to 64)
|
Write LAM mask register. See F0A2 for the register bit organization.
Write vacuum alarm limit. The data is in the IEEE floating point
format requiring two word writes.
Write alarm retry limit (number of times out of tolerance before
generating an alarm).
Write a delay value and reset the hardware test counter for F6A7 (read
test). The value written by this command determines how long
subsequent F6A? commands will be delayed. F16A15 also resets the
hardware test counter to zero.
Write a starting channel and a number of channels to read status word
with F1A0. The data format is as follows.
| Bits 15:8 | Starting channel (0 to 63)
|
| Bits 7:0 | Number of channels (1 to 64)
|
Write a starting counter and a number of counters to read with F1A1.
The data format is as follows.
| Bits 15:8 | Starting counter (0 to 10)
|
| Bits 7:0 | Number of counters (1 to 11)
|
Write a starting address for F6A2 (memory read) and F6A3 (block memory
read).
Write a starting data point to read the averaging pool index data (A
record of which pumps have been used for averaging) with F1A3.
Write vacuum channel status bits. The channel to be modified is specified
with F19A1. The data format is as follows.
| Bit-0 | equipped if set
|
| Bit-1 | in service if set
|
Write a vacuum channel (0 to 63) to modify the status bits.
Clear diagnostic counters (located in CNTBUF). The data format is as
follows.
| Bits 15:8 | Starting counter (0 to 10)
|
| Bits 7:0 | Number of counters (1 to 11)
|
Disable module LAM.
Reset vacuum interface.
Reset the FPC (MC68881).
Enable module LAM.
Reset all word pointers for reading.
Reset all word pointers for writing.
The CAMAC 145 is a single wide module, which consists of a board and
front panel. Main functions of the module are a microcomputer, a
floating point processor, an CAMAC interface and a vacuum readback
interface.
- CPU: Motorola MC68000 microprocessor clocked at 8 MHz
- Memory: 64K bytes of RAM, 64K bytes of EPROM, 2K bytes of NVR
- Interrupt controller: AMD Am9519A
- Timer: AMD Am9513A (five timing channels)
- TCLK event source: Programmable with PLS153
- RS232 port: Signetics 2681 communication interface and Linear
Tech. LT1081 driver/ receiver
- CAMAC interface: Command decoder (providing up to 192 interrupt
vectors), 16 bit read and write registers, command managing circuits
and LAM circuit
- Vacuum readback interface: Incoming line is coupled with
transformer and terminated into 51 ohms, and Signetics NE521
dual-comparator reshapes incoming signal converting it from bipolar
signal to unipolar TTL signal.
- Serial to parallel conversion: Conversion circuit is implemented
in Altera EPM5128 (high density, erasable PLD), which includes parity
check, time-out detection, clear synchronization as well as serial to
parallel conversion.
- Floating point conversion: Motorola MC68881, full confirmation to
the IEEE P754 standard, capable of handling seven data types (byte,
word and long word integers; single, double and extended precision
real numbers; and packed BCD real numbers)
- DTACK generation and CAMAC command managing circuits are
implemented in Altera EPM5032.
- Others: 8 bit data display on front panel
Memory Map of CAMAC 145 Module with MC68000
| SP | SD |
| | |
FE8000 +--------+--------+
| |--------| IOPG (4Kb)
| |
FF0000 +--------+--------+
| |
| |
| PROM (64Kb) |
| |
0 +--------+--------+
|Note(*) | |
4000 +--------+ +
| |
| RAM (64Kb) |
| |
+--------+--------+
10000 | |--------| NVR (4Kb) Only odd locations are used for
this (Data Bits 0:7).
Notes: (*) A block of address locations (from 0 to $3FFF in the SP
space is switched from PROM to RAM. At the system reset, a part of
PROM is mapped into the address block, where the CPU reads the
initial stack pointer and program counter and starts executing the
firmware which resides in the PROM. The CPU turns off the PROM from
the address block with the first instruction in the firmware. Because
the PROM is no longer needed to be mapped there once the firmware
execution is started.
The CAMAC command management circuits for the 145 are the same as the
one for the 193 except the fact that they are implemented in the
Altera EPM5032.
All the CAMAC commands except F0A1, F8A0 and F9A0 are processed
through the circuit shown in Fig. 1a. The circuit has two D-type
flip-flops, which are connected together in tandem. The CAMAC dataway
cycle is totally asynchronous with the CPU memory cycle. The two
flip-flops synchronize the CAMAC cycle with the CPU cycle in an
orderly manner.
When there is no command pending, GCMD (General Command) in the figure
arrives at Pin-CK of the flip-flop on the left, and the low to high
transition of the signal triggers the flip-flop. If QD1 is low, CMPND
(Command Pending stays false, and the Q is generated as shown in Fig.
1b. At the lagging edge of S2, the flip-flop on the right is set by
QP1, and the interrupt request INT1 is sent to the CPU. When the
CPU acknowledges the request, it clears the request with CMWDEN
(CAMAC Write Data Enable) during the interrupt service routine. If
QD1 is high, CMPND becomes true, and the Q is not generated as shown
in Fig. 1c.
When a read command arrives, it is processed through the circuit
discussed in (5.3.1), and if another command is not pending, the
interrupt request INT1 is generated. The CPU fetches and latches a
word of data for the next read command during the service routine. If
a word of data has been latched with the previous read command, the
current command reads it. The read command control circuit is shown
in Fig. 2a. When RCMD (Read Command) arrives, if QD? is true (data
ready), and if CMTCH (Command Match) is high, what result from these
are (1) RDVAL (Read Data Valid) = true, (2) RDEN (Read Data Enable)
true and (3) Q = true as shown in Fig. 2b. When RCMD arrives, if QD2
is not true, the results are (1) RDVAL = false, (2) RDEN = false
and (3) Q = false as shown in Fig. 2c. When RCMD arrives, even if QD2
is true, if CMTCH is false, QD2 is cleared 100 nSec after the leading
edge of GCMD (that is before S? arrives), and the results are (1)
RDVAL = false, (2) RDEN = false and (3) Q ? false. Synchronization
between RCMD and CMRDLT (CAMAC Read Data Latch) is done by two
flip-flops shown in Fig. 2a.
One simple device called 82S147A (512 x 8 bipolar PROM) does convert
CAMAC functions/ subaddresses to interrupt vectors. The device can be
programmed for any applications that one would imagine, and if one
wants to change the repertoire of F/As, all that he has to do is to
program another PROM. The only restriction is the fact that 9 bit
information produces 8 bit information or that the MC68000 can handle
up to 192 user interrupt vectors.
The MC68881 was designed for use as a coprocessor with the MC68020
microprocessor. However, when it is used with the MC68000, it is
treated as a peripheral device rather than as a coprocessor. The
MC68000 sees a number of registers in the MC68881, through which the
CPU transfers instructions and data to the FPC and receives flags and
data from it.
The FPC software was written using what is called the F-line trap
technique. The MC68000 does not execute the FPC op-codes, however it
does detect or trap them, forcing itself into an exception state.
While it is in the exception state, the CPU transfers control to a
routine that decodes the FPC op-codes and emulates it with a series
of 68000 instructions that control the 68881.
The serial to parallel conversion circuits consist of Input Control,
Data Shifter, Data Strobe Generator, Output Enable, Parity Check,
Time-out Detector, Timing Generator and Clear Synchronize.
The incoming serial word is made of 20 bits (one header bit, 18 data
bits and one parity bit). A flip-flop is set when the header bit
arrives because it always contains an '1'. The flip-flop is toggled
whenever an '1' arrives, and it produces an even parity over 19 bits
(one header bit and 18 data bits). If there is a mismatch between the
produced bit and the incoming parity bit the parity error is
generated.
A flip-flop is set with the first bit of the incoming serial word and
is reset with the 20th bit. If resetting does not occur within one
msec, the time-out error is generated. Under normal conditions, it
takes 20 uSec to complete the serial reception.
When the CPU reads the data, it attempts to clear the serial to
parallel conversion circuits. However, because the CPU read is
asynchronous with the serial reception, if clear occurs in the middle
of reception, the following operation becomes totally out of order.
In order to avoid all of this, the clear request is temporarily
stored on a flip-flop and is inhibited until the serial reception
completes. The CINHB (Clear Inhibit) signal is generated by an
one-shot which is triggered by bit cell pulses.
- N: When on, it indicates that the module is addressed by the crate
controller.
- LAM: When on, it indicates that the module is asserting the LAM.
- LMEN: When on, it indicates that the LAM is enabled.
- HB: When on, it indicates that the CPU is alive and functioning
normally under program control.
- HALT: When on, it indicates that the CPU is being reset or that the
CPU has stopped executing instructions (such as in a double bus fault
condition).
- TCLK: When on, it indicates that the 10 MHz carrier of the Tevatron
clock is detected at the module.
- VRIP: When on, it indicates that vacuum data reception is in progress.
- DSB<0:7>: These are used for various diagnostic purposes, e.g.,
indication of module initialization.
- VIV: This is a test point for vacuum readback input.
- GND: This is a test point for the ground.
- RS232: It provides a standard asynchronous terminal port.
- RESET: When depressed, it resets the module hardware and
re-starts the module firmware.
- +5 and -5: These indicate the status on +5 and -5 power supplies.
The I/O connections are made via the 36 contact Viking type connector.
| Contact | Signal | Contact | Signal
|
|---|
| 1L | Gnd | 1R | Gnd
|
| 2L | nc | 2R | TCKIN
|
| 7L | VCMN | 7R | VCMP
|
| 13L | RXDA | 13R | nc
|
| 14L | Gnd | 14R | TXDA
|
| 15L | RXDB | 15R | nc
|
| 16L | Gnd | 16R | TXDB
|
Notes: L = left, R = right, nc = no connections
There are a total of eight PLDs (Programmable Logic Devices) used on
the C145 module. The documentation on these devices exist on VAX or
an IBM PC AT, and their file names are listed as follows.
- PLD1: FTV145A.LS on SYS$AUX1:[EXORMACS.C145], C145 FA TO VECTOR
CONVERSION #A
- PLD2: PLD2.ABL on A:\C145, this device decodes CAMAC FAN and
produces general command, read command, F0A1, (F8A0) and F9A0, and it
also
generates Q and X responses.
- PLD3: PLD3.ABL on A:\C145, this device produces memory select
lines (PROM, RAM, I/O Page, IACK and NVR).
- PLD4: PLD4.ABL on A:\C145, this device produces select lines for
CAMAC registers, latches, SIO, timer, UIC and FPC.
- PLD5: PLD5.ABL on A:\C145, this device produces select lines for
vacuum read channel/ data, heart beat, display data bits and map
register.
- PLD6: PLD6.ABL on A:\C145, this device produces LAM, LAM enable,
R/ W data strobes, IAK1 and IAK2.
- PLD11 (EPM5032): CRCDT.* on A:\C145, this includes DTACK
generator, CAMAC command control and CAMAC read control.
- PLD12 (EPM5128): SPCNV2.* on A:\C145, this includes serial to
parallel conversion, parity check, time-out and clear synchronize.
- B. Hendricks, C145.C (Firmware program list), April 19, 1989.
- K. Seino, TS145B.SRC (Test program list), July 7, 1989.
- Motorola, Inc., 16 Bit Microprocessor User's Manual, 1982.
- Motorola, Inc., MC68881/ MC68882 Floating Point Coprocessor User's
Manual, 1987.
- Advanced Micro Devices, Inc., MOS Microprocessors and Peripherals 1985
Data Book.
- Motorola, Inc., AR233, Software links math chip to 68000-family uPs.
- C145 Schematic: ED-218520
- C145 Front Panel: MD-218521
- C145 FP Silkscreen: MD-218522
- C145 Assembly: MD-218544
Summary of CAMAC Commands
| F0A0 | Read vacuum data for number of channels as specified with F16A0
|
|---|
| F0A1 | Read module status.
|
|---|
| F0A2 | Read and clear LAM source register.
|
|---|
| F0A3 | Read LAM mask register.
|
|---|
| F0A4 | Read average vacuum data.
|
|---|
| F0A5 | Read alarm limit.
|
|---|
| F0A6 | Read number of bad pumps.
|
|---|
| F0A7 | Read number of vacuum interface time-outs.
|
|---|
| F0A8 | Read number of FPC errors.
|
|---|
| F0A9 | Read system timer.
|
|---|
| F0A10 | Read alarm retry limit.
|
|---|
| F0A11 | Read current alarm retry count.
|
|---|
| F0A12 | Read number of pumps in average.
|
|---|
| F0A13 | Read vacuum interface reset count
|
|---|
| F0A14 | Read parity error count
|
|---|
| F1A0 | Read status for pumps specified with F17A0.
|
|---|
| F1A1 | Read diagnostic counter registers.
|
|---|
| F1A3 | Read vacuum averaging pool indices.
|
|---|
| F2A0 | Read the high word of the average vacuum reading.
|
|---|
| F2A1 | Read the low word of the average vacuum reading.
|
|---|
| F2A2 | Read the high word of the system timer.
|
|---|
| F2A3 | Read the low word of the system timer.
|
|---|
| F2A4 | Read the high word of the vacuum alarm limit.
|
|---|
| F2A5 | Read the low word of the vacuum alarm limit.
|
|---|
| F2A6 | Read the high word of the average vacuum reading. (Auxiliary)
|
|---|
| F2A7 | Read the low word of the average vacuum reading. (Auxiliary)
|
|---|
| F2A8 | Read the high word of the vacuum averaging sum.
|
|---|
| F2A9 | Read the low word of the vacuum averaging sum.
|
|---|
| F6A0 | Read module number.
|
|---|
| F6A1 | Read firmware version number.
|
|---|
| F6A2 | Make diagnostic memory reads from address specified with F17A2.
|
|---|
| F6A3 | Make diagnostic block memory reads from address specified with F17A2.
|
|---|
| F6A7 | Make diagnostic CAMAC reads.
|
|---|
| F8A0 | Test LAM, Q is returned if LAM is on.
|
|---|
| F9A0 | Reset module.
|
|---|
| F16A0 | Write starting channel and number of channels for F0A0.
|
|---|
| F16A5 | Write vacuum alarm limit.
|
|---|
| F16A10 | Write vacuum alarm retry limit.
|
|---|
| F16A15 | Write diagnostic delay value for CAMAC read/ write tests.
|
|---|
| F17A0 | Write starting channel and number of channels for F1A0.
|
|---|
| F17A1 | Write starting counter and number of counters for F1A1.
|
|---|
| F17A2 | Write address for subsequent F6A2 and F6A3.
|
|---|
| F17A3 | Write starting datapool index for F1A3.
|
|---|
| F19A0 | Write vacuum channel status bits.
|
|---|
| F19A1 | Write status channel to modify.
|
|---|
| F19A2 | Clear diagnostic counters.
|
|---|
| F24A0 | Disable LAM.
|
|---|
| F24A1 | Reset vacuum interface.
|
|---|
| F24A2 | Reset the FPC (68881).
|
|---|
| F26A0 | Enable LAM.
|
|---|
| F26A1 | Reset all word pointers for reading.
|
|---|
| F26A2 | Reset all word pointers for writing.
|
|---|
Vacuum channel and status
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| PE| TE| | | | CHANNEL NUMBER |
+---+---+---+---+---+---+---+---+-------+---+---+---+---+---+---+
15 14 8 7 5 0
PE = Parity Error, TE = Time-out Error
Vacuum data
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| | M | N | E |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
15 12 11 8 7 4 3 0
M.N x 10 ** (-E)
PDR (Packed Decimal Real)
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| | SE| | | | EXPO |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
15 14 12 11 8 7 4 3 0
SE = Sign of Exponent
+---------------+---------------+---------------+---------------+
| | | | MANT16 | Decimal
+---------------+---------------+---------------+---------------+ Point
+---------------+---------------+---------------+---------------+
| MANT15 | | | |
+---------------+---------------+---------------+---------------+
Words 3 through 5 are not shown here.
SPBR (Single Precision Binary Real)
+---+-------------------------------+---------------------------+
| S | BIASED EXPONENT (8) | FRACTION (7) |
+---+-------------------------------+---------------------------+
15 14 7 6 0
S E-127
(-1) x 2 x 1.F
+---------------------------------------------------------------+
| FRACTION (16) |
+---------------------------------------------------------------+
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