September 9, 1983


The CAMAC 175 HCRM module is used to encode tevatron clock events on the tevatron clock. The module contains 16 channels, which may be independently triggered externally or from the CAMAC dataway. Each time a channel is triggered an event is transmitted on the clock. The 16 channels are prioritized to allow for an orderly generation of clock events in the case of simultaneous triggers to two or more channels. Any number of 175 modules may be connected together via a front panel ribbon cable in order to increase the number of available encoding channels. This front cable terminates at the Tevatron Clock transmitter, which converts the parallel data from the 175 module to serial Modified Manchester code for transmission around the accelerator and distant points.


The module supports the following CAMAC function codes:
Read module number, returns 175 base 10 on R1-R16.

F(16)*A(n) n=0-15
Write channel event register. Each channel contains an 8 bit register which determines the event code assigned to that channel. Event codes are 0-255 decimal.

F(0)*A(n) n=0-15
Read channel event register. Reads the event code assigned to that particular channel.

Write enable/disable register. The enable/disable register allows individual channels to be enabled or disabled for external triggers.

Channel Ch15Ch14Ch13Ch12 Ch11Ch10Ch9Ch8 Ch7Ch6Ch5Ch4 Ch3Ch2Ch1Ch0
Bit 16151413 1211109 8765 4321
  MSB                   LSB
0=Channel disabled
1=Channel enabled

This register does not affect the CAMAC trigger command F(25)*A(n). Individual channels may still be triggered by CAMAC command even when external triggers are disabled for that particular channel.

Read enable/disable register. The format for the read enable/disable register command is the same as for the write command.

Trigger from CAMAC. Channels may be triggered by CAMAC command. The subaddress 0-15 determines the channel to be triggered.

Read LAM register. Each channel is capable of initiating a LAM to the crate controller. The LAM register indicates which channel(s) have LAM conditions.

Channel Ch15Ch14Ch13Ch12 Ch11Ch10Ch9Ch8 Ch7Ch6Ch5Ch4 Ch3Ch2Ch1Ch0
Bit 16151413 1211109 8765 4321
  MSB                   LSB
1=LAM condition exists

The LAM register is cleared whenever the F(4)*A(12) command is received. See the discussion below on LAMs.

Write LAM mask register. The LAM for any channel may be masked with the LAM mask register, and a LAM condition at the masked channel will no longer affect the LAM line from the module. If a LAM condition exists for a particular channel and the channel is subsequently masked with the F(17)*A(13) command, the mask takes effect immediately.

Channel Ch15Ch14Ch13Ch12 Ch11Ch10Ch9Ch8 Ch7Ch6Ch5Ch4 Ch3Ch2Ch1Ch0
Bit 16151413 1211109 8765 4321
  MSB                   LSB
0=Mask LAM
1=Enable LAM

Read LAM mask register. The format for reading the LAM mask register is the same as for writing the register.

Test Look At Me (LAM). The F(8)*A(15) command returns the state of the module LAM line on the Q line.
Q=0The LAM line is not set.
Q=1The LAM line is set.

Module reset. A reset does the following:
  1. All channels are disabled...external triggers are ignored
  2. All channel event registers are set to 255 decimal...the no-op code.
  3. The LAM register is cleared.
  4. All LAMs are masked.


Normal timing of the module is such that a clock event will be transmitted ton the Tevatron Clock starting 1.3 uSec from the time the channel is triggered. This holds for both external triggers and triggers from the CAMAC dataway. This time will never be less than 1.3 uSec, but it can extend to 1.4 uSec depending on the relative phasing of the incoming trigger ant the 10MHz Tevatron Clock signal.

The 16 channels in the 176 module are prioritized with channel 0 having the highest priority and channel 15 the lowest. When a particular channel is triggered, either externally or from CAMAC, one of several actions will occur.

If no other events from higher priority channels are pending )about to be transmitted), the event will be placed on the tevatron clock 1.3 uSec after the trigger is received. However, if any event from any channel is in the process of being transmitted when another channel is triggered, the event being transmitted will not be interrupted. The second event will be placed on the clock 1.3 uSec after its trigger...not after the end of the first event.

If a particular channel is triggered and a lower priority channel is triggered simultaneously or soon afterward, the higher priority channel is unaffected by the lower priority event. As before, the high priority event will start 1.3 uSec after the trigger for that event is received. In this case the timing for the lower priority channel is altered since it is now impossible to start the second event 1.3 uSec after its trigger without interrupting the event already being transmitted. In effect, the lower priority channel is held off until the higher priority event has been transmitted. In this case there is a .2 uSec delay from the end of the high priority event until the start of the low priority event.

In the case where a low priority event has been triggered and a higher priority event is triggered soon after the first, one of two possible conditions applies.

  1. If the transmission of the low priority event has begun, it continues without interruption. The higher priority event will start 1.3 uSec after its trigger. (The time to transmit a single event is only 1.0 uSec).
  2. If the transmission of the low priority event has not begun when the trigger for the high priority event is received, the low priority event will be "bumped" and will be transmitted after the high priority event. As before, the start of the high priority will be 1.3 uSec after its trigger and it will be followed by the low priority event. There will be a .2 uSec separation between the end of the first event and the start of the second event.
In this manner it is possible for a low priority channel to be bumped several times by higher priority channels. In this situation there may be several microseconds of delay from the time a channel is triggered until the associated event is transmitted on the tevatron clock.


The front panel of the 175 module contains 2 LEMO type connectors labeled PI and PO. (Priority In and Priority Out). These connectors are used to prioritize the various 175 modules when more than one is used in a system. The resulting daisy chain determines the relative priorities of the modules. No connection is made to the PI input of the highest priority card. The PO output of the highest priority card is connected to the PI input of the next highest module. This continues for all 175 modules in the system. When these connections are made, the combined channels are all prioritized according to their position (0-15) within the individual modules and the position of a particular module within the group. For example, all the channels in the 2nd priority modules are lower in priority then the 16 channels of the 1st priority module.

4.0 LAMS

The discussion in the previous section shows that it is possible to have extended delays from the time a trigger is received until the event is placed on the clock. This situation occurs when event traffic is high. In this case it is possible for a low priority channel to be triggered several times in rapid succession with subsequent loss of one or more events. It is this situation which causes a LAM to be raised for the affected channel. The LAM is latched and will not clear until the LAM register is read or until the module is reset. The affected channel continues to operate, however, and additional events may be lost if this high traffic condition persists or is repeated. A Lam therefore, indicates that an event from the associated channel has not been transmitted and that the total number of transmitted events is less than the number of triggers. This situation indicates that the affected channel is of too low priority for the assigned event and the event should be reassigned to a higher priority channel.


1LCH 0 external trigger 1RGND
2LCH 1 external trigger 2RGND
3LCH 2 external trigger 3RGND
4LCH 3 external trigger 4RGND
5LCH 4 external trigger 5RGND
6LCH 5 external trigger 6RGND
7LCH 6 external trigger 7RGND
8LCH 7 external trigger 8RGND
9LCH 8 external trigger 9RGND
10LCH 8 external trigger 10RGND
11LCH 10 external trigger 11RGND
12LCH 11 external trigger 12RGND
13LCH 12 external trigger 13RGND
14LCH 13 external trigger 14RGND
15LCH 14 external trigger 15RGND
16LCH 15 external trigger 16RGND
17L  17R 
18L  18R 

Security, Privacy, Legal