TEVATRON CLOCK SYSTEM
HCRM 175 CAMAC MODULE

D.Beechy
September 9, 1983

1.0 GENERAL DESCRIPTION

The CAMAC 175 HCRM module is used to encode tevatron clock events on the tevatron clock. The module contains 16 channels, which may be independently triggered externally or from the CAMAC dataway. Each time a channel is triggered an event is transmitted on the clock. The 16 channels are prioritized to allow for an orderly generation of clock events in the case of simultaneous triggers to two or more channels. Any number of 175 modules may be connected together via a front panel ribbon cable in order to increase the number of available encoding channels. This front cable terminates at the Tevatron Clock transmitter, which converts the parallel data from the 175 module to serial Modified Manchester code for transmission around the accelerator and distant points.

2.0 CAMAC FUNCTION CODES

F(6)*A(0)

Read module number, returns 175 base 10 on R1-R16.

F(16)*A(n) n=0-15

Write channel event register. Each channel contains an 8 bit register which determines the event code assigned to that channel. Event codes are 0-255 decimal.

F(0)*A(n) n=0-15

Read channel event register. Reads the event code assigned to that particular channel.

F(17)*A(0)

Write enable/disable register. The enable/disable register allows individual channels to be enabled or disabled for external triggers.

Format

Channel	Ch15	Ch14	Ch13	Ch12	Ch11	Ch10	Ch9	Ch8	Ch7	Ch6	Ch5	Ch4	Ch3	Ch2	Ch1	Ch0
Bit	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1
	MSB															LSB
0=Channel disabled
1=Channel enabled

This register does not affect the CAMAC trigger command F(25)*A(n). Individual channels may still be triggered by CAMAC command even when external triggers are disabled for that particular channel.

F(1)*A(0)

Read enable/disable register. The format for the read enable/disable register command is the same as for the write command.

F(25)*A(n)

Trigger from CAMAC. Channels may be triggered by CAMAC command. The subaddress 0-15 determines the channel to be triggered.

F(4)*A(12)

Read LAM register. Each channel is capable of initiating a LAM to the crate controller. The LAM register indicates which channel(s) have LAM conditions.

Format

Channel	Ch15	Ch14	Ch13	Ch12	Ch11	Ch10	Ch9	Ch8	Ch7	Ch6	Ch5	Ch4	Ch3	Ch2	Ch1	Ch0
Bit	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1
	MSB															LSB
1=LAM condition exists

The LAM register is cleared whenever the F(4)*A(12) command is received. See the discussion below on LAMs.

F(17)*A(13)

Write LAM mask register. The LAM for any channel may be masked with the LAM mask register, and a LAM condition at the masked channel will no longer affect the LAM line from the module. If a LAM condition exists for a particular channel and the channel is subsequently masked with the F(17)*A(13) command, the mask takes effect immediately.

Format

Channel	Ch15	Ch14	Ch13	Ch12	Ch11	Ch10	Ch9	Ch8	Ch7	Ch6	Ch5	Ch4	Ch3	Ch2	Ch1	Ch0
Bit	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1
	MSB															LSB
0=Mask LAM
1=Enable LAM

F(1)*A(13)

Read LAM mask register. The format for reading the LAM mask register is the same as for writing the register.

F(8)*A(15)

Test Look At Me (LAM). The F(8)*A(15) command returns the state of the module LAM line on the Q line.

Q=0	The LAM line is not set.
Q=1	The LAM line is set.

F(12)*A(0)

Module reset. A reset does the following:

1. All channels are disabled...external triggers are ignored
2. All channel event registers are set to 255 decimal...the no-op code.
3. The LAM register is cleared.
4. All LAMs are masked.

3.0 TIMING/PRIORITY

The 16 channels in the 175 module are prioritized with channel 0 having the highest priority and channel 15 the lowest. When a particular channel is triggered, either externally or from CAMAC, one of several actions will occur.

If no other events from higher priority channels are pending )about to be transmitted), the event will be placed on the tevatron clock 1.3 uSec after the trigger is received. However, if any event from any channel is in the process of being transmitted when another channel is triggered, the event being transmitted will not be interrupted. The second event will be placed on the clock 1.3 uSec after its trigger...not after the end of the first event.

If a particular channel is triggered and a lower priority channel is triggered simultaneously or soon afterward, the higher priority channel is unaffected by the lower priority event. As before, the high priority event will start 1.3 uSec after the trigger for that event is received. In this case the timing for the lower priority channel is altered since it is now impossible to start the second event 1.3 uSec after its trigger without interrupting the event already being transmitted. In effect, the lower priority channel is held off until the higher priority event has been transmitted. In this case there is a .2 uSec delay from the end of the high priority event until the start of the low priority event.

In the case where a low priority event has been triggered and a higher priority event is triggered soon after the first, one of two possible conditions applies.

1. If the transmission of the low priority event has begun, it continues without interruption. The higher priority event will start 1.3 uSec after its trigger. (The time to transmit a single event is only 1.0 uSec).
2. If the transmission of the low priority event has not begun when the trigger for the high priority event is received, the low priority event will be "bumped" and will be transmitted after the high priority event. As before, the start of the high priority will be 1.3 uSec after its trigger and it will be followed by the low priority event. There will be a .2 uSec separation between the end of the first event and the start of the second event.

3.1 MODULE TO MODULE PRIORITY

4.0 LAMS

5.0 I/O CONNECTIONS