CONTROLS
CAMAC 193
TRANSIENT
RECORDER
Controls Hardware Release No. 69.1
(Firmware Version # 1.0)
CAMAC 193 Module
Eight Channel Transient Recorder
K. C. Seino and J. G. Smedinghoff
August 17, 1989
TABLE OF CONTENTS
1. INTRODUCTION
2. SPECIFICATIONS
2.1 Board C
2.2 Board P
2.3 System
3. FIRMWARE DESCRIPTION
3.1 Vectored Interrupt Handling
3.2 CAMAC Command Request Clearing
3.3 CAMAC Read Buffer Content Flag
3.3.1 CAMRD1 Macro
3.3.2 Successive CAMAC Read
3.4 ADC Data Collection Modes
3.4.1 Single Channel Read
3.4.2 Snapshot
3.4.3 Transient Recorder
4. CAMAC COMMANDS AND DATA FORMATS
4.1 F0A0 4.2 F0AN 4.3 F1A0 4.4 F1A1
4.5 F2A0 4.6 F2FN 4.7 F3A1 4.8 F3A2
4.9 F3A3 4.10 F4A0 4.11 F6A0 4.12 F6A1
4.13 F6A2 4.14 F6A3 4.15 F6A4 4.16 F6A7
4.17 F8A0 4.18 F9A0 4.19 F16A1 4.20 F16A2
4.21 F16A3 4.22 F16A13 4.23 F16A14 4.24 F16A15
4.25 F17A1 4.26 F17A2 4.27 F18A1 4.28 F18A2
4.29 F18A4 4.30 F19A0 4.31 F19A1 4.32 F19A2
4.33 F19A3 4.34 F24A0 4.35 F26A0 4.36 F28A1
4.37 F28A2 4.38 F30A1 4.39 F30A2
5. HARDWARE DESCRIPTION
5.1 Board-C
5.2 Board-P
5.3 Memory Map
5.4 CAMAC Command Management
5.4.1 General Command Control
5.4.2 Read Command Control
5.5 CAMAC F & A to Interrupt Vector Conversion
5.6 Trip Clock Event Test
5.7 Front Panel
5.7.1 Board-C
5.7.2 Board-P
5.8 I/O Connections
6. FUSEWARE
7. REFERENCES
8. DRAWINGS
APPENDIX A
A.1 Summary of CAMAC Commands
A.2 FOP Command Summary
A.3 Debugger Command Summary
1. INTRODUCTION
The 193 module is a medium speed analog data acquisition member of the
CAMAC 19X family. The module has a multiplexed 12 bit ADC subsystem
consisting of a multiplexer, an instrumentation amplifier, a sample/ hold
amplifier and an ADC. The module supports up to eight analog channels in
the
voltage range from -10.24 to 10.235 volts.
The module consists of two pc boards with common front panel. The
Board-
C is a computer/ CAMAC interface board which contains a Z8002, RAM, PROM,
clock event sources, interrupt controllers, a multichannel timer and a CAMAC
interface. The Board-P is a peripheral board which consists of a ADC
subsystem and a time-stamp counter.
The 190 module can be operated in three plot modes, i.e., Mode A, Mode
B
and Mode C. However, the 193 module is only operated in Plot Mode C, pre-
triggered recording. In this mode, data is continuously collected and
placed
in a circular memory buffer at the occurrence of each sample trigger until
the
selected arm source goes active. At that time the module accepts a selected
number of sample triggers and then stops. At each sample trigger, a common
time-stamp is first read, and then all eight analog channels are digitized
and
read in succession.
The hardware of the CAMAC 19X family had been designed by W. Knopf. In
order to overcome some of the shortcomings of the original design, the 193
design was done to include (1) Read module status without interrupting CPU,
(2) Direct FA to vector conversion is done in single PROM and (3) Clear-cut
synchronization between CAMAC and CPU is done in two sets of tandem flip-
flops.
The software model of the 193 module was very similar to the one of the
191, and therefore the 193 firmware was derived from the one for the 191.
2. SPECIFICATIONS
2.1 Board C
(1) CPU: Z8002 clocked at 6 MHz
(2) Memory: 44K bytes of RAM, 16K bytes of PROM
(3) TCLK event sources: One for time-stamp reset and seven for general
use
(4) External inputs: Four arm and trigger signals
(5) Timer: AMD Am9513A (five timing channels)
(6) Interrupt controller: Two AMD Am9519As
(7) RS232 port: One
(8) CAMAC interface: FA to vector conversion done in single PROM,
which
generates up to 256 interrupt vectors
2.2 Board P
(1) ADC: 10 usec conversion per channel, 12-bit resolution, selectable
up to 8 differential channels, -10.24 to 10.235V voltage range,
+/- 35V input voltage protection
(2) Time-stamp counter: Clock rate selectable for 100 KHz, 10 KHz,
1 KHz or 100 Hz; 16-bit counter
2.3 System
(1) Single channel read: ADC data and time-stamp are read with F2AN
and
F2A0 respectively.
(2) Snapshot: F17A1 specifies arm event (clock or external), F18A1
sets
the delay (0 to 65535 msec), data is collected for 8 channels
after delay from arm event, data and time-stamp can be read with
F0AN and F0A0 respectively.
(3) Transient record: Recording starts upon receipt of F17A2 or F30A2
and stops number of triggers after arm event, F17A2 specifies arm
(clock or ext.) and trigger (clock, ext. or int.), F18A4 specifies
sample period (100 to 655350 usec), F18A2 specifies delay (0 to
2047
triggers), buffered data can be read in three ways - ADC data for
channel, ADC data and time-stamp for channel, and ADC data for
multichannels.
3. FIRMWARE DESCRIPTION
The C193 firmware consists of initialization, background processing,
clock event source routines, debugger routines, trap handlers, heart beat
and
trap event interrupt routines, CAMAC interrupt routines, FOP typecode
service
routines, an interrupt vector table and RAM allocations.
3.1 Vectored Interrupt Handling
CAMAC commands, arm and trigger events and the heart beat timing gain
attention from the CPU as a vectored interrupt. The priority of vectored
interrupts is determined with PLD6 and two Am9519As (UICs). The C193 has
the
following priority scheme on vectored interrupts.
PRIORITY | EVENT | NOTE
-------------+---------------------------------+-------------------
0 (highest)| CAMAC command |
1 | Transient record arm | UIC-A, level 1
2 | Transient record clk sample trg | UIC-A, level 2
3 | Snapshot arm | UIC-A, level 3
4 | | UIC-A, level 4
5 | | UIC-A, level 5
6 | | UIC-A, level 6
7 | | UIC-A, level 7
-------------+---------------------------------+-------------------
8 | External transient record arm | UIC-B, level 0
9 | External transient sample trg | UIC-B, level 1
10 | External snapshot arm | UIC-B, level 2
11 | | UIC-B, level 3
12 | Transient internal sample trg | UIC-B, level 4
13 | | UIC-B, level 5
14 | Snapshot sample delay | UIC-B, level 6
15 (lowest) | Heart beat | UIC-B, level 7
When more than one interrupt requests are pending, the one with the
highest priority is honored. Once an interrupt is acknowledged, further
vectored interrupts are disabled until the acknowledged interrupt is
completely serviced. (A FCW value of 4800 is loaded into the system memory.
The value disables vectroed interrupts.) This prevents multiple interrupt
acknowledgement. One has to remember that other exceptions (reset, traps,
nonmaskable interrupt and nonvectored interrupt) are still honored by the
CPU
while a vectored interrupt is being serviced.
3.2 CAMAC Command Request Clearing
The CAMAC command arrives at the C193, and it generates an interrupt
request if there is not any other command pending. When the CPU
acknowledges
the request, it clears the request in the interrupt service routine. The
software has a control over the time when to clear and does not allow next
command to come in before it reads the data. The reader is suggested to
read
(5.4.1) in HARDWARE DESCRIPTION.
3.3 CAMAC Read Buffer Content Flag
The address of a CAMAC read command service routine is stored in the
register R14. The address of the current service routine is compared with
the
one of the previous routine (stored in R14), and a proper action is taken
based upon the comparison result.
3.3.1 CAMRD1 Macro
This is a macro to generate code for a CAMAC read command which returns
one word of data. The Q response is returned every other time the command
is
executed so that only fresh data may be returned to the host.
3.3.2 Successive CAMAC Read
With a CAMAC read command such as F3A1, a block of data may be read
from
a buffer. In the service routine for F3A1, the current command is compared
with the previous one, and the data pointer is advanced to next point only
if
there is a command match. If there is not, the data is acquired with the
unchanged pointer and returned to the host.
3.4 ADC Data Collection Modes
There are three different modes of ADC data collection. They are
single
channel read, snapshot and transient recorder.
3.4.1 Single Channel Read
Upon receipt of F2AN (N = 1 to 8), the time-stamp is read and a
specified
channel is digitized. The ADC data is returned to the host when it is
ready.
The time-stamp is read with the F2A0 command.
3.4.2 Snapshot
An arm event is specified with the F17A1 command. Data is collected
for
all the eight channels after a specified delay from the arm event (the delay
is specified with F18A1). The time-stamp and the ADC data are read with
F0A0
and F0AN (N = 1 to 8) respectively. Snapshot may be taken once or
repeatedly.
3.4.3 Transient Recorder
Transient recording starts upon receipt of F17A2 or F30A2, and it stops
a
specified number of sample triggers after the F28A2 command or a specified
arm
event. The arm and the trigger are specified with F17A2, and the internal
sample rate is specified with F18A4. The delay is specified with F18A2.
4. CAMAC COMMANDS AND DATA FORMATS
The reader should remember one thing. The hardware ADC Channels 0 thru
7
are called as Channels 1 thru 8 in the firmware.
4.1 F0A0
Read snapshot time-stamp. The time-stamp of the most recent snapshot
occurrence is returned.
4.2 F0AN
Read snapshot ADC data value for Channel N. The ADC data value of
Channel N for the most recent snapshot occurrence is returned where N = 1
thru
8. (Note that Channels are called 0 thru 7 in the hardware.)
4.3 F1A0
Read LAM source register. The LAM source register is organized as
follows.
+---------------------------------------------------------------+
|IBR| | | | | | | | | | | | | | S | T |
| | | | | | | | | | | | | | | N | R |
+---------------------------------------------------------------+
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TR Transient recorder buffered data is ready to be read.
SN Snapshot data is ready to be read.
IBR "I've been reset", the module has been reset. This bit can be
cleared using FOP typecode #9.
4.4 F1A1
Read LAM mask register. The format is identical to the LAM source
register. A bit which is set in the mask register will permit generation of
a
module LAM due to that LAM source. Other bits will not generate LAM unless
they are set. The state of the bits as read by the F1A0 command is
unchanged.
(In a polling application, all bits could be masked off but the status can
be
still tested by reading the LAM source.) At a module reset, the LAM mask
register is initialized to FFFF (hex).
4.5 F2A0
Read time-stamp at the time of last single channel digitize. The
module
returns the 16-bit value of the time-stamp register associated with the last
single channel digitize (F2AN). The read is non-destructive, subsequent
reads
will return the same value (until after another single channel read is
issued).
4.6 F2AN
Read single channel data (N = 1 to 8, note that Channels are 0 to 7 in
the hardware). The time-stamp may be read via F2A0. The data format is as
follows.
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| S | 12 - BIT TWO'S COMPLEMENT DATA | UNDEFINED |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
4.7 F3A1
Read buffered transient recorder data for a single channel (Mode 1).
The
value returned is pointed to by the Mode-1 data pointer. The Mode-1 data
pointer is incremented to the next data point after each execution. No-Q
will
be returned if transient recording is turned off, the Mode-1 pointer has
past
the end of data, or transient recording is in progress. The F16A1 command
is
used to set the Mode-1 data pointer to point to a specified channel and its
data.
4.8 F3A2
Read buffered transient recorder data alternating time-stamp and ADC
data
with time-stamp returned first (Mode 2). The value returned is pointed to
by
the Mode-2 data pointer. No-Q will be returned if transient recording is
turned off, the Mode-2 data pointer has past the end of data, or transient
recording is in progress. The F16A2 command is used to set the Mode-2 data
pointer to point to a specified channel and its data.
4.9 F3A3
Read buffered transient recorder data, i.e., time-stamps and ADC data
for
all eight channels (Mode 3). The value returned is pointed to by the Mode-3
data pointer. The Mode-3 data pointer is incremented to the next data point
after each execution of F3A3. No-Q will be returned if transient recording
is
turned off, the Mode-3 data pointer has past the end of data, or transient
recording is in progress. The F16A3 command is used to set the Mode-3 data
pointer to point to a specified channel and its data.
4.10 F4A0
Read module status. The module status bits are organized as follows.
Bit-0; heart beat OK, Bit-1; ADC busy, Bit-2; trip TCLK event test OK
This command is implemented in the hardware, and it does not interrupt the
CPU. Q is always returned.
4.11 F6A0
Read module ID number. The number 193 (C1 hex) is returned.
4.12 F6A1
Read module firmware veresion number. A 16-bit value is returned. The
most significant byte is the major version number (release), and the least
significant byte is the minor version number (modification level).
4.13 F6A2
Read 16-bit module configuration/ status word. The time-stamp period
as
measured during initialization is returned along with other module status.
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| UNDEFINED | LE| | TSP | UNDEFINED | TR |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LE LAM is enabled.
TSP Time-stamp period measured at module reset
0 = 10 usec, 1 = 100 usec, 2 = 1 ms, 3 = 10 ms,
4 = no clock present
TR Transient recorder status
0 = off, 1= collecting data before arm event,
2 = collecting data after arm event,
3 = collection complete, data available for reading
4.14 F6A3
Read FOP status word. The word is organized as follows.
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| STATUS | TYPECODE (TC) |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
15 8 7 0
TC 8-bit typecode with which the high byte (status) is associated.
0 implies status is from last command transmission on F19A2.
STATUS is specific to the typecode indicated in the low byte. It is
is treated as a signed byte with the following convention.
> 0 partial or qualified success
= 0 success
< 0 error
4.15 F6A4
Read FOP reply data. Typecode-specific data is to be returned to the
host. The amount of data which is available is also typecode-specific. It
may be implicit for the typecode or it may have been specified by the host
in
a preceding command and data transmission sequence. The familiar No-Q retry
procedures are required in any case.
4.16 F6A7
Read hardware debugging value. This value increments each time an F6A7
is done, and it is reset to zero when an F16A15 is done. The amount of time
that this command uses is determined by the delay value written by F16A15.
4.17 F8A0
Test module LAM. The Q response indicates whether the module is
requesting LAM (Q = true) or not (Q = false). This command is implemented
entirely in the hardware and does not interrupt the module CPU.
Consequently,
No-Q retries are not required. A single access always returns the proper
status.
4.18 F9A0
Reset module. This command always returns Q. This command is
implemented entirely in the hardware and is equivalent to pressing the reset
button on the module front panel. It causes the module CPU to be reset, and
the ensuing module initialization may take as much as 100 milliseconds.
Attempts at communication before reset is complete will result in No-Q.
4.19 F16A1
Write transient recorder Mode-1 data pointer.
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| CHAN (0-8) | | DATA POINT NUMBER (0-2047) |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
15 12 10 0
CHAN channel number (0 for time-stamp, 1 to 8 for ADC channel 1 to
8)
DATA
POINT number of transient recorder data point (0 = oldest,
NUMBER 2047 = newest)
This command sets the channel number and data point number for F3A1
(Mode-1 transient recorder read). The data point number is incremented
after
each F3A1.
4.20 F16A2
Write transient recorder Mode-2 data pointer.
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| CHAN (1-8) | | DATA POINT NUMBER (0-2047) |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
15 12 10 0
CHAN channel number (1 to 8)
DATA
POINT number of transient recorder data point (0 = oldest,
NUMBER 2047 = newest)
This command sets the channel number and data point number for F3A2
(Mode-2 transient recorder read). The data point number is incremented
after
each two F3A2's.
4.21 F16A3
Write transient recorder Mode-3 data pointer.
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| CHAN (0-8) | | DATA POINT NUMBER (0-2047) |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
15 12 10 0
CHAN starting channel number (0 = time-stamp, 1 to 8 for ADC
channels 1 to 8)
DATA
POINT starting number of transient recorder data point (0 = oldest,
NUMBER 2047 = newest)
This command sets the channel number and data point number for F3A3
(Mode-3 transient recorder read). The channel number is incremented after
each F3A3 (modulo 9). When the channel number rolls over to 0, the data
point
number is incremented.
4.22 F16A13
Upon receipt of this commmand, the module firmware writes a test
pattern
in the transient recorder buffer and declares the data ready to be read.
The
command specifies where in the buffer the test pattern will start. (0-2047)
4.23 F16A14
Test CAMAC hardware for writes. This command will be delayed for a
time
specified by the most recent F16A15, and it will then compare the host data
with the hardware test counter. If they are different, LAM will be set.
The
hardware test counter is then incremented.
4.24 F16A15
Write delay value and reset the hardware test counter for F6A7 (read
test) and F16A14 (write test). The value written by this command determines
how long subsequent F6A7 and F16A14 will be delayed in units of 1.833
microseconds. F16A15 also resets the hardware test counter to zero.
4.25 F17A1
Write snapshot arm control word. Snapshot data available flag in the
LAM
source register will be cleared. Data is collected for all the 8 channels
after a specified delay from the ARM event (the snapshot is taken N
milliseconds after ARM happens, N is written by F18A1). The format of the
control word is as follows. Unused bits should be filled with zeros.
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| | AD| | AS |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
15 8 7 1 0
AS Arm Source
0 = cancel data acquisition, 1 = ARM on clock event source #1,
2 = ARM on external source #2,
3 = ARM on clock event source #1 or external source #2
AD Arm Disable
If 1, the ARM source is disabled after the first arm event and
snapshot is taken only once. If 0, future arm events will
cause
additional snapshot to be taken, overwriting previous data.
4.26 F17A2
Write transient recorder arm and trigger control word. The data
available flag in the LAM source register will be cleared. Data is
collected
for all 8 channels on every sample trigger. The transient recorder stops
digitizing N sample triggers (written by F18A2) after the ARM event. The
format of the control word is as follows. Unused bits should be filled with
zeros.
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| | TS | | AS |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
15 9 8 1 0
AS Arm Source
0 = cancel data acquisition, 1 = ARM on clock event source #1,
2 = ARM on external source #4,
3 = ARM on clock event source #1 or external source #4
TS Trigger Source
0 = internal timer (synchronized to time-stamp reset),
1 = undefined, 2 = clock event source #2, 3 = external source
#3
4.27 F18A1
Write delay value for snapshot. The snapshot will be taken N (delay
value) milliseconds after a selected ARM event. Valid delay values are in
the
range 0 to 65535 (millisecond).
4.28 F18A2
Write arm delay value for transient recorder. The transient recorder
stops taking data and the buffered data becomes available for reading N
(delay
value) samples after the selected ARM event. Valid delay values are in the
range 0 to 2047 (sample triggers).
4.29 F18A4
Write internal transient recorder sample period (in units of
microseconds). The actual value must be greater than or equal to 10 (i.e.,
100 usec) due to throughput considerations. The timer register is loaded
immediately upon receipt of this command and will change the rate of
transient
recorder data acquisition in progress.
4.30 F19A0
Write LAM mask register. See F1A0 for the register bit organization.
4.31 F19A1
Configure any of the eight available clock event sources. The host may
program each of the eight sources independtly to make it active on the
occurrence of one or more clock events. If more than one clock events are
specified, the source becomes active on the logical OR of the specified
events. The host may selectively disable clock events from activating a
source. Sources 1-7 are available to the host for use in specifying general
arm and trigger conditions. Source 0 is dedicated for resetting the time-
stamp counter. The data format is as follows.
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| CLOCK EVENT # (0-255) | | DS | CM |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
15 8 5 3 2 0
CM Command Code
0 Reset all, clears all clock events for all the sources.
1 Disable all events for the source specified with DS.
2 Disable all events and enable one event for the source
specified with DS.
3 Disable a single event for the source specified with DS.
4 Enable a single event for the source specified with DS.
5-7 Undefined, treated as no-ops.
DS Decoder Source
0 Time-stamp reset source
1 Transient recorder arm source
2 Transient recorder sample trigger source
3 Snapshot reference time source
4.32 F19A2
Write FOP command. This CAMAC command is used to begin and/or end an
FOP
command to the module's typecode processor.
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
|SNM|XEQ| | TYPECODE (TC) |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
15 14 8 7 0
SNM Start receiving New Message on F19A3. Current contents of the
received message buffer are lost.
XEQ End of message to module, execute requested action with
supplied
data (if any).
TC 8-bit command code (1-255). Typecode 1-15 are strictly
reserved
for functions common to all members of the 190 family. All
other
typecodes are implementation-specific and are assigned by the
module programmer. The same typecode should be specified on
both
the SNM and XEQ transmissions.
Note that if the SNM and XEQ bits are both set then there is no message
data to be transmitted on F19A3, all meaning is implicit in the typecode
itself and execution of the typecode handler will begin immediately. In
this
case all data previously transmitted via F19A3 are lost.
Error returns:
-1 Ambiguous command, neither start nor stop flag is set.
-2 Undefined typecode.
4.33 F19A3
Up to 256 words of 16-bit data will be accepted on this command
following
an FOP command to start a new message on F19A2. These data will be placed
in
a temporary buffer and are available to the typecode handler routine when an
execute command is received on F19A2.
4.34 F24A0
Disable module LAM. (At module reset, LAM is enabled.)
4.35 F26A0
Enable module LAM. (At module reset, LAM is enabled.)
4.36 F28A1
Generate snapshot arm event.
4.37 F28A2
Generate transient recorder arm event.
4.38 F30A1
Restart snapshot with latest F17A1 data. Executing this command is
equivalent to re-executing the most recently received F17A1 command.
4.39 F30A2
Restart transient recording with latest F17A2 data. Executing this
command is equivalent to re-executing the most recently received F17A2
command.
5. HARDWARE DESCRIPTION
The module consists of Board-C, Board-P, a 50-contact ribbon cable/
connector assembly and a front panel. The Board-C functions as a micro-
computer, a CAMAC interface and a TCLK (Tevatron Clock) decoder/ event
source.
The Board-P functions as a MADC (Multiplexed ADC) and a time-stamp counter.
5.1 Board-C
The card on the left side of the module is called 'Board-C', and it
contains the follwing.
(1) CPU: Zilog Z8002 microprocessor clocked at 6 MHz
(2) Memory: 44K bytes RAM, 16K bytes EPROM
(3) Interrupt controller: Two AMD Am9519As
(4) Timer: AMD Am9513A (five timing channels)
(5) TCLK event source: One for time-stamp reset and seven for general use
(6) RS232 port: Signetics 2651 communication interface and Linear Tech.
LT1081 driver/ receiver
(7) CAMAC interface: Command decoder (providing up to 256 interrupt
vectors), 16-bit read and write registers, command managing circuits
and LAM circuit
(8) Others: 16-bit data display on front panel, external trigger connec-
tions for 4 signals on front/ rear
5.2 Board-P
(1) ADC: 10 us/ ch. conversion time, 12-bit resolution, selectable up to
8 channels, input voltage range of -10.24V to +10.235V, input voltage
protection range of +/- 35V
(2) Time-stamp counter: 16 bits, clock rate selectable for 100 KHz, 10
KHz,
1 KHz or 100 Hz
5.3 Memory Map
Memory Map of CAMAC 193 Module with Z8002
0 +------------------------+
| |
| |
| PROM (16Kb) | 4000
| | Clock event RAM
4000 +------------------------+ 4200
| | I/O page
5000 +------------------------+ 4300
| | P-Board I/O page
| |
| | 5000
8000 + +
| |
| RAM (44Kb) |
| |
| |
C000 + +
| |
| |
| |
| |
FFFF +------------------------+
5.4 CAMAC Command Management
5.4.1 General Command Control
All the CAMAC commands except F4A0, F8A0 and F9A0 are processed through
the circuit shown in Fig. 1a. The circuit has two D-type flip-flops, which
are connected together in tandem. The CAMAC dataway cycle is totally
asynchronous with the CPU memory cycle. The two flip-flops synchronize the
CAMAC cycle with the CPU cycle in an orderly manner.
When there is not any command pending, GCMD (General Command) in the
figure arrives at Pin-CK of the flip-flop on the left, and the low to high
transition of the signal triggers the flip-flop. If QD1 is low, CMPND
(Command Pending) stays false, and the Q is generated as shown in Fig. 1b.
At
the lagging edge of S2, the flip-flop on the right is set by QP1, and the
interrupt request INT1 is sent to the CPU. When the CPU acknowledges the
request, it clears the request with CMWDEN (CAMAC Write Data Enable) during
the interrupt service routine. If QD1 is high, CMPND becomes true, and the
Q
is not generated as shown in Fig. 1c.
5.4.2 Read Command Control
When a read command arrives, it is processed through the circuit
discussed
in (5.4.1), and if another command is not pending, the interrupt request
INT1
is generated. The CPU fetches and latches a word of data for the next read
command during the service routine. If a word of data has been latched with
the previous read command, the current command reads it. The read command
control circuit is shown in Fig. 2a. When RCMD (Read Command) arrives, if
QD2
is true (data ready), and if CMTCH (Command Match) is high, what result from
these are (1) RDVAL (Read Data Valid) = true, (2) RDEN (Read Data Enable) =
true and (3) Q = true as shown in Fig. 2b. When RCMD arrives, if QD2 is not
true, the results are (1) RDVAL = false, (2) RDEN = false and (3) Q = false
as
shown in Fig. 2c. When RCMD arrives, even if QD2 is true, if CMTCH is
false,
QD2 is cleared 100 nsec after the leading edge of GCMD (that is before S1
arrives), and the results are (1) RDVAL = false, (2) RDEN = false and (3) Q
=
false. Synchronization between RCMD and CMRDLT (CAMAC Read Data Latch) is
done by two flip-flops shown in Fig. 2a.
5.5 CAMAC F & A to Interrupt Vector Conversion
One simple device called 82S147A (512 x 8 bipolar PROM) does convert
CAMAC
functions/ subaddresses to interrupt vectors. The device can be programmed
for any applications that one would imagine, and if one wants to change the
repertoire of F/As, all that he has to do is to program another PROM. The
only restriction is the fact that 9-bit information produces 8-bit
information
or that the Z8002 reads 8-bit vectors.
5.6 Trip Clock Event Test
When the C193 is being operated in the transient record mode, a Main
Ring
ramp trip occurs and stops transient recording. The trip event is detected
in
the A0 area and sent to the MAC room, where Trip Event Request module
receives
and puts the event on the Tevatron clock system. The event is broadcast to
C193 modules in the Main Ring service buildings.
The C193 and its companion (Trip Event Request module) have circuits
which
allow the operator to test the trip event connections even when a real trip
event does not exit. The operator sits at the console and sends CAMAC
commands to the C193 and the companion module. He first enables the event
test on the companion module, which sends repeated, simulated events to the
C193 via the clock system. The events interrupt the CPU on the C193, and
the
CPU keeps triggering an one-shot as often as it is interrupted. The
Q-output
of the one-shot stays high and provides a high (true) level if it is kept
triggered. The operator reads module status on the C193. If the trip event
test bit stays true, he knows that the test is successful.
5.7 Front Panel
5.7.1 Board-C
(1) N: When on, it indicates that the module is addressed by the crate
controller.
(2) LAM: When on, it indicates that the module is asserting the LAM.
(3) LMEN: When on, it indicates that the LAM is enabled.
(4) HB: When on, it indicates that the CPU is alive and functioning
normally under program control.
(5) TCK: When on, it indicates that the 10 MHz carrier of the Tevatron
clock is detected at the module.
(6) DSB<0:15>: These are used for various diagnostic purposes, e.g.,
indication of module initialization and data collection in progress,
display of ADC data for checking and adjusting offset and gain.
(7) EXT TRG<1:4>: These are connected to Interrupt Levels 11 thru 8 to
facilitate general purpose external arm and sample trigger sources.
(8) RS232: It provides a standard asynchronous serial terminal port.
(9) RESET: When depressed, it resets the module hardware and restarts
the module software.
(10) +5 and -5: These indicate the status on +5 and -5 power supplies.
5.7.2 Board-P
(1) ADBSY: When on, it indicates that the ADC is active.
(2) +5, +15 and -15: These indicate the status on +5, +15 and -15 power
supplies.
5.8 I/O Connections
The I/O connections are made via the 36-contact Viking type connectors.
Viewed from the front of the module, the Board-C is located on the left slot
and the Board-P is on the right.
Board-C
Contact Singal Contact Signal
1L Gnd 1R Gnd
2L nc 2R TCKIN
10L Gnd 10R ETRG4
12L Gnd 12R ETRG3
14L Gnd 14R ETRG2
16L Gnd 16R ETRG1
17L RXD 17R TXD
18L Gnd 18R nc
Board-P
Contact Signal Contact Signal
1L Gnd 2L CH7A
3L CH7B 4L CH6A
5L CH6B 6L CH5A
7L CH5B 8L CH4A
9L CH4B 10L CH3A
11L CH3B 12L CH2A
13L CH2B 14L CH1A
15L CH1B 16L CH0A
17L CH0B 18L Gnd
Notes: L = left, R = right, nc = no connections
6. FUSEWARE
There are a total of seven PLDs (Programmable Logic Devices) used on the
C193 module, six on Board-C and one on Board-P. The documentations on these
devices exist on the VAX or an IBM PC/ AT, and their file names are listed
as
follows.
(1) PLD1: FAVCT2.LS on SYS$AUX1:[EXORMACS.C193], FA to Vector Conversion
No. 2
(2) PLD2: PLD2.ABL on A:\C193, this device decodes CAMAC FAN and produces
general command, read command, F4A0 and F9A0, and it also generates Q
and X responses.
(3) PLD3: PLD3.ABL on A:\C193, this device produces select lines for
memory
blocks (PROM, RAM, TCLK event channels, I/O page and PI/O page) and
vectored interrupt acknowledge.
(4) PLD4: PLD4.ABL on A:\C193, this device produces select lines for
CAMAC
registers, latches, timer, PCI, UICA and UICB.
(5) PLD5: PLD5.ABL on A:\C193, this device produces LAM enable, LAM,
read/
write strobes, and R/W strobes for data-bit display.
(6) PLD6: PLD6.ABL on A:\C193, this device produces ready, vectored
inter-
rupt request and acknowledge signals.
(7) PLD11: PLD11.ABL on A:\C193, this device produces time-stamp read,
ADC
data read and ADC status read signals.
7. REFERENCES
(1) J. Smedinghoff, C193.Z8K (Firmware program list), Feb. 4, 1989.
(2) K. Seino, TS193A.Z8K (Test program list), June 13, 1989.
(3) A. D. Thomas, et. al., CAMAC 190 Multimode Buffered MADC Controller,
Controls Hardware Release No. 26.2, March 12, 1987.
(4) Zilog, Inc., Z8000 CPU Technical Manual, January, 1983.
(5) Advanced Micro Devices, Inc., MOS Microprocessors and Peripherals 1985
Data Book.
8. DRAWINGS
(1) Board C Schematic: ED-218464
(2) Board C Master Drawing: MD-218523
(3) Board C Assembly: MD-218524
(4) Board P Schematic: ED-218465
(5) Board P Master Drawing: MD-218525
(6) Board P Assembly: MD-218526
(7) Front Panel: MD-218462
(8) Front Panel Silkscreen: MD-218463
APPENDIX A
A.1 Summary of CAMAC Commands
F0A0 Read time-stamp of most recent snapshot
F0A(n) Read snapshot ADC value w/o time-stamp (n = 1-8)
F1A0 Read LAM source register
F1A1 Read LAM mask register
F2A0 Read time-stamp at last single channel read
F2A(n) Read single channel ADC data w/o time-stamp (n = 1-8)
F3A1 Read transient recorder data in mode 1
F3A2 Read transient recorder data in mode 2
F3A3 Read transient recorder data in mode 3
F4A0 Read module status (this is an 'all hardware' command)
F6A0 Read module number (C1 hex, 193 decimal)
F6A1 Read software version (major number/ rev. level number)
F6A2 Read module status/ configuration word
F6A3 Read diagnostic protocol status
F6A4 Read diagnostic protocol data
F6A7 Hardware read test (module diagnostic)
F8A0 Test LAM (this is an 'all hardware' command)
F9A0 Reset module (this is an 'all hardware' command)
F16A1 Write mode 1 data pointer (for F3A1)
F16A2 Write mode 2 data pointer (for F3A2)
F16A3 Write mode 3 data pointer (for F3A3)
F16A13 Write test data into transient recorder buffer
F16A14 Write data for hardware write test
F16A15 Write delay value for hardware read and write tests (F6A7)
F17A1 write arm and trigger control word for snapshot
F17A2 Write arm and trigger control word for transient recorder
F18A1 Write snapshot delay value (in msec)
F18A2 write transient recorder arm delay count (in sample triggers)
F18A4 Write transient recorder internal sample period
F19A0 Write LAM mask register
F19A1 Write clock event source configuration
F19A2 Write diagnostic protocol command
F19A3 Write diagnostic protocol data
F24A0 Disable LAM
F26A0 Enable LAM
F28A1 Generate snapshot arm event
F28A2 Generate transient recorder arm event
F30A1 Restart snapshot with latest F17A1 data
F30A2 Restart transient recorder with latest F17A2 data
A.2 FOP Command Summary
Typecode Meaning
1 Initialize read of FOP command data
2 Initialize read clock event source table
3 Initialize read/ clear error summary
4 Initialize memory dump at starting address
5 Patch memory locations
6 not used
7 not used
8 not used
9 Clear "I've Been Reset" LAM bit
A.3 Debugger Command Summary
Command Parameters Description
DR none Display registers
DW start-adr last-adr Display memory word
GO transfer-adr Go to user program
SW adr (terminate w/ CR) Substitute memory word
TS none Time-stamp test
XD none eXit debug mode
All debugger parameters are entered in hexadecimal and must be in
upper case. Parameters and the command name must be separated by a
blank. A full-duplex terminal running at 9600 baud is assumed.
Debugger mode is entered whenever a character is received from the
terminal. While in the debugger mode all other module functions are
suspended (including any CAMAC I/O). When finished, always issue an
XD command or reset the module.
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