CONTROLS CAMAC 279 ED-35978
CONTROLS HARDWARE RELEASE NO. 43.0
CAMAC 279 Module
Beam Sync Clock Interface / Timer
Robert J. Ducar
February 19, 1985
5 SPARES
1 DESCRIPTION
The one-wide CAMAC 279 module provides two separate
timing pulses with programmmable delay from a BSCLK event.
Either MRBS or TVBS Clock may be applied as the activating
clock. These clocks, which are derived by dividing by seven
the Main Ring rf and Tevatron proton rf accelerating
frequencies, operate at approximately 7.5 MHz and have one
clock pulse every seven rf buckets.
Each of the two delay channels provides a programmable
delay range of 0 to 65535 BSCLK ticks with a resolution of one
tick or 7 rf cycles. In that there are exactly 159 BSCLK
ticks (1113 rf cycles) per revolution of beam, the maximum
delay corresponds to 412.17 turns which is approximately 8.65
milliseconds. Programmed delays are typically scaled in rf
cycles or in machine revolutions, not in time. The 277
module, which is a 177 modified to accept the slower clock,
can provide longer delays, though the resolution is ten BSCLK
ticks or 70 rf cycles at best.
The specific operating conditions for each of the two
delay channels of the 279 module are programmed in on-board
PALs. Once armed and enabled, a channel can delay from any
specified BSCLK event or events. A channel may be
continuously armed, or be armed by any combination of BSCLK or
TCLK events, or by externally applied levels or transitions.
It is anticipated that this module, with minor timing
modifications, may also serve as a TCLK Interface / Timer.
Module number 287 has been reserved for this application.
This hardware variation would provide delay resolution of 100
nanoseconds with a maximum delay of 6.5535 milliseconds from
any referenced TCLK event(s).
2 CAMAC 279 OP CODES
All codes return module Q and X immediately.
This module asserts LAM only when the BSCLK
input is inactive.
F(0) A(0) Read Channel 0 Delay Value
---------
R16 - R1
-----------------------------------
MSB - Delay Value - LSB
The delay value is an unsigned integer
with the LSB valued as one BSCLK pulse.
F(0) A(1) Read Channel 1 Delay Value
---------
R16 - R1
-----------------------------------
MSB - Delay Value - LSB
The delay value is an unsigned integer
with the LSB valued as one BSCLK pulse.
F(1) A(0) Read Status
---------
R16 - R9 | R8 - R1
---------------------------------
0 | Status
R8: CH1EN - Channel 1 Enabled
R7: CH0EN - Channel 0 Enabled
R6: CH1ARM - Channel 1 Armed
R5: CH0ARM - Channel 0 Armed
R4: CH1TMG - Channel 1 Timing
R3: CH0TMG - Channel 0 Timing
R2: BSCLKP - Beam Sync Clock Present
R1: TCLKP - TCLK Present
F(6) A(0) Read Module Number
---------
R16 - R9 | R8 - R1
-------------------------------
0 117 Hex, 279 Dec
F(6) A(1) Read Version Number
---------
R16 - R9 | R8 - R1
-----------------------------
0 Version Number
F(7) A(0) Dummy Read - No Data Are Returned
---------
F(9) A(0) Reset Module
---------
This command is a logical or with Z*S2 and
power up clear. A reset sets the delay
values for both Channel 0 and Channel 1 to
zero. The effect of module reset upon the
enable/disable states of the two channels
is determined by on-board PAL equations.
F(16) A(0) Set Channel 0 Delay Value
----------
W16 - W1
-----------------------------------
MSB - Delay Value - LSB
The delay value is an unsigned integer
with the LSB valued as one BSCLK pulse.
F(16) A(1) Set Channel 1 Delay Value
----------
W16 - W1
-----------------------------------
MSB - Delay Value - LSB
The delay value is an unsigned integer
with the LSB valued as one BSCLK pulse.
F(24) A(0) Disable Channel 0
----------
F(24) A(1) Disable Channel 1
----------
F(26) A(0) Enable Channel 0
----------
F(26) A(1) Enable Channel 1
----------
3 CAMAC 279 MODULE - I/O ASSIGNMENTS
A = R B = L
POS SIGNAL POS SIGNAL
--- ----------- --- -----------------
1L Common 1R BSCLK Input
2L Common 2R BSCLK Output
3L Common 3R Common
4L Common 4R TCLK Input
5L Common 5R TCLK Output
6L Common 6R Common
7L Common 7R BSDCE Output
8L Common 8R TDCE Output
9L Common 9R Common
10L Common 10R Ext Trig 1 Input
11L Common 11R Ext Trig 0 Input
12L Common 12R Common
13L Common 13R CH1TMG
14L Common 14R CH0TMG
15L Common 15R Common
16L Common 16R Channel 1 Output
17L Common 17R Channel 0 Output
18L Common 18R Common
The Ext Trig 0 and 1 inputs are generally terminated in
100 ohms. All other inputs and outputs are 50 ohm compatible.
Channel 0 and 1 outputs may be wire-or'd.
4 CAMAC 279 MODULE - FRONT PANEL
The CAMAC 279 module has the following front panel features:
N led: Red (stretched)
LAM led: Red, on when BSCLK input inactive
TCLK led: Green, on when TCLK is present
BSCLK Input: Lemo, 50 Ohm terminated
BSCLK Out: Lemo, 74S140 driver
led, Green (stretched), on when BSCLK active
Revolution Markers:
A: Lemo, Amber led, BSCLK event $AA
B: Lemo, Amber led, BSCLK event $BB
C: Lemo, Amber led, BSCLK event $CC
A+B+C: Lemo, Green led, BSCLK events $AA + $BB + $CC
All leds are stretched. 74128 drivers.
BSDCE: Lemo, Red led (stretched), 74128 driver.
BSCLK event(s) as determined by PAL equations.
TDCE: Lemo, Red led (stretched), 74128 driver.
TCLK event(s) as determined by PAL equations.
CH0: Lemo, Red led (stretched), 75450B driver.
Channel 0 Output, 1 microsecond pulse, 50 ohm
compatible emitter follower output may be wire-
or'd to Channel 1 Output. The output pulse is
nominally 2.5 volts.
CH1: Lemo, Red led (stretched), 75450B driver.
Channel 1 Output, 1 microsecond pulse, 50 ohm
compatible emitter follower output may be wire-
or'd to Channel 0 Output. The output pulse is
nominally 2.5 volts.
5 SPARES
A supply of CAMAC 279 operational spares will be
maintained on the second floor of the Linac Annex. Caution is
advised in transferring the unique PALs at locations 37, 41,
and 42. Also be sure to set on-board dip switches to the same
configuration.
6 DOCUMENTATION
0812-ED-35978 Schematic
0812-BD-35979 Artwork
0812-BD-35980 Master Drawing
0812-BD-35981 Assembly Drawing
0812-MD-34863 Outline Drawing
0812-MC-35982 Front Panel Mechanical
0812-MC-35983 Front Panel Silkscreen
Controls Hardware Release No. 41
"Beam Sync Clock Event Assignments"
7 PALS DOCUMENTATION
Directory: DEVL::USR$DISK3:[DUCAR.PALS]
Filenames: 27905A.DAT First NAF Decoder 82S153
27912A.DAT Second NAF Decoder 82S153
27921x.DAT Third NAF Decoder 82S153
27936A.DAT BSCLK Event Decoder #1 82S153
27937x.DAT TCLK Event Decoder 82S153
27941x.DAT BSCLK Event Decoder #2 82S153
27942x.DAT Channel Arming Controller 82S153
CAUTION: Filenames listed with "x" are generally unique
to specific installations and version numbers
of installed 279 modules. Refer to filename
[DUCAR.DOC]CMC279.VER for more specific infor-
mation.
rjd: DEVL::USR$DISK3:[DUCAR.DOC]CMC279.RNO
