CONTROLS HARDWARE RELEASE NO. 62.0CONTROLS
CAMAC 372
ED-218425
CONTROLS HARDWARE RELEASE NO. 62.0
CAMAC 372 Module
Digital Function Generator
Alexander Matyushin
Robert J. Ducar
March 25, 1988
1 DESCRIPTION
2 MEMORY ORGANIZATION
6 DIP SWITCH SETTINGS
6.1 Configuration Select At Location #316.2 Update Frequency Select At Location #45
7 CAMAC 372 MODULE - FRONT PANEL
8 SPARES
9 DOCUMENTATION
10 PALS DOCUMENTATION
1 DESCRIPTION
The CAMAC 372 module is a high speed digital function
generator appropriate for systems requiring high resolution
set values at very fast update rates. The module provides
128K x 16 bit of on-board static RAM which may be organized
as a single 32 bit output function or two 16 bit output
functions. Each function may be up to 65K words in length,
though smaller function lengths may be accommodated by use
of unique stop codes. Loading or reading of the memory in
accord with the above organizations is directly
accommodated.
The module is provided with a TCLK interface for
generation of the update frequency and for decoding of
selected events that may serve as start times for the
function(s). The update frequency is hardware selected and
may range from 1KHz to 1Mhz.
The function data may be written in either unsigned
integer or two's compliment format. A unique end of
function data format is recognized to cause a stop of the
function until receipt of the next start time. Functions
are turned ON or OFF synchronous to the occurrence of the
start time. CAMAC read or write operations may be executed
while the module is playing out a function.
The output is capable of being tri-stated and is
accompanied by an update pulse as each new value is
generated.
Consideration is being given to a companion module,
sharing the CAMAC N line, that will provide associated power
supply control and monitor and 16 bit DAC views of the
generated output.
2 MEMORY ORGANIZATION
The on-board static RAM is organized as 128k x 16 bits
requiring a 17 bit address. The user sets the upper 16 bits
of the memory address. The LSB of the memory address is
controlled exclusively by board circuitry and is transparent
to the user. The content of the memory is as follows for a
32 bit output function (F0) that starts at location 00000.
The lower ordered word of the 32 bit function is always at
an even memory location.
ADR + LSB MEMORY CONTENT
-----------------------------
0000 + 0 | <- Lower Ordered Word - LSB | \
----------------------------- 1st Long Word
0000 + 1 | MSB - High Ordered Word -> | /
-----------------------------
0001 + 0 | <- Lower Ordered Word - LSB | \
----------------------------- 2nd Long Word
0001 + 1 | MSB - High Ordered Word -> | /
-----------------------------
0002 + 0 | <- Lower Ordered Word - LSB | \
----------------------------- 3rd Long Word
0002 + 1 | MSB - High Ordered Word -> | /
-----------------------------
| |
-----------------------------
FFFF + 1 | Last Memory Location |
-----------------------------
The content of the memory is as follows for two 16 bit
output functions (F1 and F2) that start at location 00000.
The F1 function is always located at the even locations, and
F2 is always located at the odd locations.
ADR + LSB MEMORY CONTENT
-----------------------------
0000 + 0 | MSB - F1 Data - LSB | 1st F1 Value
-----------------------------
0000 + 1 | MSB - F2 Data - LSB | 1st F2 Value
-----------------------------
0001 + 0 | MSB - F1 Data - LSB | 2nd F1 Value
-----------------------------
0001 + 1 | MSB - F2 Data - LSB | 2nd F2 Value
-----------------------------
0002 + 0 | MSB - F1 Data - LSB | 3rd F1 Value
-----------------------------
0002 + 1 | MSB - F2 Data - LSB | 3rd F2 Value
-----------------------------
| |
-----------------------------
FFFF + 1 | Last Memory Location |
-----------------------------
The length of any of the functions may range up to 65K
points. The end of a function table is specified by unique
stop codes. The stop codes are dependent on the
organization of the memory as a 16 or 32 bit function, and
on the function being defined as a unipolar or bipolar
function. These differing configurations will be set by an
on-board three position DIP switch and will be readable.
Examples of the various stop codes are as follows. Address
xxxx is arbitrary.
For 32 bit Unipolar and Bipolar functions:
ADR + LSB MEMORY CONTENT
| |
-----------------------------
xxxx + 0 | <- Lower Ordered Word - LSB | \
----------------------------- Last Long Word
xxxx + 1 | MSB - High Ordered Word -> | /
-----------------------------
xxxx+1 + 0 | F F F F | \
----------------------------- F0 UP Stop Code
xxxx+1 + 1 | F F F F | /
-----------------------------
| |
-----------------------------
xxxx + 0 | <- Lower Ordered Word - LSB | \
----------------------------- Last Long Word
xxxx + 1 | MSB - High Ordered Word -> | /
-----------------------------
xxxx+1 + 0 | 0 0 0 0 | \
----------------------------- F0 BP Stop Code
xxxx+1 + 1 | 8 0 0 0 | /
-----------------------------
For a 16 bit Unipolar function F1:
ADR + LSB MEMORY CONTENT
| |
-----------------------------
xxxx + 0 | MSB - F1 Data - LSB | Last F1 Value
-----------------------------
xxxx + 1 | MSB - F2 Data - LSB | nth F2 Value
-----------------------------
xxxx+1 + 0 | F F F F | F1 UP Stop Code
-----------------------------
xxxx+1 + 1 | MSB - F2 Data - LSB | n+1 F2 Value
-----------------------------
| |
For a 16 bit bipolar function F1:
ADR + LSB MEMORY CONTENT
| |
-----------------------------
xxxx + 0 | MSB - F1 Data - LSB | Last F1 Value
-----------------------------
xxxx + 1 | MSB - F2 Data - LSB | nth F2 Value
-----------------------------
xxxx+1 + 0 | 8 0 0 0 | F1 BP Stop Code
-----------------------------
xxxx+1 + 1 | MSB - F2 Data - LSB | n+1 F2 Value
-----------------------------
| |
For 16 bit Unipolar and Bipolar function F2:
ADR + LSB MEMORY CONTENT
| |
-----------------------------
xxxx + 0 | MSB - F1 Data - LSB | nth F1 Value
-----------------------------
xxxx + 1 | MSB - F2 Data - LSB | Last F2 Value
-----------------------------
xxxx+1 + 0 | MSB - F1 Data - LSB | n+1 F1 Value
-----------------------------
xxxx+1 + 1 | F F F F | F2 UP Stop Code
-----------------------------
| |
| |
-----------------------------
xxxx + 0 | MSB - F1 Data - LSB | nth F1 Value
-----------------------------
xxxx + 1 | MSB - F2 Data - LSB | Last F2 Value
-----------------------------
xxxx+1 + 0 | MSB - F1 Data - LSB | n+1 F1 Value
-----------------------------
xxxx+1 + 1 | 8 0 0 0 | F2 BP Stop Code
-----------------------------
| |
If a stop code is not recognized, the playout of
functions will automatically stop as the Program Address
Pointer (PAP) rolls over from FFFF to 0000. Functions F1
and F2 need not stop at the same time, though these
functions always begin at the same start time.
3 START TIMES & MULTIPLE TABLES
A Start Time (ST) is defined as the initialization of
the module to begin playing out a particular function (F0)
or functions (F1 and F2). ST is sourced by the decode of a
single TCLK event, by the logical or of two or more TCLK
events, or by occurrence of an external ST. ST is initially
synchronized with the extracted 10 MHz clock of TCLK. Any
memory cycles in process are allowed to complete. The
derived 1 MHz memory clock and the fixed update frequency
are also synchronized at this time. Memory read/write
control circuitry is allowed to synchronize with the 1 Mhz
memory clock. ST is also the occasion for effecting
synchronous ON or OFF of the function(s).
Additionally, upon receipt of ST, the Program Address
Pointer is set to the starting point of a function table.
This set value is limited to the four most significant bits
of PAP with all of the lower ordered bits being set to zero.
This translates to a maximum of sixteen 8K word blocks, each
supporting a maximum 4K table for an F0 function or two 4K
tables for functions F1 and F2. Memory reads are performed
from locations PAP and PAP +1 and values are loaded
immediately in both holding and output registers and PAP is
then incremented to PAP + 2. The occurrence of the first
update pulse writes the output register and is followed by a
double memory read cycle and write of the holding register.
Activating TCLK events and function starting addresses
are fixed to the specific application and are programmed
into on-board PALs.
The beginning of the playout of a function always
encounters a fixed delay from receipt of an activating clock
event or from the externally applied ST pulse. This delay
accommodates the completion of extant CAMAC operations and
the fetch of the first two words of function data from
memory. As measured from the leading edge of ST or from the
leading edge of DVLD from the TCLK decoder chip, the start
delay is as follows:
Tsd = 1.900 usec +/- 50 nsec
4 CAMAC 372 OP CODES
All listed codes return module Q and X immediately
unless otherwise noted. An on-board DIP switch confiqures
the module as a F0 generator or as a F1 and F2 generator.
The selected configuration determines whether or not certain
codes will return Q. This module will never assert LAM.
It is to be noted that application of TCLK is
absolutely necessary for the proper operation of this
module. The control circuits for the memory utilize the 10
MHz frequency extracted from TCLK for all read and write
operations. It is also to be noted that the memory chips
remain powered by a battery when module power is removed in
order to retain loaded data.
F(20)A(x) Set Write/Read Address Pointer
W16 - W1
--------------------------
|MSB - ADR - LSB|
This general operation sets the upper 16 bits of the
17 bit Write/Read Address Pointer, WRAP. The associated
sub address of this operation determines how the LSB of
the counter is handled, whether or not a read is to
occur from the indicated address, and whether or not the
upper 16 bits of WRAP are allowed to increment. This
operation is normally followed by strings of F(0)A(0)
operations for reading or F(16)A(0) operations for
writing of function values.
F(20)A(0) Set WRAP for Sequential Read of F0
[ Q only returned for F0 configuration ]
This is the first operation for reading a 32 bit
function. A read is performed with WRAP LSB equal to
zero, data deposited in the CAMAC Register (CREG), and
WRAP LSB is then toggled to one. Subsequent strings of
F(0)A(0) operations will read CREG, request another read
of memory, overwrite CREG, and cause the WRAP to
increment.
F(20)A(1) Set WRAP for Sequential Read of F1
[ Q only returned for F1 & F2 configuration ]
This is the first operation for reading the lower
ordered 16 bit function (F1) which resides in the even
locations of memory. A read is performed, data is
deposited in CREG, and an increment is applied to the
upper 16 bits of WRAP. WRAP LSB is always equal to
zero. Subsequent strings of F(0)A(0) operations will
read CREG, request another read of memory, overwrite
CREG, and cause the upper 16 bits of WRAP to increment.
F(20)A(2) Set WRAP for Sequential Read of F2
[ Q only returned for F1 & F2 configuration ]
This is the first operation for reading the upper
ordered 16 bit function (F2) which resides in the odd
locations of memory. A read is performed, data is
deposited in CREG, and an increment is applied to the
upper 16 bits of WRAP. WRAP LSB is always equal to one.
Subsequent strings of F(0)A(0) operations will read
CREG, request another read of memory, overwrite CREG,
and cause the upper 16 bits of WRAP to increment.
F(20)A(3) Set WRAP for Sequential Write of F0
[ Q only returned for F0 configuration ]
This is the first operation for writing a 32 bit
function. The upper 16 bits of WRAP are loaded and WRAP
LSB is set to zero. Subsequent strings of F(16)A(0)
operations will write the memory and cause the WRAP to
increment.
F(20)A(4) Set WRAP for Sequential Write of F1
[ Q only returned for F1 & F2 configuration ]
This is the first operation for writing the 16 bit F1
function. The upper 16 bits of WRAP are loaded and WRAP
LSB is set and held to zero. Subsequent strings of
F(16)A(0) operations will write the memory and cause the
upper 16 bits of WRAP to increment.
F(20)A(5) Set WRAP for Sequential Write of F2
[ Q only returned for F1 & F2 configuration ]
This is the first operation for writing the 16 bit F2
function. The upper 16 bits of WRAP are loaded and WRAP
LSB is set and held to one. Subsequent strings of
F(16)A(0) operations will write the memory and cause the
upper 16 bits of WRAP to increment.
F(0)A(0) Read Memory Data
R16 - R1
--------------------------
|MSB - DATA - LSB|
F(16)A(0) Write Memory Data
W16 - W1
--------------------------
|MSB - DATA - LSB|
F(1)A(0) Read F0 Function Status and Control
[ Q only returned for F0 configuration ]
R16-R6 R5 R4 R3 R2 R1 |
------------------------------------
| 0 | OVF | TCLS | STP | ON | BP |
R1: F0 in Bipolar Format
R2: F0 Function ON
R3: F0 Function Stopped
R4: TCLK Active Status
R5: Program Address Pointer Overflow
F(1)A(1) Read F1 Function Status and Control
[ Q only returned for F1 & F2 configuration ]
R16-R6 R5 R4 R3 R2 R1 |
------------------------------------
| 0 | OVF | TCLS | STP | ON | BP |
R1: F1 in Bipolar Format
R2: F1 Function ON
R3: F1 Function Stopped
R4: TCLK Active Status
R5: Program Address Pointer Overflow
F(1)A(2) Read F2 Function Status and Control
[ Q only returned for F1 & F2 configuration ]
R16-R6 R5 R4 R3 R2 R1 |
------------------------------------
| 0 | OVF | TCLS | STP | ON | BP |
R1: F2 in Bipolar Format
R2: F2 Function ON
R3: F2 Function Stopped
R4: TCLK Active Status
R5: Program Address Pointer Overflow
F(6)A(0) Read Module Number
R16 - R1
-------------------------
| 0174 Hex, 372 Dec |
F(9)A(0) Reset Module
This command is a logical or with Z*S2 and power-up
clear. It initializes all logic circuitry, acts as an
immediate OFF for the function(s), and clears all output
registers to zero output.
F(26)A(0) Synchronous ON for F0 Function
Synchronous ON for F1 and F2 Functions
F(26)A(1) Synchronous ON for F1 Function
[ Q only returned for F1 & F2 configuration ]
F(26)A(2) Synchronous ON for F2 Function
[ Q only returned for F1 & F2 configuration ]
F(24)A(0) Synchronous OFF for F0 Function
Synchronous OFF for F1 and F2 Functions
F(24)A(1) Synchronous OFF for F1 Function
[ Q only returned for F1 & F2 configuration ]
F(24)A(2) Synchronous OFF for F2 Function
[ Q only returned for F1 & F2 configuration ]
5 CAMAC 372 MODULE - I/O ASSIGNMENTS
Rear I/O: 36 Position Edge Connector A = R B = L
-- Assignment for F0 Configuration --
POS SIGNAL POS SIGNAL
--- -------------- --- ----------------
1L Common 1R Common
2L D30 2R D31 (F0 MSB)
3L D28 3R D29
4L D26 4R D27
5L D24 5R D25
6L D22 6R D23
7L D20 7R D21
8L D18 8R D19
9L D16 9R D17
10L D14 10R D15
11L D12 11R D13
12L D10 12R D11
13L D8 13R D9
14L D6 14R D7
15L D4 15R D5
16L D2 16R D3
17L D0 (F0 LSB) 17R D1
18L UPDATE 18R OUTPUT CONTROL
-- Assignment for F1 and F2 Configuration --
POS SIGNAL POS SIGNAL
--- -------------- --- ----------------
1L COMMON 1R COMMON
2L D14 2R D15 (F2 MSB)
3L D12 3R D13
4L D10 4R D11
5L D8 5R D9
6L D6 6R D7
7L D4 7R D5
8L D2 8R D3
9L D0 (F2 LSB) 9R D1
10L D14 10R D15 (F1 MSB)
11L D12 11R D13
12L D10 12R D11
13L D8 13R D9
14L D6 14R D7
15L D4 15R D5
16L D2 16R D3
17L D0 (F1 LSB) 17R D1
18L UPDATE 18R OUTPUT CONTROL
DATA OUTPUT: Data are TTL compatible active high out.
The output drivers have a current source maximum of 24 ma.
It is recommended that output data be terminated to ground
at the receiver end with an impedance of no less than 100
ohms.
UPDATE: The Update pulse is an active high 100 nsec
pulse that occurs at the update frequency of the module.
Data change at the low to high transition of the Update
pulse.
OUTPUT CONTROL: This input is pulled-up to +5V on the
module. When brought to the logic low state, the data
output is in the tri-state, high-impedance mode.
6 DIP SWITCH SETTINGS
For all DIP switch settings, 0 corresponds to closed
and 1 corresponds to open.
6.1 Configuration Select At Location #31
Configuration TST f0 BP1 BP2
_________________ --- -- --- ---
Stop Code Enabled 0 x x x
Stop Code Disabled 1 x x x
F0 Unipolar Output x 1 0 0
F0 Bipolar Output x 1 1 1
F1 Unipolar Output x 0 0 x
F1 Bipolar Output x 0 1 x
F2 Unipolar Output x 0 x 0
F2 Bipolar Output x 0 x 1
6.2 Update Frequency Select At Location #45
The update period in microseconds equals the binary
value of the DIP switch plus one. Some useful examples are
as follows:
UPDATE MSB <- Switch -> LSB
--------------------------------------------
Period Frequency 1 2 3 4 5 6 7 8 9 10
--------------------------------------------
1 usec 1 MHz 0 0 0 0 0 0 0 0 0 0
2 usec 500 KHz 0 0 0 0 0 0 0 0 0 1
4 usec 250 KHz 0 0 0 0 0 0 0 0 1 1
10 usec 100 KHz 0 0 0 0 0 0 1 0 0 1
20 usec 50 KHz 0 0 0 0 0 1 0 0 1 1
100 usec 10 KHz 0 0 0 1 1 0 0 0 1 1
1000 usec 1 KHz 1 1 1 1 1 0 0 1 1 1
7 CAMAC 372 MODULE - FRONT PANEL
The CAMAC 372 module has the following front
panel features:
N led: Red (stretched)
TCLK: Input and Output Lemo with Green led
EXT START: Input and Output Lemo
8 SPARES
A supply of CAMAC 372 operational spares is maintained on
the second floor of the Linac Annex. Upon replacement be
sure to check DIP switch settings and all PALS - especially
the PAL at location #57 - for identical version numbers.
9 DOCUMENTATION
0812-ED-218425 Schematic
0812-BD-218426 Artwork
0812-BD-218427 Master Drawing
0812-MD-34863 Outline Drawing
0812-MC-218428 Front Panel Mechanical
0812-MC-218429 Front Panel Silkscreen
10 PALS DOCUMENTATION
Directory: DEVL::USR$DISK3:[DUCAR.PALS]
Filenames: 37209A.DAT 1st NAF Decoder PLS173
37215A.DAT Status & Mod# Generator PLS173
37219A.DAT 2nd NAF Decoder PLS153
37223A.DAT Stop Code Generator PLS173
37227A.DAT Enable & Update Gen PLS173
37238A.DAT Memory Control PLS173
37257x.DAT T Start & PAP Init Adr PLS173
CAUTION: The TCLK decoder PAL at location #57 is
unique to each specific installation.
rjd: DEVL::USR$DISK3:[DUCAR.DOC]CMC372.RNO
PALS DOCUMENTATION
module 37209a title ' CAMAC 372 MODULE A. MATYUSHIN/DUCAR 3-23-88 ' 37209a device 'f173';
F16, F8, F4, F1, F2, A8 pin 1,2,3,4,5,6; A4, A2, A1, S1, N pin 7,8,9,10,11; F0, DF9, Q, X, RD, DF1620 pin 13,14,15,16,17,18; DF6, DF1, NC21, DF0, DF2426 pin 19,20,21,22,23;
H,L,X,Z = 1,0,.X.,.Z.;
"Use standard PALASM operators
@ALTERNATE
equations
;
;
DF0 = /N*F16*F8*/F4*/F2*F1*A8*/A4*/A2*/A1 ;" F(0)A(0)
/DF1620 = /N*/F16*F8*/F4*/F2*F1*A8*/A4*/A2*/A1 + " F(16)A(0)
/N*/F16*F8*F4*/F2*F1*A8*/A4*/A2*/A1*F0 + " F(20)A(0)*F0
/N*/F16*F8*F4*/F2*F1*A8*/A4*/A2*A1*/F0 + " F(20)A(1)*/F0
/N*/F16*F8*F4*/F2*F1*A8*/A4*A2*/A1*/F0 + " F(20)A(2)*/F0
/N*/F16*F8*F4*/F2*F1*A8*/A4*A2*A1*F0 + " F(20)A(3)*F0
/N*/F16*F8*F4*/F2*F1*A8*A4*/A2*/F0 ;" F(20)A(4-5)*/F0
DF1 = /N*F16*F8*/F4*/F2*/F1*A8*/A4*/A2*/A1*F0 + " F(1)A(0)
/N*F16*F8*/F4*/F2*/F1*A8*/A4*/A2*A1*/F0 + " F(1)A(1)
/N*F16*F8*/F4*/F2*/F1*A8*/A4*A2*/A1*/F0 ;" F(1)A(2)
;
DF6 = /N*F16*F8*F4*F2*F1*A8*/A4*/A2*/A1 ;" F(6)A(0)
;
/DF9 = /N*F16*/F8*/F4*/F2*/F1*A8*/A4*/A2*/A1*S1 ;" F(9)A(0)S1
;
DF2426 = /N*/F16*/F8*/F4*F1*A8*/A4*/A2*/A1*S1 + " F(24+26)A(0)S1
/N*/F16*/F8*/F4*F1*A8*/A4*/A2*A1*/F0*S1 + " F(24+26)A(1)S1*/F0
/N*/F16*/F8*/F4*F1*A8*/A4*A2*/A1*/F0*S1 " F(24+26)A(2)S1*/F0
;
/RD = DF0 + DF1 + DF6 " READ
;
/Q = DF0 + DF1 + DF6 + /DF1620 + " CAMAC Q
/N*F16*/F8*/F4*/F2*/F1*A8*/A4*/A2*/A1 + " F(9)A(0)
/N*/F16*/F8*/F4*F1*A8*/A4*/A2*/A1 + " F(24+26)A(0)
/N*/F16*/F8*/F4*F1*A8*/A4*/A2*A1*/F0 + " F(24+26)A(1)*/F0
/N*/F16*/F8*/F4*F1*A8*/A4*A2*/A1*/F0 " F(24+26)A(2)*/F0
/X = DF0 + DF6 + " CAMAC X
/N*F16*F8*/F4*/F2*/F1*A8*/A4*/A2 + " F(1)A(0-1)
/N*F16*F8*/F4*/F2*/F1*A8*/A4*A2*/A1 + " F(1)A(2)
/N*F16*/F8*/F4*/F2*/F1*A8*/A4*/A2*/A1 + " F(9)A(0)
/N*/F16*F8*/F4*/F2*F1*A8*/A4*/A2*/A1 + " F(16)A(0)
/N*/F16*F8*F4*/F2*F1*A8*/A4 + " F(20)A(0-3)
/N*/F16*F8*F4*/F2*F1*A8*A4*/A2 + " F(20)A(4-5)
/N*/F16*/F8*/F4*F1*A8*/A4*/A2 + " F(24+26)A(0-1)
/N*/F16*/F8*/F4*F1*A8*/A4*A2*/A1 " F(24+26)A(2)
;
"DESCRIPTION: This PAL provides the first level of NAF decoding
for the CAMAC 372 module.
end 37209a
module 37215a title ' CAMAC 372 MODULE A. MATYUSHIN/DUCAR 3-23-88 ' 37215a device 'f173';
OVF, DF1, STP2, DF6, STP1, ONF2 pin 1,2,3,4,5,6; A2, A1, BP2, TST, ONF1 pin 7,8,9,10,11; BP1, TCLKS, DB8, DB6, DB5, DB4 pin 13,14,15,16,17,18; DB3, DB2, DB1, DB0, DF16 pin 19,20,21,22,23;
H,L,X,Z = 1,0,.X.,.Z.; "Use standard PALASM operators @ALTERNATE equations
DF16 = DF1 + DF6 " Needed for IF Term
IF (DF1) /DB0 = DF1*/A1*/A2*BP1*BP2 + " Data Bus Bit 0 (LSB)
DF1*/A2*A1*BP1 +
DF1*A2*/A1*BP2 ;
;
IF (DF1) /DB1 = DF1*/A1*/A2*ONF1*ONF2 + " Data Bus Bit 1
DF1*A1*/A2*ONF1 +
DF1*A2*/A1*ONF2;
IF (DF16) /DB2 = DF1*/A1*/A2*STP1*STP2 + " Data Bus Bit 2
DF1*/A2*A1*STP1 +
DF1*A2*/A1*STP2 + DF6
IF (DF1) /DB3 = DF1*TCLKS ;" Data Bus Bit 3
IF (DF16) /DB4 = DF6 + DF1*/OVF " Data Bus Bit 4
IF (DF16) /DB5 = DF6 + DF1*TST " Data Bus Bit 5
IF (DF6) /DB6 = DF6 ;" Data Bus Bit 6
IF (DF6) /DB8 = DF6 ;" Data Bus Bit 8
"DESCRIPTION: This PAL inserts in the internal data bus of the
CAMAC 372 module the Function Status and Control
word and Module Number during appropriate read
commands.
end 37215a
module 37219a title ' CAMAC 372 MODULE A. MATYUSHIN/DUCAR 3-24-88 ' 37219a device 'f153';
F4, DF0, A4, DF1620, A2 pin 1,2,3,4,5; A1, S1, F0, CLSB pin 6,7,8,9; WDC, DF16, WLD, WCK, RSTR pin 11,12,13,14,15; SETR, SCRQ, SLSB, RLSB pin 16,17,18,19;
H,L,X,Z = 1,0,.X.,.Z.;
"Use standard PALASM operators
@ALTERNATE
equations
;
/SETR = /DF1620*F4*/A4*/A2*S1 + " SET Read Memory
/DF1620*F4*/A4*A2*/A1*S1 +
DF0*S1;
;
DF16 = /DF1620*/F4*S1 ;" F(16)A(0)S1
;
/RSTR = DF16 ;" Reset Read Memory
;
/SCRQ = /SETR + DF16 " Set CAMAC Request
;
/WLD = /DF1620*F4 ;" WRAP Load
;
WCK = /WLD*S1 + WDC*/F0 + CLSB*WDC*F0 " WRAP Clock
;
/SLSB = /DF1620*F4*/A4*A2*/A1*S1 + " Set LSB Flip-flop
/DF1620*F4*A4*/A2*A1*S1 ;
/RLSB = /DF1620*F4*/A4*/A2*S1 + " Reset LSB Flip-flop
/DF1620*F4*/A4*A2*A1*S1 +
/DF1620*F4*A4*/A2*/A1*S1 ;
"DESCRIPTION: This PAL provides the second level of NAF decoding
for the CAMAC 372 module, sets the memory access
request, and controls the WRAP Write Read Address
Pointer.
Alternate equation for /RSTR:
/RSTR = /DF1620*F4*/A4*A2*A1*S1 +
/DF1620*F4*A4*/A2*S1
end 37219a
module 37223a title ' CAMAC 372 MODULE A. MATYUSHIN/DUCAR 3-23-88 ' 37223a device 'f173';
MB0, MB1, MB2, MB3, MB4, MB5 pin 1,2,3,4,5,6; MB6, MB8, MB10, MB12, MB14 pin 7,8,9,10,11; MB15, MB13, MB11, MB9, MB7, BP1 pin 13,14,15,16,17,18; F0, BP2, OUT2, OUT1, TST pin 19,20,21,22,23;
H,L,X,Z = 1,0,.X.,.Z.; "Use standard PALASM operators @ALTERNATE equations
OUT2 = MB0*MB1*MB2*MB3*MB4*MB5*MB6*MB7*MB8*MB9*MB10* ;" Stop Code
MB11*MB12*MB13*MB14*/MB15*BP2*/TST + " Comparator Out
/MB0*/MB1*/MB2*/MB3*/MB4*/MB5*/MB6*/MB7*/MB8* ;" for the F2
/MB9*/MB10*/MB11*/MB12*/MB13*/MB14*/MB15*/BP2*/TST ;" Function
OUT1 = MB0*MB1*MB2*MB3*MB4*MB5*MB6*MB7*MB8*MB9*MB10* ;" Stop Code
MB11*MB12*MB13*MB14*MB15*BP1*F0*/TST + " Comparator Out
/MB0*/MB1*/MB2*/MB3*/MB4*/MB5*/MB6*/MB7*/MB8*/MB9* ;" for the F1
/MB10*/MB11*/MB12*/MB13*/MB14*/MB15*/BP1*/TST + " Function
MB0*MB1*MB2*MB3*MB4*MB5*MB6*MB7*MB8*MB9*;
MB10*MB11*MB12*MB13*MB14*/MB15*/F0*BP1*/TST;
"DESCRIPTION: This PAL recognizes stop codes for the
CAMAC 372 module.
end 37223a
module 37227a title ' CAMAC 372 MODULE A. MATYUSHIN/DUCAR 3-23-88 ' 37227a device 'f173';
DF2426, OVF, F2, A2, A1, F0 pin 1,2,3,4,5,6; MC89, STP1, MRRQ, STP2, ONF1 pin 7,8,9,10,11; CLR, ONF2, DSF1, DSF2, Q1, Q2 pin 13,14,15,16,17,18; UPD, OCK1, OCK2, EHC2, EHC1 pin 19,20,21,22,23;
H,L,X,Z = 1,0,.X.,.Z.; "Use standard PALASM operators @ALTERNATE equations
;
EHC1 = ONF1*OVF*MRRQ*/F0*/STP1 + " Enable Hold Register
ONF1*OVF*MRRQ*F0*/STP1 + " Clock 1
ONF1*OVF*MRRQ*F0*/STP2 ;
;
EHC2 = ONF2*OVF*MRRQ*/F0*/STP2 + " Enable Hold Register
ONF2*OVF*MRRQ*F0*/STP1 + " Clock 2
ONF2*OVF*MRRQ*F0*/STP2 ;
;
OCK1 = EHC1*MC89 + /CLR " Output Register Clock 1
OCK2 = EHC2*MC89 + /CLR " Output Register Clock 2 ; /UPD = OCK1 + OCK2 " Update Clock
/DSF1 = /CLR + Q1 + DF2426*/F2*/A2 " Disable Function F1
/Q1 = DF2426*F2*/A2 + DSF1 " DSF1 F-F Output /Q
/DSF2 = /CLR + Q2 + DF2426*/F2*/A1 " Disable Function F2
/Q2 = DF2426*F2*/A1 + DSF2 " DSF2 F-F Output /Q
;
;
"DESCRIPTION: This PAL provides enable signals for the play out of
the function for the CAMAC 372 module and generates
the output register update clocks.
end 37227a
module 37238a title ' CAMAC 372 MODULE A. MATYUSHIN/DUCAR 3-23-88 ' 37238a device 'f173';
QD, QB, QE, QC, QA, CRD pin 1,2,3,4,5,6; CLSB, CRQS, EHC1, EHC2, NC11 pin 7,8,9,10,11; NC13, WDC, CS, MCWR, HCK2, HCK1 pin 13,14,15,16,17,18; WOE, NC20, LSB, WE, OE pin 19,20,21,22,23;
H,L,X,Z = 1,0,.X.,.Z.; "Use standard PALASM operators @ALTERNATE equations
HCK1 = EHC1*QB*/QC ;" Hold Register Clock 1
HCK2 = EHC2*QA*QE ;" Hold Register Clock 2
MCWR = CRQS*CRD*/QD*QE ;" Memory to CAMAC Write
WDC = CRQS*/QA*/QE ;" WRAP Decrement Clock
/WE = CRQS*/CRD*/QB*QE ;" Write Enable
/CS = CRQS*/QA+EHC1*/QE + EHC1*QB + " Chip Select
EHC2*/QE + EHC2*QB
/LSB = EHC2*QC*QA + CRQS*/QA*QE*CLSB " Least Significant Bit
/OE = EHC1*QA +EHC2*QA + CRQS*CRD*/QA*QE " Output Enable
WOE = CRQS*/QA*QE ;" WRAP Output Enable
"DESCRIPTION: This PAL generates memory controls signals (MCRL)
and register strobe for the CAMAC 372 module.
end 37238a
module 37257b title ' CAMAC 372 MODULE A. MATYUSHIN/DUCAR 2-27-90 ' 37257b device 'f173';
EXP, B0, B1, EXT, B2, B3 pin 1,2,3,4,5,6; B4, DVLD, B5, B6, B7 pin 7,8,9,10,11; NC13, NC14, NC15, TD3, NC17, TSTR pin 13,14,15,16,17,18; TD2, TD1, TD0, NC22, PLD pin 19,20,21,22,23;
H,L,X,Z = 1,0,.X.,.Z.; "Use standard PALASM operators @ALTERNATE equations
TSTR = DVLD*/B7*/B6*/B5*B4*/B3*B0 + " $11 $13 $15 $17
DVLD*/B7*/B6*/B5*B4*/B3*B1*/B0 + " $12 $16
DVLD*/B7*/B6*/B5*B4*B3*/B2*/B1*B0 + " $19
DVLD*/B7*/B6*/B5*B4*B2*/B1*/B0 + " $14 $1C
/EXP ;" Ext Reset
;
/TD0 = /TSTR ;" PAP ADR. 0 (LSB)
;
/TD1 = /TSTR ;" PAP ADR. 1
;
/TD2 = /TSTR ;" PAP ADR. 2
;
/TD3 = /TSTR ;" PAP ADR. 3 (MSB)
;
/PLD = TSTR ;" PAP Load
;
"DESCRIPTION: This PAL decodes the TCLK events for the CAMAC 372 module,
defines the four most significant bits of the starting
address, and starts the play out of the function.
end 37257b