CAMAC C377 - Timer Module
A. Franck
May 29, 1985
Table of Contents
^General Description
The CAMAC 377 MODULE provides eight timing channels. Each channel
is composed of a 32 bit counter which is normally clocked by a 1MHz
signal derived from the Tevatron clock. Timing cycles are normally
triggered by events encoded on the Tevatron clock. Each channel may be
programmed independently with respect to delay and clock events.
The programmable channel delay may range from a minimum of 2usec to
a max of FFFF FFFFH microseconds (approx. 1.2 Hrs.). These delays are
based on the 10Mhz Tevatron clock.
The clock events to be used as triggers are selectable and may
include any of the possible 256 events. A maximum of fifteen events are
allowed per channel. A RAM is used on the module as the storage medium
for events.
Two modes are available for writing delays. The normal mode will
load the channel whenever written except when the channel is busy
counting. The sync mode will load the channel only on a busy to
non-busy transition. This mode may delay the loading of the channel,
but minimizes the probability of missing a trigger event during the
loading process. Delays may be written using either mode, but any given
setting must be written in a low-high word order and using the same mode
to be recognized as valid.
Neither mode will interrupt a busy channel to load a new delay. In
the case that a channel is holding a value to be loaded, a pending bit
is set in the channel's readable status word.
Two delay values may be read back per channel; a last written value
and a running value. The two values will be the same unless the pending
bit is set. In the case of multiple setting writes during a pending
state, the last setting written will be used.
The eight channels may be enabled or inhibited separately or as a
group. The channel's status word contains an enable/inhibit status bit.
However, with the exception of the initial enable command, the
enable/inhibit commands are not normally used in this module. Since the
module will internally inhibit and enable channels for new settings,
they need not be executed by the front end (for purposes of new
settings). This decreases front end burden and allows the externally
written inhibit command to be used as a panic button to stop a channel
even if it is busy. Enabling a previously inhibited, loaded channel
will cause the channel to be reloaded and to wait for a trigger.
Provisions are made for an external clock and an external reset.
These are to be used together as an alternative to the Tevatron Clock.
If the external clock frequency is less than 10MHz, the delay time must
be scaled accordingly. A jumper header is provided to allow selected
channels to respond to the external reset signal. Either an external
reset or a Tevatron event may be used for a channel trigger but they may
not be OR'ed.
Module LAM is generated only upon absence of clock signal, either
Tevatron or external. LAM (clock) status is readable by means of each
channel's status word.
This module is provided with a battery backed RAM which allows the
return of operation after a power down. After power up, battery backed
data is tested for validity and, if valid, is used to load counters, set
event triggers, and enable channels as they were configured prior to
power down. Pending settings are not preserved on power down.
The eight outputs each provide a positive 3 volt 1usec pulse upon
timeout. Each has a series output diode to make possible external
OR'ing of channels. If external OR'ing is necessary, care should be
taken to keep the output cables as short as possible because long runs
can produce transmission line mismatch effects.
^CAMAC Functions
|
Notes | A(n) 0 >= n <= 7
n is the channel pointer
|
| * indicates X is returned immediately
but Q is returned on a later read
(Allow about 100 Microseconds)
|
| F(0) A(n)* | Read channel counter value low word, running value
| R16 | | R1
| | C15 | Low Counter Value | C0
|
|
| F(1) A(n)* | Read channel counter value high word, running value
| R16 | | R1
| | C31 | High Counter Value | C16
|
The running values are values actually loaded into the counters.
|
| F(2) A(n)* | Read channel counter value , low word, last written value
| R16 | | R1
| | C15 | Low Counter Value | C0
|
|
| F(3) A(n)* | Read channel counter value , high word, last written value
| R16 | | R1
| | C31 | High Counter Value | C16
|
The last written values may different from the running values if a setting is pending due to a busy condition.
|
| F(4) A(n) | Read events auto increment
| | R16 | | R8 | R7 | | R1
| | Word 1 | Event 1 | Event Count
| | | MSB | | LSB | MSB | | LSB
| | Word 2 | Event 3 | Event 2
| | ... | ... | ...
| | Word 8 | Event 15 | Event 14
|
This command will return two bytes per read. The pointer
will be initialized by any opcode. Q will be delayed on the first
read only. Thereafter, X and Q are returned immediately along with data.
If more than fifteen events are written to a channel, they
will not be stored. Also if reads beyond the event count are
executed, the last byte read will be repeated.
|
| F(5) A(0)* | Read software version number
|
| F(6) A(0)* | Read module number
| R16 | | R1
| | C31 | 0179H (377D) | C16
|
|
| F(7) A(n)* | Read channel status
| R16 | | R5 | R4 | R3 | R2 | R1
| | --0-- | S3 | S2 | S1 | S0
|
| S0 | = 1 if channel is enabled
| | S1 | = 1 if clock present (LAM)
| | S2 | = 1 if a setting is pending
| | S3 | = 1 if a synchronized load is in progress and the channel is in the non-busy phase
| | S4 - S15 | = 0 not used
|
|
| F(9) A(0) | Reset module
- Performs reset as does Z*S2 and power up clear.
- Does a RAM and Battery Backed Data validation.
- Inititializes all non-BBRAM and all counters to 00.
- Re-establishes previous enable conditions, trigger events, and counter settings.
This operation should be allowed 1 second to complete.
|
| F(9) A(1) | This is an F(9) A(0) reset with battery-backed RAM initialization.
Leaves all channels inhibited and all counter values set to 0.
|
| F(16) A(n) | Write channel counter value - low word, normal mode
| w16 | | w1
| | C15 | Low Counter Value | C0
|
|
| F(17) A(n) | Write channel counter value - high word, normal mode
| w16 | | w1
| | C31 | High Counter Value | C16
|
The normal mode load is performed when the channel is not busy.
|
| F(20) A(n) | Write channel counter value - low word, sync mode
| w16 | | w1
| | C15 | Low Counter Value | C0
|
|
| F(21) A(n) | - Write channel counter value - high word, sync mode
| w16 | | w1
| | C31 | High Counter Value | C16
|
The sync mode loads the channel only on a busy to non-busy transition.
| **Note: | The module will accept any value from 0000 0000 to
FFFF FFFFH as a counter value.
It should be noted that the minimum delay the module
can produce is 2 microseconds. Therefore, writing
0 or 1 as a delay will yield a delay of 2 microseconds.
|
|
| F(18) A(n) | Write event number and control byte
| W16 | | W10 | W9 | W8 | | W1
| | Not used | N1 | N0 | E7 - Event Number - E0
| | | Control | Event Number
|
| N0 | = 0 add event
= 1 delete event
| | N1 | = 1 delete all events
| | N2 - N7 | = 0 Not used
|
The event number may range from 00 to FF and once written
to a specified channel, will trigger that channel upon
receiving the event via the Tevatron clock. Fifteen events
may be written. If greater than fifteen are written, the
excess will be ignored. Also repeat writing of an event
will not result in duplicate entries.
|
| F(24) A(n) | Inhibit selected channel
|
| F(26) A(n) | Enable Selected channel
|
| F(28) A(0) | Inhibit all channels
|
| F(30) A(0) | Enable all channels
|
| |
| Note: | - Inhibit / Enable status is read by status read F(7) A(n).
-A channel will reload if inhibited and enabled.
|
|
^Opcode Summary
CAMAC 377 MODULE OPCODE SUMMARY
| F(0) A(n) | Read channel counter value - low word, running value
|
| F(1) A(n) | Read channel counter value - high word, running value
|
| F(2) A(n) | Read channel counter value - low word, last written value
|
| F(3) A(n) | Read channel counter value - high word, last written value
|
| F(4) A(n) | Read event, auto increment
|
| F(5) A(0) | Read software version number
|
| F(6) A(0) | Read module number
|
| F(7) A(n) | Read channel status
|
| F(9) A(0) | Reset module, restore settings
|
| F(9) A(1) | Reset module, including BBRAM, clear settings
|
| F(16) A(n) | Write channel counter value - low word, normal mode
|
| F(17) A(n) | Write channel counter value - high word, normal mode
|
| F(18) A(n) | Write event number and control byte
|
| F(20) A(n) | Write channel counter value - low word, sync mode
|
| F(21) A(n) | Write channel counter value - high word, sync mode
|
| F(24) A(n) | Inhibit selected channel
|
| F(26) A(n) | Enable selected channel
|
| F(28) A(0) | Inhibit all channels
|
| F(30) A(0) | Enable all channels
|
^CAMAC 377 MODULE I/O SPECIFICATIONS
| Inputs | Tevatron clock input |
|
| External clock input |
|
| External reset input |
|
|
Note: Each input is terminated in 50 ohms.
All are available on the front panel or
the I/O connector.
|
| Outputs | Tevatron clock output | This is the
buffered Tevatron clock input which is
made available on the front panel and
the I/O connector. Each output is driven
by a separate 74S140 driver.
|
| Channel 0 - 7 outputs | These are
available on the front panel and the I/O
connector. Each output is driven by a
separate driver capable of driving
3.0 volts into 50 ohms. The output is a
positive 1 microsecond wide pulse. All
outputs use a series diode to enable
external OR'ing of channels.
|
| Indicators | Lam Led | Indicates an absence of clock
signal.
|
| N Led | Indicates a module select has
occurred.
|
| Channel 0 - 7 Leds | Indicates a channel
pulse output has occurred.
|
^I/O Signals
CAMAC 377 MODULE I/O CONNECTOR ASSIGNMENTS
| 1L | Channel 0 out | 1R | Common
|
| 2L | Common | 2R | Ext. Clk. in
|
| 3L | Channel 1 out | 3R | Common
|
| 4L | Common | 4R | Tev. Clk. in
|
| 5L | Channel 2 out | 5R | Common
|
| 6L | Common | 6R | Tev. Clk. out
|
| 7L | Channel 3 out | 7R | Common
|
| 8L | Common | 8R | Ext. Res. in
|
| 9L | Channel 4 out | 9R | Common
|
| 10L | Common | 10R |
|
| 11L | Channel 5 out | 11R | Common
|
| 12L | Common | 12R |
|
| 13L | Channel 6 out | 13R | Common
|
| 14L | Common | 14R |
|
| 15L | Channel 7 out | 15R | Common
|
| 16L | Common | 16R |
|
| 17L | | 17R | Common
|
| 18L | Common | 18R |
|
^CAMAC 377 MODULE OPERATIONAL NOTES
| To Activate a Channel
| - Write a counter value to the timer channel.
- Write an event number to the selected channel.
For multiple event writes, repeat the F(18) command.
- Enable the channel.
|
| To Change a Timer Channel Parameter
| Simply write the new parameter of interest. It
is not necessary to rewrite any other parameter if it does not change.
|
| Timer Characteristics
| - The timers are not reset by events occurring during the time out period.
- The channel enable command reloads the timer and prepares it to receive another trigger.
- Module reads have no effect on timer operation.
- The module uses a stacking procedure to
accept the following commands; F(16),F(17),F(18),
F(20),F(21),F(24),F(26),F(28), and F(30). The stack
write time is about 60 microseconds. Stacking
was done to allow rapid repetitive command
writes to occur. The stack depth is 64 commands.
|
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