module _TSCC40A; flag '-r0'; title ' TEVATRON SERIAL CRATE CONTROLLER II - Slot 24 R. J. DUCAR TSCC40A.DAT 5-16-89 Converted to ABEL using TA' TSCC40A device 'F173'; "Pin definitions PARSP pin 1; QA1 pin 2; QC1 pin 3; B pin 4; QAA pin 5; Y0 pin 6; LDF pin 7; RDF pin 8; QG4 pin 9; QC4 pin 10; QE4 pin 11; GND pin 12; CLR pin 13; XG pin 14; PAC9G pin 15; PAC8G pin 16; ONL pin 17; ONLC pin 18; RPARSP pin 19; EPACG pin 20; ABG pin 21; CD pin 22; AB pin 23; VCC pin 24; equations ABG = !PARSP # ABG & !QA1; "Flying Bit Source Flag AB = ABG # QG4; "Flying Bit Source !CD = QG4; "Advance PIOR Frame Count !PAC8G = RDF & !Y0; "Frame 8 Clock Gate !PAC9G = LDF & !Y0; "Frame 9 Clock Gate !EPACG = QC1 # !EPACG & !ABG & !QC4; "Enable Frame Count Flag XG = QA1 # XG & !ABG & !QE4; "PIOR Transmit Gate !ONLC = !ONL # !CLR; "OFF Line + Clear !RPARSP = !ONL # !CLR # !B "Reset PIOR Response FF # QAA & QG4 & !LDF & !RDF; "DESCRIPTION: This PAL provides the first level of logic control " for the transmission of PIOR frames on the Slot 24 " board of the TSCC II. end _TSCC40A