Tevatron Serial Crate Controller/(TSCC II)

Controls Hardware Release No. 2 (Revised)

R.J. Ducar

November 9, 1981

TEVATRON SERIAL CRATE CONTROLLER

ED-35242/5

Contents

General

1. Serial Transmissions

2. Port A PIOX Operations

3. Port B PIOX Operations

4. TSCC Service Request Levels

5. Port A PIOR Responses

6. Port B PIOR Responses

7. Arbitration

7.1 Port A Arbitration

7.2 Port B Arbitration

8. Block Transfer

9. Miscellaneous Features

Appendix A: I/O and Monitor Connections

Appendix B: TSCC II PALS

General

The Tevatron Serial Crate Controller (TSCC) is a two-ported CAMAC crate controller designed for a 10 MHz bit serial synchronous control network. Serial data transmissions are 50 ohm capatible, low-power, self-clocking and utilize a Biphase Manchester code. Port A is the Host Computer Port and has separate input and output lines (PIOX and PIOR). Port B is also a serial port and is generally symmetric to Port A. The intended function of Port B is to accommodate Local Intelligence or testing facilities. The TSCC allows for arbitration between the two ports by means of programmable crate and slot reserve functions. The TSCC also provides a block transfer return (BTR) path to the Host facilities. The BTR function, which is controlled only by Port A, shares operation of the CAMAC dataway with Ports A and B. BTR operates in the UQC mode.

As referenced from an associated TSCC Link Driver*, a CAMAC serial transaction is completed in less than 20 psec, plus cable delay. The BTR function is capable of transferring data at better than 750 kbyte/ sec rate.  

1. Serial Transmissions

All serial transmissions to or from the TSCC are in the form of frames that contain 16 or 24 bits of data. PIOX transmissions consist of two to four frames, while PIOR transmissions consist of two to three frames. These frames are separated by a wait-state of no more than 400 nsec. Each frame has a two bit header (H1 and H2) and a two bit trailer (T1 and T2). T1 is always assigned to parity and T2 is always a 1. The parity bit maintains even parity for the whole frame.

* Reference Controls Hardware Release No. 8

Data are coded by the self-clocking Biphase Manchester convention. This code is characterized by a signal transition at the beginning of each cell boundary. A signal transition within a cell asserts true (1), while no transition conveys false (0).  

2. Port A PIOX Operations

The first frame in a PIOX transmission is always as follows:

H1
H2
15.......................08
07
06
05
04
03........00
T1
T2
0
0
CRATE ADDRESS
SCRA
SNRA
RCRB
RNRB
X
P
1

H2 being 0 indicates a 16 bit data frame.

The 8 bit Crate Address is compared against two internally selected values. The first value is distinct in the network and the second is an Aggregate Address that may be common to more than one crate in the network. For a particular TSCC, these addresses are set by DIP switches located on the Slot 24 module of the TSCC. The Aggregate Address capability may be eliminated by removal of IC 244.

The next four bits provide arbitration information:

SCRA: Reserve crate for Port A, CRA

SNRA: Reserve slot for Port A, NRA

RCRB: Remove Port B Crate Reserve, CRB

RNRB: Remove Port B Slot Reserve, NRB

The value of the last four bits of data is irrelevant .

The second frame of a PIOX transmission is always as follows:

H1
H2
15....................11
10
09.............06
05
04...................00
T1
T2

0
0
N16...N8...N4...N2...N1
1
A8...A4...A2...A1
1
F16...F8...F4...F2...F1
P
1

This is the NAF code, the use of which is guided by the following conventions:

N(0-23) Indicates a normal dataway cycle in the crate where:

F(0-7) indicates a read operation and use of the R lines

F(16-23) indicates a write operation and the use of the W lines

F(8-15) and F(24-31) function codes do not make use of the R or W lines.

N(24) Indicates an operation targeted to the crate controller where

N(24)A(0)F(0) Requests transmission of the LAM status in the response. L24 through L1 is returned.

N(24)A(0)F(4) Toggles an ON LINE/OFF LINE internal flip flop. Upon a power up condition, the crate is in the ON LINE state.

N(24)A(0)F(8) Causes the Inhibit line (I) to be set.

N(24)A(0)F(12) Causes the Inhibit line (I) to be reset.

N(24)A(15)F(16) Requests that the BTR function be set. Subsequent frames indicate the target NAF, Word Count, and Maximum No Q allowed.

N(24)A(15)F(20) Requests that the BTR function be reset and terminated.

N(24)A(15)F(24) Causes a C·S2 cycle to be executed.

N(24)A(15)F(28) Causes a Z·S2 cycle to be executed. The Inhibit line is also set.

Aggregate commands targeted to the crate controller are not allowed by the TSCC hardware.

If the second frame indicates a dataway write operation, a third frame is transmitted as follows:

H1
H2
23.......................0
T1
T2

0
1
W24(MSB)  ---   W1
P
1

H2 being 1 indicates a 24 bit data frame.

If the second frame denotes a BTR function set up [N(24)A(15)F(16)], additional third and fourth frames are transmitted as follows:

H1
H2
15...............11 
10
09..........06
05
04..............00
T1
T2

0
0
N16  N8  N4  N2  N1 
0
A8  A4  A2  A1
0
F16  F8  F4  F2  F1
P
1

H1
H2
15.......................08
07.......................00
T1
T2

0
1
32,768 - BTR Word Count - 1
128  - BTR Maximum No Q - 1
P
1

The third frame contains the NAF code that is to be repeatedly cycled by the BTR function. N must range N(0-23) and F must range F(0-7). In the fourth frame, Word Count can range from zero to 65,535 with resultant word returns ranging from 1 to 65,536 respectively. Maximum No Q can range from 0 to 255.

3 Port B PIOX Operations

Port B PIOX operations are similar to those of Port A, though more restricted. The first frame in a Port B PIOX transmission is as follows:

H1
H2
15..............08
07
06
05 00
T1
T2

0
0
CRATE ADDRESS
SCRB
SNRB
X
P
1

The crate address is compared against only the distinct address of the controller. No comparison is made to the Aggregate Address.

The tvo arbitration bits are as follows:

SCRB: SET CRATE RESERVE FOR PORT B, CRB

SNRB: SET SLOT RESERVE FOR PORT B, NRB

Port B cannot remove either of Port A's reserves, CRA or NRA.

The second PIOX frame contains NAF data. Port B is limited to only one N(24) operation. This is N(24)A(0)F(0) which results in the return of LAM status. Port B has no access to the BTR control circuits.

The third PIOX frame for Port B, if appropriate, contains Write data 

4. TSCC Service Request Levels

Four separate and prioritized service request levels can be asserted within the TSCC.

SR Level 1: This level is raised in response to the coming on of dc power and causes a Z·S2 cycle to be executed.

SR Level 2: This level is raised in response to a properly addressed and coherent transmission on the Port A PIOX line.

SR Level 3: This level is raised by the internal BTR function.

SR Level 4: This final level is raised in response to a properly addressed and coherent transmission on the Port B PIOX line.

The Z·S2 cycle of SRI occurs approximately two seconds after application of power. This cycle does not generate a response on any of the response lines; Port A PIOR, Port B PIOR, or BTR. The servicing of SR3 results in a response on the BTR line for Block Transfer dataway operations that return Q.

Assertion of SR2 triggers a Port A PIOR response unless the crate is OFF LINE or if the transmitted Crate Address is an Aggregate Address. Assertion of SR4 always triggers a Port B PIOR response, even if the crate is OFF LINE to Port A.

The raising of a service request level normally results in a CAMAC dataway cycle. A cycle may be inhibited, however, by arbitration conflicts or by detected protocol errors. Except for C and Z cycles, N(24) operations do not involve use of the CAMAC dataway. Port A dataway cycles are not allowed if the crate is OFF LINE.

5. Port A PIOR Responses

The first two frames of the Port A PIOR response are always as follows

H1
H2
23...............16
15...........8
07..........00
T1
T2

0
1
ECHO CRATE ADDRESS
STATUS BYTE 1
STATUS BYTE 2
P
1

H1
H2
23.......16
15...............11 
10
09..........06
05
04...............00
T1
T2


0
1
STATUS BYTE
N16  N8  N4  N2  N1 
1
A8  A4  A2  A1
1
F16  F8  F4  F2  F1
P
1

The Crate Address and NAF data are considered as echo data. The Crate Address is generated from the T SCC address selector switch whereas NAF is directly reflected from the second PIOX transmission. Status Byte data are as follows:

STATUS BYTE 1

MSB
    
    
  
  
  
  
LSB

Q
X
I
BP/AIP
CRLAM
CRA
NRA
CRB

Q - Q indicates that a target module returned Q during a dataway cycle.

X - X indicates that a target module returned X during a dataway cycle.

I - I indicates the state of the Inhibit line.

BP/AIP - This indicates the state of the Beam Permit/ Abort in Progress status line from the CAMAC dataway.

CRLAM - This indicates if any LAM is raised in the crate.

CRA - Indicates that Port A has the crate reserved.

NRA - Indicates that Port A has a slot reserved.

CRB - Indicates that Port B has the crate reserved.

STATUS BYTE 2

MSB
    
    
  
  
  
  
LSB


NRB
CRBT
NRBT
BTA
PAN=PBN
PAXE
NAFOKPA
SR2P

NRB - Indicates that Port B has a slot reserved.

CRBT - Indicates that CRB was terminated by a Port A operation.

NRBT - Indicates that NRB was terminated by a Port A operation.

BTA - Indicates that the Block Transfer function is active.

PAN=PBN - Indicates that the slot currently addressed by Port A equals the last slot addressed by Port B.

PAXE - Indicates a detected protocol error on the Port a PIOX line for the second or subsequent frames.

NAFOKPA - Indicates that the second PIOX transmission was properly received with l's separating the NAF fields and a N that ranged between 0 and 24.

SR2P - Indicates that service request level 2 was - raised and permitted to cycle the dataway if appropriate. This line also indicates the acceptance of arbitration requests. 

STATUS BYTE 3

MSB
    
    
  
  
  
    
LSB


PARDF
PALDF
PAN=BTNA
NAFOKBT
N(24)Q
FAGR
C
Z

PARDF - This is the REad Data Flag for Port A and indicates that there will be a third response frame which will contain readf data or retransmitted write data.

PALDF - This is the LAM Data Flag for Port A and indicates that there will nen a a third frame response which will contain the status of LAMs for slots 1 thru 24. L22 and L23 are always false.

PAN=BTNA - This indicates that the slot addresses by Port A was the same slot being addressed by an active Block Transfer function.

NAFOKBT - This line indicates a properly received NAF frame for the Block Transfer operation in response to a N(24)A(15)F(16) operation. Reciept of a N that ranged from 0 to 23, a F that ranged from 0 to 7, and 0's seperating the NAF fields is implied.

N(24)Q - This indicates that a N(24) operation to the TSCC was executed. This line is largely irrelevant to the N(24)A(0)F(0) operation which always results in a return of LAM status.

FAGR - This is the only crate controller LAM and indicates a failed Aggragate Command. This line is reset only by a Port A read of LAM status

C - This indicates the state of the dataway Clear line during the last executed cycele. It is expected to be present onle during a Poiryt A induced C·S2 cycle

Z - This indicates the state of the dataway Initialize line during the last executed cycle. It is expected tobe present only during a Port A induced Z·S2 cycle.

The third frame of a Port A PIOR response, if present, is indicated by the assertion of PARDF or PALDF in Status Byte 3. It contains 24 bits of read data, echo write data, or LAM status.

H1
H2
23                       0
T1
T2



R24   -  READ DATA  -   R1



0
1
W24 - ECHO WRITE DATA - W1
P
1



L24  -  LAM STATUS   -  L1

6. Port B PIOR Responses

Port B responses are the same as those for Port A except for some differences in Status Bytes 2 and 3.

STATUS BYTE 2

MSB
    
    
  
  
  
    
LSB


NRB
CRBT
NRBT
BTA
PAN=PBN
PBXE
NAFOKPB
SR4P

PAN=PBN - Indicates that the slot currently addressed by Port B equals the last slot addressed by Port A

PBXE - Indicates a detected protocol error on the Port B PIOX line for the second or third frame

NAFOKPB - Indicates that the second PIOX transmission was properly received with l's separating the NAF fields and a N that ranged between 0 and 24.

SR4P - Indicates that service request leve; 4 was raised and permitted to cycle the dataway if appropriate. This line also indicates the acceptance of arbitration requests.

STATUS BYTE 3

MSB
    
    
  
  
  
    
LSB


PBRDF
PBLDF
PBN=BTNA
BTN16
BTN8
BTN4
BTN2
BTN1

PBRDF - This is the Read Data Flag for Port B and indicates that there will-be a third response frame which will contain read data or retransmitted write data.

PBLDF - This is the LAM Data Flag for Fort B and indicates that there will be a third response frame containing the status of LAMs for slots 1 thru 24.

PBN=BTNA - This indicates that the slot addressed by Port B was the same slot being accessed by an active Block Transfer function.

A properly addressed port will always generate a PIOR response unless the Port A PIOX operation is an OFF LINE or Aggregate command. Additionally, no response will be generated if a protocol error is detected in the first PIOX frame which contains the Crate Address. Responses are typically launched within 2 microseconds of the receipt of the PIOX transmission. This response time could be as long as 4 microseconds if service requests at the TSCC happen to collide.  

7. Arbitration

The TSCC provides two serial ports of access, aggregate commands on the Host port, and a Block Transfer facility. These intermixed yet distinct demands for the CAMAC dataway reasonably require levels of both hardware prioritization and programmed arbitration. The primary function of arbitration is to facilitate uninterrupted execution of sequential dataway cycles to one or several modules within a CAMAC crate.

Most of the hardware levels of arbitration center around the Block Transfer function. The TSCC's acceptance of the Block Transfer setup operation, N(24)A(15)F(16), effectively reserves the target slot for the duration of the Block move. Port A, Port B, and Port A Aggregate operations are automatically prevented from communicating with this slot. Attempting to do an Aggregate cycle on an active Block Transfer slot always fails and results in the raising of FAGR, which in turn generates a LAM from slot 24. Aggregate commands, other than to an active Block Transfer slot, are always accepted.

The programmed requests for crate or slot reserve are contained in the first frame of the PIOX transmission. These requests are in the form of SCRA and SNRA bits for Port A and SCRB and SNRB bits for Port B. The resultant reserve states within the TSCC are CRA, NRA, CRB, and NRB. Programmed control of these states to either the asserted or false condition requires an allowed dataway cycle and module Q. Port A and Port B can simultaneously have NRA and NRB asserted for different arget slots. CRA cannot coexist with either CRB or NRB. Similarly, CRB cannot coexist with either CRA or NRA.

Reserve levels are normally set with the first operation of a multicycle sequence and normally removed with the last operation. The desired level of reserve must be reinforced with all intervening cycles. Separate crate cycles outside of the desired sequence are not necessary to set or reset the reserve states.

Port A has the capability of terminating a reserve established by Port B, CRB or NRB, via the RCRB or RNRB bits in the first PIOX frame. The capability of Port A to terminate these reserves is primarily dependent on Port A receiving a cycle permit, SR2P, while not dependent on module Q or target slot address.

If a Port B level of reserve is terminated, flags CRBT and/or NRBT are set. The first subsequent operation by Port B is not allowed if either CRBT or NRBT is set. These flags are reset after the response to this nno Opn operation is generated.

Port B cannot reset Port A reserve states, CRA or NRA. There is, however, a timeout aspect to CRA and NRA which will allow Port B access after approximately 1/2 second. This permitting ~evel to CRA and NRA is identified as PARG, Port A Reserve Gate.  

7.1 Port A Arbitration

The following summarizes the conditions under which Port A is allowed to execute its desired task, be it a dataway cycle or an operation to the controller. An allowed execution, SR2P, implies that a request for crate or slot reserve can be accepted and set if the target module returns Q. Port A is allowed to execute if the following conditions 1,2 & 3 or 1,2 & 4 are satisfied.

1. The crate is ON LINE, PAN/BTNA, PAXE is not set, and NAFOKPA is set.

2. CRB is not set, or if CRB is set and a valid CRB reset condition for CRB is present. A valid reset condition consists of RCRB or PAAGR being set.

3. NRB is not set, or if NRB is set and a valid NRB reset condition for NRB exists. A valid reset condition consists of a) RNRB being set or b) if a successful set of CRA is pending or c) if PAN=PBN and PAAGR is set.

4. PAN!=PBN and if either PBN=BTN is not set or if NAFOKBT is not set.

7.2 Port B Arbitration

The following summarizes the conditions under which Port B is allowed to execute desired dataway cycles. An allowed execution, SR4P, implies that a request for crate or slot reserve can be accepted and set if the target module returns Q. -

Port B is allowed to execute if all the following conditions are

1. Both CRBT and NRBT are not set.

2. NAFOKPB is set.

3. PBXE is not set.

4. CRA is not set.

5. PBN!=BTNA.

6. NRA is not set or if PAN!=PBN

7. SCRB is not set or if CRA, NRA, and BTA are all not set.

Reserves cannot be programmed by N(24) operations since dataway Q is not generated. Port A can, however, reset CRB or NRB with a N(24) operation. SR4P is irrelevant to the Port B request for LAM status, N(24)A(0)F(0), since LAM status is always returned for this operation. The status responses for both Port A and Port B contain adequate information to fully explain the actual handling of any desired request to the crate.  

8. Block Transfer

The Block Transfer operation is directly initiated by the N(24)A(15)F(16) Port A PIOX command to the TSCC. It is usually appropriate to precede this controller command with programmed setup communications to the target module/subsystem so that it may ready the desired data. Port A slot reserve (NRA) should normally be used during the target module setup. NRA is automatically cleared by the TSCC at the start of a Block Transfer operation.

Once the Block Transfer task is initiated, the separate serial response line (BTR) becomes active. The first and last frame of a Block Transfer response is always as follows.

H1
H2
23........16
15...13
12



08
07..04
03
02
01
00
T1
T2


1
0
CRATE ADDRESS
0
BTN16
BTN8
BTN4
BTN2
BTN1
0
BTA
BTTWC
BTTNQ
BTTTO
P
1

The five bit BTN field indicates the target slot of the Block Transfer operation.

BTA - Indicates that the Block Transfer function is active.

BTTWC - Indicates that the Block Transfer function was terminated by decrement of the desired word count to zero.

BTTNQ - Indicates that the Block Transfer function was terminated by decrement of the preset maximum no Q count to zero.

BTTTO - Indicates that the Block Transfer function was terminated by the TSCC because a Time Out occurred. The internal Time Out value is approximately 1/2 second.

These last four bits of status are mutually exclusive. If none is present, it is implied that the BT function was programmed off by the N(24)A(15)F(20) Port A operation. Intervening frames on the BTR line contain the read data from successful dataway operations to the target module. They are structured as follows:

H1
H2
23                  00
T1
T2


1
1
R24  -  BT DATA  -  R1
P
1

The maximum transfer rate accommodated by Block Transfer is 750 kbyte/sec. This corresponds to a CAMAC dataway cycle every 4 microseconds. Maximum block length for BT is 65K CAMAC words. Port A and B may freely communicate with crate modules other than the BT target module throughout a Block Transfer operation.  

9. Miscellaneous Features

Power Up Conditions: Powering up the CAMAC crate + 6 volts causes a one to two second clear to the TSCC circuits and a subsequent Z.S2 cycle. Additionally, the Inhibit line is set, the crate is put in the ON LINE mode and CRBT and NRBT are set. A recessed pushbutton is also provided at the front of the TSCC's slot 24 module for manual clears.

3P/AIP Line: The P1 patch line of the CAMAC dataway is driven by the BP/AIP status of the ABORT System. The input to the associated line driver is available at the TSCC I/O connector. An output of this line is also available for daisy-chaining to other local crates.

A/B Line: The P2 patch line of the CAMAC dataway is driven low during Port B dataway cycles.

ON LINE/OFF LINE Operations: Any given CAMAC crate can be toggled ON or OFF line by the Port A N(24) A(0) F(4) command. When a TSCC is put OFF LINE, no PIOR response is generated and the various levels of reserve rematn intact, though subject to timeout. Block Transfer, if active is allowed to continue to completion. Port B operations will be allowed if CRA is not set.

Voltage Requirements: Each TSCC module requires +6 volts. Power is fused at each module. A LED is provided at each module to indicate presence of power. The Slot 22 module of the TSCC also requires -6 volts. This power is also fused and has an internal LED monitor.

Physical Implementation: The TSCC is realized as a four board module set meant to occupy Slots 22 through 25 of a standard CAMAC crate. Due to mass terminated inter-board connections behind the front panels, the TSCC modules should be inserted and extracted as a set.

Front Panels: A facsimile of the TSCC front panels is attached as Appendix A. The labels on these panels are, for the most part, self explanatory. CRL indicates presence of any LAM assertion in the crate. PAIA and PBIA indicate PIOX input activity at Port A or Port B respectively. ONL indicates that the crate is ON LINE. BTA indicates that the Block Transfer function is active.

I/O and Monitor Connections: PIOX and PIOR connections for Ports A and B, BTR, and BP/AIP driver in and out are provided at the Slot 22 /O area. Connection is by means of a 36 pos Viking connector. A buffered BTR signal is provided at the front of the Slot 22 module. Undecoded dynamic N lines are available at the rear of the Slot 25 module. A listing of these connections is attached as Appendix B.

Appendix A

I/O and Monitor Connections

Slot 22 Module

18 position/36 contact card edge connector

Slot 25 Module

10 Contact Header 3M 3446-1202

Appendix B

TSCC II PALS

• TSCC15A.DAT
• TSCC18A.DAT
• TSCC21A.DAT
• TSCC27A.DAT
• TSCC40A.DAT
• TSCC41A.DAT
• TSCC44A.DAT
• TSCC46A.DAT
• TSCC47A.DAT
• TSCC50A.DAT
• TSCC51A.DAT
• TSCC64A.DAT
• TSCCHDR1.DAT
• TSCCHDR2.DAT