...PRELIMINARY DRAFT...
RD/Controls Hardware Release 27.0
RD/CONTROLS MULTIPLEXED ADC SYSTEM ( RD-MADC )
A. M. Forni, W. R. Knopf
I. INTRODUCTION:
The Multiplexed Analog to Digital Converter (MADC) was designed and fabricated at FERMILAB by the RD/Controls group to replace the existing XEROX 13 bit MADC systems. The XEROX MADC system has 64 analog channels multiplexed into one 13-bit Analog to Digital Converter. The architecture (ie. electrical and mechanical components) of the XEROX MADC system is outdated and replacement parts are difficult to get or nonexistent.
II. GENERAL DESIGN GOALS:
Develop a 64 channel analog-to-digital conversion system with 14 bit resolution. This conversion system should be flexible and allow for the capability of using 12, 14 or 16 bit A/D converters at various conversion speeds as system needs are redefined; it should also be modular enough to allow for upgrading of individual components without the need for a total system replacement. Analog inputs should have a high common mode rejection voltage, orders of magnitude greater then the analog supply voltage. The analog inputs should allow for ease of connection into the system, being flexible as to the number of input devices that will be monitored. Interface to the control system was to be in the same manner as was the XEROX system (ie. Camac parallel interface module) to allow for transparent integration into the control system.
III. DESIGN OVERVIEW:
To meet the design goals and keep the cost per input channel low the 64 channels are distributed over 8 cards, each containing an 8 input multiplexed analog-digital converter (MADC); thus conversion can occur in parallel and no analog voltages have to be routed between cards over the backplane. The MADC card is selected and read by the local bus controller card (LBC). The LBCs function is to provide an interface between a Camac parallel module and the MADC cards. The LBC card also displays the data returned from a convert cycle by way of a 2's complement LED bar display on the front panel; the channel is selected via a front panel thumbwheel switch. Conversion of the selected MADC channel can be initiated locally via a front panel pushbutton. All analog inputs as well as digital interface signals are connected to the system via the backplane connectors.
The crate selected was a Euro crate (3U size) with a commercial General Purpose microprocessor bussed backplane (GP bus), since this unit is already in use for the Link Repeater system, Phase-to-Tevatron clock converter module and Arcnet Bridge system. This also allows for future implementation as a node in an Arcnet networked system to support block transfer and stand-alone mode.
The analog signals are routed to the MADC system through a distribution panel. It consists of 16 twin-X printed circuit board connectors mounted on a 1.75" by 19" panel. The analog signal is then connected to the crate through a 16 conductor ribbon cable. This cable has alternating shield, + signal and -signal per input channel.
IV. SPECIFIC HARDWARE DESIGN:
MADC A/D module (RD MADC 8A ). Drawing # 0880 EC 172838
This MADC card contains:
o (8) precision unity-gain differential buffer amplifiers,
o (1) analog 8-to-1 multiplexer,
o (1) scaling/integrating amplifier,
o (1) 14-bit ADC,
o (4) data and address latches,
o and glue logic.
Crystal Semiconductor part CS-5014 was chosen for the A/D converter. It is one of a family of converters with resolution at 12, 14, and 16 bits. Digital conversion time is fixed with an external 4.0 Mhz clock to 14.25 uS. The throughput rate is set to 21 KHz; this allows the scaling amplifier to integrate some of the inherent noise from the devices being monitored, resulting in a slew rate of 10 V/16 uS. On power up the A/D will perform a self calibration technique that insures accuracy over time and temperature.
Crystal Semiconductor A/D's have a full scale input voltage of only +/- 5.0 volts. This voltage is below the design specification of +/- 10.0 volts. To achieve the design specification a scaling amplifier was used. A precision amplifier from Harris Semiconductor part HA7-5127A-5 was chosen. This op-amp has a gain bandwidth of 8.5 Mhz, offset voltage of 10 uV, slew rate of 10 V/uS. and settling time of 1.5 uS.
A buffer amplifier (Burr-Brown INA-117P) isolates the A/D input from the hostile environment of the devices being monitored. This precision unity-gain differential amplifier has an unusually high common-mode voltage of +/- 200 VDC or + AC peak continuous operation. The differential input impedance is typically 800 K-ohms, nonlinearity 0.001% maximum, unity gain of 0.02% maximum and gain bandwidth of 200 Khz @ 3 db.
The Analog Devices AD586LQ provides the external precision voltage reference required by the A/D. It has an initial error of 2.5 mV. with a temperature coefficient of 5 ppm/'C over a temperature range of 0' to + 70' C.
The A/D module uses one PLD (Lattice GAL-6001) to control all on-board functions (ie card select, channel latch and convert delay). It also has two data and two address buffer/latches. This module is capable of digitizing a +/ 10.0 volt full scale value and converting it into a 14 bit binary 2's complement value. The binary data generated by the A/D is a left justified 16 bit word with unused data bits internally set to low (zero) by the A/D converter. The module starts a conversion on the requested channel and returns the data from the previous conversion (data from latches) every time a request is received by the module.
MADC Local Bus Controller (RD MADC_LBC ). Drawing # 0880 EC 172838
To match the signal interfacing to the control system in the same manner as does the Xerox system a local bus controller was required. This controller has bi-directional data bus drivers, a data monitoring LED display, a manual channel selector (ranging from 0 to 63), manual convert button and glue logic to control it all. This module busses a 6-bit address received from the Camac parallel interface module and initiates the proper control lines to start a convert cycle. The data returned during this convert cycle is passed to the Camac parallel interface module. The data can also be locally displayed if the manual channel selector readout matches the 6-bit address from the Camac parallel interface module. This display is in the form of a LED bar graph with sign bit (msb) arranged as the top bit. To initiate a local convert cycle the channel selector is set to the desired channel number and the manual convert button is pushed twice. This sends two convert commands to the A/D module corresponding to the channel number. The LED bar graph display latches the results from this manual convert cycle.
MADC Bus to Bridge Processor Interface Module (RD MADC BUS).
Drawing # 0880-EC-172902
This module and it's companion module the MADC Buffer memory to CAMAC Interface module were designed to replace the local bus controller module. They are used in conjunction with the bridge processor and it's associated companion modules, the Arcnet interface and buffer memory module.
The MADC bus to bridge processor interface module gives the bridge processor the capability of directly reading from and writing to devices over the A/D data bus such as A/D channels, Dual-Ported RAM and in general, any other device located on the GP bus.
This module has a 16-bit data bus and an 8-bit address latch. It also has one GAL 6001 for glue logic, bus drivers for processor and MADC control lines.
MADC Ram to Camac Interface Module (RD MADC RAM).
Drawing # 0880-EC-172903
This module provides a dual-ported RAM buffer between the parallel control system interface and a crate resident processor. This allows the collection of MADC data by a processor being passed via the RAM to the control system. The benefits of this arangement are that only one Camac cycle is required to access any MADC channel, also the presence of a processor allows for data preprocessing such as averaging or scaling. At present this data is refreshed at a 1KHz rate. This module has a 1k by 16-bit wide Dual-Ported RAM (also only 64 words are presently used); the glue logic is a GAL 22V10 for controlling processor waits and read/write to the RAM.
This module requires the presence of the bridge processor and it's companion module, the MADC bus to bridge processor Interface module.
MADC CYCLE ( Read data over CAMAC )
In order to read a MADC channel over the parallel Camac system two Camac dataway read cycles must be performed, the first one to latch the channel address and start a convert, the second one to read the data from the first convert. See table 1 for proper function codes and subaddress.
MADC Averaging History
Early installations showed the noise, generated by power supplies, in analog readbacks. This was due to the faster conversion time and higher resolution of the new A/D's. In order to give the users a more stable readback the averaging feature was added. In this mode the processor in the A/D crate keeps a local pool of all 64 channels, calculates the arithmetic average over the last eight conversion cycles for each individual channel, and makes the data accessible via the dual-ported buffer. This eliminates the need for excessive RC filtering as was used with the Xerox systems and also reduces the number of read cycles by the control system from two to one.
V. CAMAC PARALLEL INTERFACE MODULE ADDRESSES (007):
The Camac interface module generates addresses for 64 A/D channels by using function codes (ie. F and A codes). This table shows the correlation between function codes and sub-addresses and the generated channel addresses.
Function code Address code Binary value A/D S1 Values
F0 A0 h00 ON ON ON ON
. . . .
F0 A7 h07 ON ON ON ON
F0 A8 h08 OFF ON ON ON
. . . .
F0 A15 h0F OFF ON ON ON
F1 A0 h10 ON OFF ON ON
. . . .
F1 A7 h17 ON OFF ON ON
F1 A8 h18 OFF OFF ON ON
. . . .
F1 A15 h1F OFF OFF ON ON
F2 A0 h20 ON ON OFF ON
. . . .
F2 A7 h27 ON ON OFF ON
F2 A8 h28 OFF ON OFF ON
. . . .
F2 A15 h2F OFF ON OFF ON
F3 A0 h30 ON OFF OFF ON
. . . .
F3 A7 h37 ON OFF OFF ON
F3 A8 h38 OFF OFF OFF ON
. . . .
F3 A15 h3F OFF OFF OFF ON
Table 1
8 CHANNEL MULTIPLEXED ADC UNIT
EURO CHASSIS BACKPLANE PINOUT
DATE :: 3/8/91
CONNECTOR GENERAL PURPOSE BACKPLANE
PIN ROWa ROWb ROWc
NUMBER SIGNAL SIGNAL SIGNAL
1 DGND SHIELD GND AGND
2 D0 CHANNEL 1+ D1
3 D2 CHANNEL 1 D3
4 D4 SHIELD GND D5
5 D6 CHANNEL 2+ D7
6 D8 CHANNEL 2 D9
7 D10 SHIELD GND D11
8 D12 CHANNEL 3+ D13
9 D14 CHANNEL 3 D15
10 A0 SHIELD GND A1
11 A2 CHANNEL 4+ A3
12 A4 CHANNEL 4 A5
13 A6 UNDEFINED A7
14 /RDY UNDEFINED /POC
15 POC UNDEFINED /CRSEL
16 /DSB UNDEFINED /BHE
17 /BLE SHIELD GND R/WB
18 /RAM_EN CHANNEL 5+ UNDEFINED
19 UNDEFINED CHANNEL 5 UNDEFINED
20 /INWAIT SHIELD GND UNDEFINED
21 UNDEFINED CHANNEL 6+ UNDEFINED
22 UNDEFINED CHANNEL 6 UNDEFINED
23 UNDEFINED SHIELD GND UNDEFINED
24 UNDEFINED CHANNEL 7+ UNDEFINED
25 UNDEFINED CHANNEL 7 UNDEFINED
26 UNDEFINED SHIELD GND UNDEFINED
27 UNDEFINED CHANNEL 8+ UNDEFINED
28 5V CHANNEL 8 UNDEFINED
29 BUSCLK UNDEFINED UNDEFINED
30 UNDEFINED UNDEFINED UNDEFINED
31 15V UNDEFINED +15V
32 +5V +5V +5V
MADC LOCAL BUS CONTROLLER
EURO CHASSIS BACKPLANE PINOUT
DATE : 3/8/91
CONNECTOR GENERAL PURPOSE BACKPLANE
PIN ROWa ROWb ROWc
NUMBER SIGNAL SIGNAL SIGNAL
1 DGND GND AGND
2 D0 BIT0 D1
3 D2 BIT1 D3
4 D4 BIT2 D5
5 D6 BIT3 D7
6 D8 BIT4 D9
7 D10 BIT5 D11
8 D12 BIT6 D13
9 D14 BIT7 D15
10 A0 BIT8 A1
11 A2 BIT9 A3
12 A4 BIT10 A5
13 A6 BIT11 A7
14 /RDY BIT12 /POC
15 POC BIT13 /CRSEL
16 /DSB BIT14 /BHE
17 /BLE BIT15 R/WB
18 /RAM_EN A0 UNDEFINED
19 UNDEFINED A1 UNDEFINED
20 /INWAIT A2 UNDEFINED
21 UNDEFINED A3 UNDEFINED
22 UNDEFINED A4 UNDEFINED
23 UNDEFINED A5 UNDEFINED
24 UNDEFINED /LBCSEL UNDEFINED
25 UNDEFINED DSI UNDEFINED
26 UNDEFINED LBC R/W UNDEFINED
27 UNDEFINED /INTEXT UNDEFINED
28 5V DEFINED UNDEFINED
29 BUSCLK DEFINED UNDEFINED
30 UNDEFINED DEFINED UNDEFINED
31 15V DEFINED +15V
32 +5V +5V +5V
MADC CONTROLLER CARD TO C 007
CABLE INTERFACE
DATE :: 3/8/91
EURO CRATE INTERCONNECT CAMAC I/O
PIN ROWb Cable VIKING C 007
NUMBER SIGNAL COLOR CODE CONNECTOR NAMES
1 GND CABLE #1 BLACK A 1 GND
2 D0 BLK/RED A 2 1
3 D1 BLK/WHITE B 2 2
4 D2 RED A 3 3
5 D3 RED/BLK B 3 4
6 D4 RED/GRN A 4 5
7 D5 RED/WHITE B 4 6
8 D6 ORG A 5 7
9 D7 ORG/BLK B 5 8
10 D8 ORG/RED A 6 9
11 D9 GRN B 6 10
12 D10 GRN/BLK A 7 11
13 D11 GRN/WHITE B 7 12
14 D12 BLUE A 8 13
15 D13 BLU/BLK B 8 14
16 D14 BLU/RED A 9 15
17 D15 CABLE #2 BLACK B 9 16
18 A1 BLK/RED A 15 A1
19 A2 BLK/WHITE A 14 A2
20 A4 RED A 13 A4
21 A8 RED/BLK A 12 A8
22 A16 RED/GRN A 11 A1
23 A32 RED/WHITE A 10 A3
24 /LBCSEL ORG B 15 /ACKNOWLEDGE
25 DSI ORG/BLK B 10 DIGITIZE
26 LBC R/W ORG/RED B 12 TEST STATUS
27 /INTEXT GRN B 11 /LAM
28 UNDEFINED GRN/BLK N/C
29 UNDEFINED GRN/WHITE N/C
30 UNDEFINED BLUE N/C
31 UNDEFINED BLU/BLK N/C
32 +5 N/C N/C
Rev. 1.1
Added three new signals to the connector definition. This change will allow the C 007 card to work with both Xreox and RD MADC systems.
signal LBCSEL was added to pin B 24
signal DIGITIZE was moved to pin B 25
signal LBC R/W was added to pin B 26 for future use.
signal /INTEXT was added to pin B 27 for future use.
VI. CALIBRATION PROCEDURE:
To calibrate A/D modules you will need some equipment; please refer to the list below for more details.
1.) Camac crate.
2.) Crate controller C-1000.
3.) C-1150 used as the D/A standard.
4.) C-007 used as the camac parallel interface module.
5.) Precision voltage calibrator (ie. Fluke 343A).
6.) MADC system crate and power supply.
7.) MADC local bus controller module.
8.) Interconnect cable from MADC crate slot 17 to camac C-007 slot 19.
9.) MADC analog input distribution panel.
10.) Ribbon interconnect cable from MADC crate to distribution panel.
11.) C-1150 output cable type Twinx-BNC cable with viking connector.
12.) Extender, general purpose bus type.
13.) IBM compatible Personal computer with PC I/O card design by RD/Controls.
14.) Calibration software MADCDIAG.EXE file.
15.) 4 1/2 digit True RMS multimeter DVM (ie. Fluke 8060A)
Assembly Instructions
1.) Install ribbon cables item #10 from backplane of MADC system crate to Analog input distribution panel item #9. This cable is typically connected on even numbered slots starting with slot #2 at backplane. see figure 2 for more detail.
2.) Install parallel interconnect cable from MADC crate slot 17 to camac C-007 slot 19.
3.) Install MADC Local Bus Controller item #7 in slot #17.
4.) Install ribbon cable from PC I/O card to camac crate controller item #2.
5.) Install D.U.T. in slot #2 with extender item #12. Then turn power on to crate and allow to stabilize for approximately 1 minutes.
6.) Install camac modules into crate and turn power on. Allow modules to stabilize for 15-30 minutes.
Calibrating procedure for D.U.T. (A/D card)
1.) Use DVM to adjust reference voltage to 5.00 volts +/- .0005.
2.) Adjust dip switch S1 to proper card address for test. See table 1.
3.) Remove D.U.T. from extender and install it into same slot.
4.) Execute MADCDIAG.EXE software program.
5.) Default settings for software are set for card 0 channel 0.
Main Menu Pop Up and Pull Down Options Variable Name Default Settings
Select Plot/Scan Parameters Number of Samples Y axis Minimum mV.Y axis Maximum mV.AutoScaleMilliseconds per read 10000-10000+10000OFF1
Select A/D Type (F10 key to cycle) RD-MADC, XEROX RD-MADC
Assign Crate & Slot Numbers Camac A/D Interface slot Camac A/D Read Function Camac A/D read Subaddress A/D Channel Number Camac Crate D/A Slot Camac D/A Write Function Camac Write Subaddress Camac D/A Write Data (Hex) Camac D/A Read Function Camac D/A Read Subaddress Camac Crate Controller Number 19000516040000016
Units Scaling Raw, Millivolts, Engineering MilliVolts
6.) Perform OFFSET ADJUSTMENT on A/D scaling amplifier. Adjust R10 until plot on your PC is flat horizontally as possible. This should be a indication of lowest offset on amplifier.
7.) Perform GAIN ADJUSTMENT on A/D scaling amplifier. Adjust R11 until plot on your PC is flat horizontally as possible. This should be a indication of consistent gain across the amplifier.
8.) Perform MULTIPLEXER TEST. You will need to put a voltage into each channel. The voltages are +5, +3.75, +2.25, +1.25, -1.25, -2.25, -3.75, -5 starting with channel 0 going to channel 7.
9.) Tag A/D card with Date and your initials.