Epicure Hardware Design Note 101.1
Specifications C1032 SWIC Scanner Interface
M. Larwill, R. Flood, T. Kiper
January 7, 1991
Revised November 21, 1995 T. Kiper
1. Introduction
The C1032 is a single-width CAMAC module which is used as an interface between the control system, one SWIC Scanner, and its associated motor drive. It contains a 16-bit Z8002 microprocessor, 32k of RAM, 32K of EPROM, a Z8036 CIO, a 2681J DUART, a Tev clock event-decoder, an 032-style block-transfer circuit, two relays and optically-coupled inputs, and an ARCnet LAN interface. The above features allow the module to replace the 032/036, 091/096, and 014/154 modules required for typical SWIC Scanner support. In addition, a 2.5 Mbit ARCnet LAN is provided for high-speed transfers of Scanner data.
The C1032 is an updated application of the C1045 Motion Controller module. When developing the C1045, hardware considerations were made to allow for future support of SWIC Scanners. The module's I/O connector is pin-for-pin compatible with the 032. With the ability to decode Tev events, and two open-collector outputs (defined as START and CLEAR), timing for a Scanner can be generated on-board. Application-specific parameters can be downloaded to the module through CAMAC or ARCnet. Attempts have been made to emulate the 032 F-codes without compromising the performance capabilities built into the module. CAMAC 032 pseudo-emulation and unique F-codes are described later in this document.
The C1032 maintains a local data pool of SWIC Scanner information which allows it to respond to requests from CAMAC within 20 usec of a request. The data pool is updated as the data becomes available from the scanner. Data is unavailable from T5 until the updateing is complete.
1.1 Memory Map for the C1032
MEMMAP
Memory map for the C1032 implementation:
31 ____________________________0
0000 - | |
| Code Segment in |
| EPROM |
7FFF - | |
-------------------------------
8000 - | Un-Initialized RAM |
| ALL EVEN BYTES = NVRAM |
-------------------------------
8100 - | PSAREA |
8600 | RAM - Variable storage |
DFFF- | TOP of User Ram |
-------------------------------
E000- | Copy of ARCnet Buffers |
E7FF | (Page 1-4) |
-------------------------------
F2FE - | System Stack ^ |
-------------------------------
F300-FF | rd tclk fifo |
-------------------------------
F400 - | r/w tclk mask |
F5FF - | 256 bytes (word boundary) |
-------------------------------
F600 - | |
| Zilog 8036 CIO |
F67F - | |
-------------------------------
F680 - | |
| 2681 DUART |
F6BF | |
-------------------------------
F6C0-CF | R/W CAMAC low word |
-------------------------------
F6D0-DF | R/W CAMAC high byte |
-------------------------------
F6E1-EF | R/W block transfer(ODD) |
-------------------------------
F700 - | ARCNET COM |
-------------------------------
F780-FF | ARCnet LED Node Latch |
-------------------------------
2. Serial Link Interface
The 1-Mbit serial link is composed of two 64 deep, 8-bit FIFO's and two 50C32 EPLD's clocked at 20 MHz. The serial transmission packet is composed of a start bit, the low data byte, and the high data byte. Since the FIFO's are byte-wide, two read/write cycles are needed to move the 16-bit data to/from the serial link. Once a byte of data is available at the output of the TX FIFO, the transmit EPLD outputs a start bit and begins transmission. This means that both bytes of a word must be successively written to the TX FIFO without interruption. The TX circuit will not output data unless the TREQ input is asserted. When the RX FIFO becomes full, the RRDY line is de-asserted, stopping any further reception of serial data. Transmit and receive status lines are available for vectored interrupts (only receive interrupts presently supported).
3. RS 232 Interface
The Signetics 2681 Dual Asynchronous Transceiver (DUART) is configured by firmware for 8 data bits, 1 stop bit, no parity, 9600 baud, no CTS/RTS handshaking. The DUART generates a non-vectored interrupt when RX data is available. Since only the RS-232 transmit and receive signals are present, the X_ON/X_OFF protocol is supported in software. RS-232 signals are buffered with a MAX233 interface chip. Channel 1 is available at a front panel 4-pin LEMO connector. Both channels of RS 232 are present at the rear Viking connector. Both channel signals TBE (transmit buffer empty) and DAV (data available) are capable of generating vectored-interrupts (though currently not supported).
Output lines OP3-OP0 are used for status and control of the following information. OP2 and OP3 respectively provide software-generated IN/OUT status of the SWIC motor position. OP0 and OP1 are NOT direct status of the START/CLEAR outputs. The following table shows the allocated address space for the 2681 registers:
DUART Address Allocation Table
Address Function
f681 Port A Mode registers (MR1A,MR2A)
f683 Port A Status register (read Clock Select Register)
f685 Port A command register (write)
f687 Port A RX/TX holding registers
f689 Aux control register (write)
Input Port Change register (read)
f68b Interrupt mask register
f68d Counter/Timer Upper register
f68f Counter/Timer Lower register
f691 Port B mode registers (MR1B,MR2B)
f693 Port B status (SRB)/clock select registers (CSRB)
f695 Port B command register
f697 Port B Rx/Tx holding registers
f699 reserved - duart + 24
f69b Output Port Config. register
f69d Set Output Port Bits command (write)
Start Counter Command (read)
f69f Reset Output Port Bits command (write)
Stop Counter Command (read)
3.1 DUART Port Bit Functions
BIT # NAME & FUNCTION
bit 7 - not used
bit 6 - not used
bit 5 - Clear Pulse ~ 3usec (drives 3 50ohm loads)
bit 4 - Start pulse ~ 3usec (drives 3 50ohm loads)
bit 3 - MOTOUT L = front panel LED on - SWIC pos. OUT
bit 2 - MOTIN L = front panel LED on - SWIC pos. IN
bit 1 - CLEAR L=front panel LED on - clear output (~10 msec)
bit 0 - START L=front panel LED on - start output (~10 msec)
4. Z8036 CIO Counter/Timer
The Z8036 is a multi-function chip which provides system counters, status and vectored-interrupt handling. It has a total of 20 I/O lines available for control and status monitoring. These signal lines are described in more detail below. The PCLOCK input is a 5 MHz square wave. The Z8036 is initialized to the following settings upon reset and power on. CT1 is set up in a 1 KHz repetitive one-shot mode with interrupt vector #6H. CT1 triggers CT2, which then divides by 100 to get a 10 Hz interrupt rate on vector #2H. CT3 is available for use by applications programs. The following tables show the address space allocated to the Z8036 CIO Counter/Timer and PIO Unit.
Z8036 Main Control Registers for the CIO
Address Function
f601 Master Interrupt Control Register
f603 Master Configuration Register
f605 Interrupt Vector, Port A
f607 Interrupt Vector, Port B
f609 Interrupt Vector, Cnts/Timers
f60b Data Path Polarity, Port C
f60d Data Direction, Port
f60f Special I/O Control, Port C
Z8036 Command, Status and Data Registers
Address Function
f611 Command/Status, Port A
f613 Command/Status, Port B
f615 Command/status, Cnt/Timer 1
f617 Command/status, Cnt/Timer
f619 Command/status, Cnt/Timer 3
f61b Data Register, Port A
f61d Data Register, Port B
f61f Data Register, Port C
Z8036 Counter/Timer Registers
Address Function
f621 Current Count - MSB's for CT1
f623 Current Count - LSB's for CT1
f625 Current Count - MSB's for CT2
f627 Current Count - LSB's for CT2
f629 Current Count - MSB's for CT3
f62b Current Count - LSB's for CT3
f62d Time Constant - MSB's for CT1
f62f Time Constant - LSB's for CT1
f631 Time Constant - MSB's for CT2
f633 Time Constant - LSB's for CT2
f635 Time Constant - MSB's for CT3
f637 Time Constant - LSB's for CT3
f639 Mode Specification for CT1
f63b Mode Specification for CT2
f63d Mode Specification for CT3
f63f Current Vector Register
Z8036 Port A Specification Register
Address Function
f641 Mode Specification
f643 Handshake Specification
f645 Data Path Polarity
f647 Data Direction
f649 Special I/O Control
f64b Pattern Polarity
f64d Pattern Transition
f64f Pattern Mask
Z8036 Port B Specification Register
Address Function
f651 Mode Specification
f653 Handshake Specification
f655 Data Path Polarity
f657 Data Direction
f659 Special I/O Control
f65b Pattern Polarity
f65d Pattern Transition
f65f Pattern Mask
4.1 CIO Port Bit Functions
PORT BIT # NAME & FUNCTION
PORTC
bit 3 TXAF H = transmit fifo almost full or empty (input)
bit 2 TXHF H = transmit fifo half full (input)
bit 1 MODE32 H = 32 bit block transfer mode (output)
bit 0 /RCVRES L = reset fifos' (output)
PORTB
bit 7 RXAFE H = rcv fifo almost full or empty (input)
bit 6 RXHF H = rcv fifo half full (input)
bit 5 /TREQIN H = ok to xmit (input)
bit 4 CAMDIS H = camac irq.s disabled (output)
bit 3 /LAMREQ L = request a LAM (output)
bit 2 /LAMEN L = enable LAM's (output)
bit 1 TCLK L = led on - Tev events have occurred (output)
bit 0 HRTBT L = led on - module alive (output)
PORTA
bit 7 DMOTO H = turn on motor-out relay (output)
bit 6 DMOTI H = turn on motor-in relay (output)
bit 5 MSTATO L = SWIC-out status (input)
bit 4 MSTATI L = SWIC-in status (input)
bit 3 CLKINT H = tev clk IRQ (vec. 16H) (input)
bit 2 SERDAV H = rcv fifo IRQ (vec. 14H) (input)
bit 1 SERDY H = xmt fifo has data in it (status) (input)
bit 0 LANIRQ H = ARCnet IRQ (vec. 10H) (input)
5. TEV CLOCK DECODER
The Tev clock decoder circuit is capable of decoding any of 256 possible events. TCLK and TDATA are fed by P1 and P2 respectively from the CAMAC Dataway. A 256 x 1 bit (word boundary) RAM provides a decode-enable mask for each event. Writing a "1" to the desired event location enables that event. An EPM5032 EPLD detects and outputs a decoded event which forms an address for the RAM mask. If that particular address (event) contains a "1", an interrupt (16H) is generated, and the address (event) is loaded into a FIFO where it can be read out by the processor. A "read" of the FIFO clears the interrupt. Interrupts will be generated as long as the FIFO contains events.
6. TIMER INTERRUPTS
Timer CT3 is available for user applications. Timer CT1 interrupts every millisecond. The processor re-enables the interrupt and returns from the service routine. Timer CT2 is set to interrupt at a 100 Hz rate. The timer interrupt is used to perform several low-priority tasks:
1) increment the time of day clock
2) check for Tev events and update associated LED
3) output data from circular buffer to serial-link FIFO
4) do heart-beat LED
5) if either serial-link FIFO is full, set LAM
6) re-issue request for Scanner data if necessary
Any time the LAM source or mask register is changed through CAMAC, as well as every time the 100 Hz timer-interrupt occurs, LAM will be set or reset according to whether LAMEN is asserted and the contents of the source and mask registers.
7. CAMAC INTERFACE OPERATION
The CAMAC slave interface is implemented using a PROM for encoding the FNA code and generation of the "Q" response and a 50C32 EPLD providing sequencer control of the operation. The 50C32 outputs an encoded interrupt vector corresponding to the valid CAMAC operation that occurred. Invalid CAMAC operations are ignored, a "no Q" is returned to the Dataway, and no interrupt occurs.
CAMAC read functions always require at least two cycles before a "Q" is returned. This is because the processor cannot respond with the requested data in the 200 nsec required by the CAMAC Dataway protocol. An interrupt does not occur when "Q" is returned.
In the 032, when the F16 buffer is full, or the F0 buffer is empty, a "no Q" is returned for the respective operations. The 1032 differs from the 032 in that when all F0 data has been read out, a "Q" is still returned with data equal to zero. A "Q" is also returned for an F16 write even when the serial link TX buffer is full. Data is thrown away. When CAMAC requests Scanner data while the data pool is being updated, FF's are returned with "Q". Other quirks regarding CAMAC operations are discussed in the section on Scanner protocols.
The C1032 supports the full 24-bit Dataway. The lower 16 bits are on a word boundary (low byte = R/W 1-8, high byte = R/W 9-16). The topmost byte is also on a word boundary (low byte = don't care, high byte = R/W 17-24).
Current valid CAMAC operations are as follows:
CAMAC Functions ( see appendix C.1 )
7.1 CAMAC Timing Diagrams
This module conforms to the ANSI 583 1982 spec. for Dataway cycle timing as described in the standard and as shown in figures 9 and 10 on page 54.
8. C1032 to SWIC Scanner Protocol
The C1032 module communicates with the SWIC Scanner by sending it 16 bits at a time. Data to be sent to the Scanner is kept in a circular buffer which is loaded by CAMAC, ARCnet, or by the TCLKINT interrupt routine at event T6. The circular buffer is examined and emptied to the TX FIFO during the 10 Hz interrupt service routine. Should the buffer become full, a bit in the LAM status register will be set.
The module uses the existing Scanner command and setup codes. Setup data is stored in NV ram on the c1032 board. When data byte 07 is written over camac this signals the code to stored this and the following data as setup data for the scanner. Upon future reboots this data is then loaded to the scanner.
If datapool request for SWIC data is active the data will be returned when ready or worst case after T6 goes inactive. If invalid data is returned by the Scanner, all data is thrown away and a new request is made until T6 goes inactive.
There are only three types of Scanner data requests currently supported: group 1 (scans 1-5), group 2 (scans 6-10), and test pattern data. The module requests group 1 and group 2 types. These requests are prioritized by the 1032 in the order above. This is important to note, as there is no header information describing the Scanner data being returned. The test pattern is read after each reboot. Camac request for the test pattern data will force and update by setting a flag. This update will happen along with the normal data update after the next T5 interrupt.
9. SWIC Scanner to C1032 Protocol
The SWIC Scanner communicates with the C1032 module by sending it two bytes of data at a time. The block of data being sent out corresponds to whatever request was first made. The data block continues to be sent until all data is transmitted. When group 1 request is successful, then the request for group 2 begins. The first transmitted byte of a block of data is the total byte count for that block. The total block length is determined by the number of scans that the Scanner was set up to do. A group of 5 scans is 494 bytes long. If no scans were done in a group, only a header containing the Scanner name is returned. If the total bytes received is greater than the maximum byte count, all further received data is ignored, and a new request is sent to the Scanner.
Routine SERINT handles the serial link data input. Presently, no interrupt occur after each two bytes of data received. The status is polled at a 1ms rate and if data is available then this data is read (upto 250 bytes/polling).
Returned data from the serial link is stored in one of three 512-byte pages of ARCnet RAM and mirrored in system ram. Before being stored, the bytes in the data word are exchanged to conform to Intel byte-ordering. Presently no in-module analysis is done on the received data. This data is in the correct order for transmitting via ARCnet. This is later done later as a background task.
10. SWIC MOTOR DRIVE INTERFACE
The C1032 provides two relays, each with NO and NC contacts available for controlling a SWIC motor drive. This permits flexible interfacing to existing 154 or 014 type drive devices. Active-low isolated status inputs and common are provided for the "in" and "out" limit positions. These inputs are optically-coupled to the CIO. An on-board isolated VCC supply (40mA max.) provides active pull-up to the receiver LEDs. Motor "in" and "out" status LEDs are driven by the OP2 and OP3 lines of the 2681 DUART respectively, which is controlled by software.
11. BROADCAST DATA LINK (LAN)
This data link (ARCnet) is capable of supporting up to 255 nodes. The network supports a length limit of not less than one mile. Nodes are able to interconnect by way of a single coax cable running from node to node. ARCnet uses a token-based protocol and will employ a VME Bridge to connect the Intrahouse LAN to the Interhouse network.
The C1032 uses the a highly-integrated IC released by Standard Microsystems, the COM20020. Details of the ARCnet controller can be found in the COM20020 specifications, but a brief description follows. The ARCnet controller accesses an internal dual-ported 2Kx8 RAM organized as four 512-byte pages. A GAL20V8 provides signal translation between the COM chip and the processor for access to the RAM and COM registers, which are mapped as eight sequential registers beginning at location F701H. RAM is accessed by setting a pointer register to the desired address. An auto-increment feature allows sequential byte-wide accesses without the processor having to increment the pointer register.
The network connects to the C1032 via a ground-isolated front panel LEMO connector which must be adapted to RG-59 coax. Each ARCnet node must have its own unique address. The 8-bit ARCnet node address is software-selectable. When enabled, the COM20020 will generate interrupt LANIRQ* (vector 10H) to indicate the receipt of a message or the completion of a transmission. The COM chip passes and receives tokens transparently to the processor. When a token is received, the COM chip is allowed to transmit messages.
Re-configuration is also transparent to the processor. If the COM chip has undergone re-configuration, it will set a bit in the LAN status register (FC00H). The re-configuration and response times are software-selectable. An ARCnet hybrid contains the discrete cable-interface logic. The hybrid is transformer-coupled to the network and is protected from cable transients by an RC network.
11.1 COM Registers
11.1.1 The COM20020 LAN Status Register (F70XH odd addresses only)
REGISTER READ ONLY ADD
STATUS RI X X POR TEST RECON TMA TA F701
DIAG. STATUS MY-RECON DUPID RCV ACT TKN EXC NAK TENT-ID X X F703
ADDRESS PTR HI RDATA AUTO-INC X X X A10 A9 A8 F705
ADDRESS PTR LO A7 A6 A5 A4 A3 A2 A1 A0 F707
DATA D7 D6 D5 D4 D3 D2 D1 D0 F709
RSRV'D X X X X X X X X F70B
CONFIG RESET CCHEN TXEN ET1 ET2 BCK PLNE SUB-AD1 SUB-AD0 F70D
TENT-ID NODE-ID SETUP TID7 NID7X TID6 NID6X TID5 NID5X TID4NID4X TID3NID3X TID2NID2X TID1NID1X TID0NID0X F70F
11.1.2 The COM20020 LAN Control Register (F70XH)
REGISTER WRITE ONLY ADD
IRQ MASK RI 0 0 0 EXCNAK RECON 0 TA F701
COMMAND D7 D6 D5 D4 D3 D2 D1 D0 F703
ADDRESS PTR HI RDATA AUTO-INC 0 0 0 A10 A9 A8 F705
ADDRESS PTR LO A7 A6 A5 A4 A3 A2 A1 A0 F707
DATA D7 D6 D5 D4 D3 D2 D1 D0 F709
RSRV'D 0 0 0 0 0 0 0 0 F70B
CONFIG RESET CCHEN TXEN ET1 ET2 BCK PLNE SUB-AD1 SUB-AD0 F70D
TENT-ID NODE-ID SETUP TID7 NID70 TID6 NID60 TID5 NID50 TID4NID40 TID3NID30 TID2NID2CKP1 TID1NID1CPK0 TID0NID0ARBSL F70F
As noted above, all accesses to the COM registers and RAM are made on odd address boundaries.
Address range F780-F7FF is mapped to an 8-bit latch into which the current ARCnet Node Address is written (odd byte only). The address needs to be written during system initialization or after any change is made to the ARCnet Address.
12. BACKGROUND DEBUGGER
The debugger/monitor uses many assembly-language subroutines that have been developed over several years. New routines will be added and refined as development of the 1032 continues. The debugger currently implements the following commands:
HE - display help menu
SB n - set breakpoint at n
RB n - remove breakpoint at n
LB - list breakpoints
DB/W m n - display bytes/words from m to n
MB/W m - modify byte/word at location m
GO m - execute program at m
MR n - modify register n
DR - display register contents
HL - hex load (Intel format)
CK - display TCLK events
EI,DI - enable/disable vectored interrupts
BT m - output to block transfer port data m
FB - fill memory from m to n with (bytes)
R<cr> or / - Repeat last command
13. FRONT PANEL DESCRIPTION
13.1 LEDS
The following is a list of the front panel leds:
N: This led will be lit when the CAMAC N line is asserted for this module.
LAMEN: When lit indicates that LAMs are enabled.
LAM: When lit indicates that a LAM is asserted.
TCLK: This led will be lit if the TCLK is present on the CAMAC backplane.
TREQ: When the C1032 is ready to receive data from the Serial Block transfer, this led will be lit.
RRDY: When lit indicates that the C1032 is receiving a ready signal on the RRDY input and the attached module is ready to receive data on the serial block transfer TDATA line.
VCC: Will be lit when there is +6 volt power to the module.
-VCC: Will be lit when there is 6 volt power to the module.
MOTOUT: When lit indicates that SWIC is in the "out" position.
MOTIN: When lit indicates that SWIC is in the "in" position.
START: Indicates status of the "start" output line.
CLEAR: Indicates status of the "clear" output line.
HEARTBEAT: This led will blink when the heartbeat routine is running.
ARCnet DSYNC active: Will be on continuously if ARCnet is passing tokens. It will be blinking if re-configures are occurring. It will be off if no signal is received from another device.
ARCNET ADDRESS: These 8 LEDs indicate the ARCnet address of the C1032. The LEDs are arranged on the front panel as follows:
D7 D3
D6 D2
D5 D1
D4 D0
13.2 LEMO Connections
ARCNET: The broadcast data link (ARCnet) connects to the C1032 through this front panel LEMO which must then be adapted to coax. (bi-directional)
TRANSMIT REQUEST (TREQ): Is used to indicate readiness to receive data on the block transfer serial link. (input)
TRANSMIT DATA (TDATA): This is the serial block transfer output data connector, which should be connected to RDATA of another module. (output)
RECEIVE DATA (RDATA): Normally connected to another module's TDATA to provide an input for serial block transfer data. (input)
RECEIVE READY (RRDY): The Serial block transfer fifo is ready to receive data. (output)
13.3 RS-232 Connector
A 4-pin LEMO connector provides RS-232 from the front panel. Below are the pin assignments counter-clockwise from the top of the connector:
1 - Ground
2 - TXDATA
3 - RXDATA
4 - not used
13.4 Reset Switch
A push-button switch is provided which resets the module.
14. CAMAC CONNECTIONS
This module conforms to ANSI/IEEE STD 583 1982 spec. table 2, page 19 for CAMAC contact allocations of a normal station. No connection is made to the +12, 12, +24, 24, C, I, or B lines. Lines P1 and P2 are connected to the Tev Clock Decoder circuit.
14.1 Auxillary Connector
Auxillary connector (P2) pin assignments for the C1032 are a superset of the 032 pin-out. The pin assignments for the auxillary connector are as follows:
P2L-1 GND P2R-1 GND
P2L-2 RXDATA P2R-2 TXDATA CH-A RS-232
P2L-3 GND P2R-3 RRDY
P2L-4 RXL P2R-4 RXH DI-PHASE RECEIVE
P2L-8 RXDATB P2R-8 TXDATB CH-B RS-232
P2L-9 TXL P2R-9 TXH DI-PHASE TRANSMIT
P2L-10 TREQL P2R-10 TREQH
P2L-12 MOTO-W P2R-12 START
P2L-13 MOTO-NC P2R-13 CLEAR
P2L-14 MOTO-NO
P2R-14 MOTI-W
P2L-15 MOTI-NO P2R-15 MOTI-NC
P2L-16 "IN" STAT. P2R-16 "OUT" STAT.
P2R-17 STATUS COM. “STATUS COMMON IS ISOLATED FROM CIRCUIT GND”
15. SWITCHES and JUMPERS
The module contains the following switches and jumpers:
15.1 Sanity Timer Jumpers
A jumper option is provided for the DS-1232 keep-alive monitor IC. The jumper selects either AS' or VIACK' as the input to the IC. A pulse must be seen at the input at least once every 1.2 seconds.
15.2 Reset Switch
A front panel push-button switch is provided which resets the module.
16. MECHANICAL SPECIFICATIONS
This module complies with ANSI Std 583 1982 Mechanical specs. as shown in Fig.4 page 48 and Fig.8, page 53.
16.1 Typical CAMAC Dataway Connector
As described in Fig K4.2.2 of ANSI Std 583 1982 page 16.
16.2 CAMAC Board Specifications
16.3 CAMAC Board Layout
The parts selected fit on a single-wide CAMAC module. The CAMAC board has 6.57in x 11in (72 sq. in.) of usable space. The P.C. card is a 6-layer board composed of separate power and ground layers with four signal layers.
17. ELECTRICAL SPECIFICATIONS
17.1 CAMAC Dataway
This module complies with all the CAMAC signal requirements as specified in the ANSI Std 583 1982, page 39, Table 6, and all specifications as stated in the standard under section 7, Signal Standards.
17.2 Power Requirements
This module conforms to ANSI Std 583 1982 as stated in section 8, Power line standards. This board uses +/- 6v CAMAC power connections and is fused at 4A for +6v, and 1A for -6v. The input power connections have bypass capacitors and tranzorbs for transient protection. Pico-fuses provide protection against damage to the printed circuit board in the event of component failure or improper installation.
APPENDIX A
A.1 INITIALIZATION
A preliminary initialization program can be examined by referring to Warner::USR$DISKS:[HDWDOCS.C1032.SOFT] files C32VXX.80K (XX==LATEST VERSION NUMBER).
A.2 INSTALLATION
The C1032 module should have jumpers configured according to previously described specifications. While the C1032 is compatible with existing 032 I/O connector wiring harnesses, it is best to also install a new wiring harness that includes the START and CLEAR signals.
The front panel ARCnet LEMO connector does not require connection to a network for the module to function properly. After turning on the power, the +/- Vcc LEDs should be lit, indicating that the fuses are intact and there is power to the module. At this time, the module should also have reset itself and performed it's initialization routines. The heart-beat LED should be blinking.
APPENDIX B
B.1 ELECTRONIC DRAWINGS
See Warner::USR$DISKS:[HDWDOCS.C1032.PCAD]*.SCH for PCAD schematics of the design. This is a multi-sheet design.
B.2 PAL and EPLD EQUATIONS
See Warner::USR$DISKS:[HDWDOCS.C1032.PAL]*.ABL for PAL equations.
B.3 MECHANICAL DRAWINGS
See Warner::USR$DISKS:[HDWDOCS.C1032.PCAD] for available P.C. board layout and front panel drawings. The board layout was done using PC-CARDS.
APPENDIX C
C.1 Function Code Documentation
See Warner::USR$DISKS:[HDWDOCS.C1032.DOC]C32FUNC.DOC for a complete list of supported camac function codes
Keywords:
Controls, EPICURE, ARCnet,....
Distribution: normal