RD Controls

Special Project Note 6.3

WAVEFORM CAPTURE SYSTEM (WCS)

Signal Integrator & Memory (SIM) Module

Hardware Specification for

the Intermediate Prototype

Mark Kozlovsky

Al Legan

Miriam Bleadon

November 25, 1992

Table of Contents

1. General Description 2

2. Technical Characteristics 3

3. VXI Interface 5

3.1 Data Channels 8

3.2 Control Bit Designation 8

4. Structure of the WCS Signal Integrator 9

4.1 Overview 9

4.2 Signal, Data, Memory and I/O lines 11

4.2.1 Signal Bus 11

4.2.2 Data Bus 11

4.2.3 I/O Bus 11

4.2.4 Memory Bus 12

4.3 The Host I/O Controller 12

4.4 Modes of Operation 15

4.4.1 IDLE 15

4.4.2 TEST 15

4.4.3 MEASURE 16

4.5 Memory Organization 16

4.5.1 Internal Memory Controller 19

4.5.2 Test Memory Controller 23

4.5.3 Host Memory Controller 26

4.6 Encoder Interface 26

4.7 ECL Interface 26

4.8 Encoder Up-Down Counter 27

4.9 Trigger Source Controller 31

4.9.1 Trigger Source Register 31

4.9.2 Synchro Pulse Register 32

4.10 V/F Counter 35

4.11 Status Controller 37

5. Operation 39

6. Packaging Information 40

7. Front Panel 40

Appendix A 43

Appendix B 49

Appendix C 58

Appendix D 61

Appendix E 62

Appendix F 63

1. General Description

The WCS Signal Integrator will be built as a single wide VXI module. It could be controlled either directly by an embedded P.C., or indirectly through a Slot-0 VXI controller via a GPIB interface, connected to an external host computer.

The environment in which this module is supposed to work is shown in Figure 1, where Fig. 1a represents the system structure for the intermediate prototype of the WCS, and Fig. 1b - the system structure of the actual WCS.

The WCS Signal Integrator will perform the following tasks in the systems shown above:

* it will accept V/F and encoder inputs and will monitor them in Up-Down counters whose contents will be placed in memory on commands from the trigger source;

* it will process encoder inputs in such a manner as to provide trigger signals only for absolute changes (increases or decreases) in the encoder position that coincide with a preferred direction;

* it will select sources of incoming V/F signals and trigger pulses;

* it will pre-scale a number of trigger pulses by a given coefficient;

* for each period of the pre-scaled trigger pulses it will generate a stream of synchro pulses with given frequency and number of pulses;

* it will use synchro pulses to initiate subsequent readings of contents of all up-down counters and write them into internal memory;

* it will test the functionality of its major components "on the fly" and inform the host system if any error occurs.

2. Technical Characteristics

a) the number of trigger sources:

* internal VXI TTL 1

* internal from Encoder 2

* external TTL 3

* external ECL 2

b) resolution of the pre-scaler, bits 4

c) maximum number of synchro pulses 255

d) synchro pulse frequencies 0.125 Hz...250 KHz

(see Table 7, p.33)

d) number of up-down counters 4

e) counter size

* Encoders 16 bits

* V/F converters 32 bits

f) memory organization:

* type: SRAM

* word size 16 bits

* number of segments 4

* number of blocks in a segment 4

* block size 8K words

* overall volume 128K words

g) number of V/F signal sources 4

Monitor Only 2

h) number of encoder sources (external) 2

i) V/F and encoder inputs:

* V/F SIG0

DIR0

SIG1

DIR1

SIG2

DIR2

SIG3

DIR3

* encoder inputs ENC0_A

Quadrature ENC0_B

0-5 Volt TTL ENC1_A

ENC1_B

ENC0_Ref

ENC1_Ref

j) monitored outputs TRIG_SOURCE

PRE_SCALER

SYNCHRO_PULSE

l) interface:

* internal User's Parallel Interface

* external Message Based VXI

m) power supply External (from VXI)

n) embedded microprocessor none

o) hardware self-test features check memory boundaries,

check data written into the memory,

3. VXI Interface

For the intermediate prototype the WCS Signal Integrator will employ the VXI-5523 adapter card from ICS Electronic Corporation . This adapter provides a complete VXI bus interface capable of performing message based data transfer. It also has a 3 row by 32 pin DIN connector for User's Parallel Interface with the signals listed in Table 1.

The VXI-5523 firmware uses the following IEEE 488.2 common commands: *CLS, *ESE, *ESE?, *ESR?, *IDN?, *OPC, *OPC?, *RST, *SRE, *SRE?, *STB?, *TST?, and *WAI. Their titles and brief descriptions are given in Table 2.

The VXI-5523 also has a series of commands to set up the parallel interface. These need only be set once, at initial power-up. This desired interface configuration can also be saved in on-board non-volatile memory. In addition, the interface card also provides commands to transfer data between the VXI bus and the user circuitry, which for our purposes is the heart of the signal integrator module.

Table 1 The User Parallel Interface

PinNo Row A Row B Row C Pin No Row A Row B Row C

1 CLC16 +5V +12V 17 I/O 30 I/O 31 I/O 32

2 GND GND -12V 18 I/O 33 I/O 34 I/O 35

3 SLFST _IND- IORST- IORDY0 19 I/O 36 I/O 37 I/O 38

4 ERROR _IND- I/CLR- IORDY1 20 I/0 39 I/O 40 I/O 41

5 STATUS0 IORDY2 IOSTB0- 21 I/O 42 GND I/O 43

6 STATUS1 IOSTB2- IOSTB1- 22 I/O 44 I/O 45 I/O 46

7 I/O 1 I/O 2 I/O 3 23 I/O 47 I/O 48 I/O 59

8 I/O 4 I/O 5 I/O 6 24 I/O 50 I/O 51 I/O 52

9 I/O 7 I/O 8 I/O 9 25 I/O 53 I/O 54 I/O 55

10 I/O 10 I/O 11 I/O 12 26 I/O 56 LBUS1 LBUS0

11 I/O 13 GND I/O 14 27 TTL TRIGGO- LBUS3 LBUS2

12 I/O 15 I/O 16 I/O 17 28 TTL TRIGGI- LBUS5 LBUS4

13 I/O 18 I/O 19 I/O 20 29 CLK10+ LBUS7 LBUS6

14 I/O 21 I/O 22 I/O 23 30 CLK10- -5.2V -2V

15 I/O 24 I/O 25 I/O 26 31 GND GND +24V

16 I/O 27 I/O 28 I/O 29 32 +5V +5V -24V

Table 2 IEEE 488.2 Command List

Command Title Description

*IDN? Identification query Returns identification string of the VXI-5523

*RST Reset Resets the VXI-5523 to a specific state

*TST? Self-test query Returns 0 unless self test fails

*OPC Operation complete Sets OPC bit in the Standard Event Register when all pending operations are completed

*OPC? Operation complete query Returns a 1 to the output queue when all pending operations have completed

*WAI Wait to Continue Halts execution of commands and queries until the current operations are completed

*CLS Clear status register Clears all Event Registers and updates Status Byte Register

*ESE<mask> Event status enable Sets the bits in the Event Status Enable Register

*ESE? Event status enable query Queries the current contents in the Event Status Enable Register

*ESR? Event status register query Queries and clears contents in the Standard Event Status Register

*SRE<mask> Service request enable query Sets the enable bits in the Service Request Enable Register

*SRE? Service request enable query Queries the current contents in the Service Request Enable Register

*STB? Read status byte query Queries the current contents in the Status Byte Register

The VXI-5523 provides the following VXI capabilities:

* static and dynamic configuration capability

* message based, 14 class instrument

* message based slave device

* 16-bit address space

* programmable interrupt for data ready

* status line change on errors

* event generator for all protocol errors

* normal handshake data transfer

* supports VXI instrument protocol and IEEE 488.2 common commands.

The VXI interface uses the P1 and P2 connectors. VXI signals include TTL TRIG lines, CLK 10+- SYSCLK, and eight LBUS lines. The LBUS lines are strappable to either row A or C local bus lines on connector P2.

Bit 0 in the VXI status byte is used as our signal to the host computer that there is an error on the module. If Bit 0 is high, then an error has occurred. The host should read the status register, I/O address 0x000F on the SIM, to help diagnose the occurrence.

The I/O lines from the User Parallel Interface can be subdivided into three channels by 8-bit increments, each of which can be designated either as a gated input or as a latched output.

1.1 Data Channels

The following configuration of these channels will be used in this design:

CHANNEL I/O LINES TYPE PURPOSE

1 1-24 gated input Control and Address

2 25-40 gated input Data Input

3 41-56 latched output Data Output

All channels will use handshake protocol to communicate with the host computer. The Control and Address channel is 24 bits wide. The upper 8 bits ( Bits 16-23 ) determine the command to be executed. The lower 16 bits ( Bits 0-15 ) hold the register or memory address that is to be operated upon. Channels 2 and 3 are each 16 bits wide, and are for data input and output.

1.2 Control Bit Designation

The following is the designation for the upper 8 bits in the Control and Address Channel.

BIT FUNCTION

16 Spare

17 Mode Select

18 Write I/O

19 Write Memory

20 Read I/O

21 Read Memory

22 Reset SIM

23 Test Memory

2. Structure of the WCS Signal Integrator

2.1 Overview

The structure of the module is given in Figure 2.

The module includes:

* ECL and Encoder Interfaces;

* Trigger Source Controller;

* Two Encoder Up-Down Counters (with Encoder Filters);

* Two V/F Up-Down Counters;

* Internal Memory Controller;

* Test Memory Controller;

* Host Memory Controller;

* Memory (128K * 16-bit words);

* Status Controller;

* I/O Controller;

* VXI Interface;

* Hardware Reset.

All Up-Down Counters and Controllers are implemented in PLDs.

Most of the internal communication signals are combined in four buses. They are:

* Signal Bus;

* Data Bus;

* I/O Bus;

* Memory Bus.

Fig.2 Signal Integrator and Memory Block Diagram

2.2 Signal, Data, Memory and I/O lines

2.2.1 Signal Bus

* ENCENA0 - Encoder 0 counter enable;

* ENCENA1 - Encoder 1 counter enable;

* VF_ENA0 - Voltage to frequency 0 counter enable;

* VF_ENA1 - Voltage to frequency 1 counter enable;

* FILTENA0 - Filter for encoder 0 enable;

* FILTENA1 - Filter for encoder 1 enable;

* V_FSIGS0 - Signal selection 0 (VF source);

* V_FSIGS1 - Signal selection 1 (VF source);

* ENCTRG0 - Encoder trigger pulse 0;

* ENCTRG1 - Encoder trigger pulse 1;

* REF0 - Encoder reference reset 0;

* REF1 - Encoder reference reset 1.

2.2.2 Data Bus

Includes 16 data lines D00...D15.

2.2.3 I/O Bus

* ENCRD0 - Read encoder counter 0;

* ENCLD0 - Load encoder counter 0;

* ENCRD1 - Read encoder counter 1;

* ENCLD1 - Load encoder counter 1;

* FILTRD0 - Read filter for encoder 0;

* FILTRD0 - Read filter for encoder 1;

* REFRD - Read reference source;

* REFLD - Write reference source;

* VFRDL0 - Read V/F counter 0 low word ;

* VFLDL0 - Load V/F counter 0 low word ;

* VFRDH0 - Read V/F counter 0 high word;

* VFLDH0 - Load V/F counter 0 high word;

* VFRDL1 - Read V/F counter 1 low word;

* VFLDL1 - Load V/F counter 1 low word ;

* VFRDH1 - Read V/F counter 1 high word;

* VFLDH1 - Load V/F counter 1 high word;

* SOURCRD - Read trigger pulse source;

* SOURCLD - Load trigger pulse source;

* SYNCHRD - Read synchro pulse generator;

* SYNCHLD - Load synchro pulse generator;

* SEGRD - Read segment;

* SEGLD - Load segment;

* MODERD - Read mode;

* MODEWR - Write mode;

* IMCADRD - Read internal memory controller address;

* TADDRD - Read test controller memory address.

* TSEGRD - Read test controller segment address.

* SOFTREF - Software Reference signal.

2.2.4 Memory Bus

* MEMAD00..MEMAD15 - Memory address lines from 0 to 15;

* /RMCE1_2, /RMCE3_4 - Two additional lines to differentiate four memory segments;

* /RAMWE - Write memory;

* /RAMOE - Read memory;

* /ENCOE0 - Encoder counter 0 output enable;

* /ENCOE1 - Encoder counter 1 output enable;

* /VFOELO0 - V/F counter 0 low word output enable;

* /VFOEHI0 - V/F counter 0 high word output enable;

* /VFOELO1 - V/F counter 1 low word output enable;

* /VFOEHI1 - V/F counter 1 high word output enable.

2.3 The Host I/O Controller

The host I/O controller allows the host computer to address all I/O registers inside the signal integrator. It also includes some logic to perform "cold" and "warm" resets on the module.

The block diagram for the host I/O controller is given in Figure 3. It includes:

* address register;

* load and read decoders;

* write/read logic;

* handshake logic;

* reset logic.

The handshake logic works as it is defined in the VXI-5523 specification. It uses the incoming inhibit signal (the cycle signal on the signal integrator block diagram) to stretch I/O read and write cycles. The incoming I/O read and write signals distinguish between I/O read and write registers.

To operate on a particular I/O register, its address must be written into the lower 16 bits ( only the lower 5 bits are used ) of the Control and Address Channel of the VXI Interface. The function that is to be performed must be written into the upper 8 bits of that same channel. To WRITE I/O, bit 18 ( I/O Line 19 ) must be turned on. To READ I/O, bit 20 ( I/O line 21 ) must be turned on.

ADDRESS NAME FUNCTION

0000H Trigger Source R/W, 16 bit data

0001H Spare ( Not Used )

0002H Synchro Pulses R/W, 16 bit data

0003H Memory Segment R/W, 2 bit data

0004H Encoder Counter 0 R/W, 16 bit data

0005H Encoder Counter 1 R/W, 16 bit data

0006H V-f Counter 0, Low Byte R/W, 16 bit data

0007H V-f Counter 0, High Byte R/W, 16 bit data

0008H V-f Counter 1, Low Byte R/W, 16 bit data

0009H V-f Counter 1, High Byte R/W, 16 bit data

000AH Encoder 0 Filter R, 16 bit data

000BH Encoder 1 Filter R, 16 bit data

000CH Internal Memory Counter R/W, 14 bit data

Address ( Even Only )

000DH Reference Source R/W, 2 bit data

000EH Mode R/W, 2 bit data

000FH Status R, 8 bit data

0010H Memory Test Address R, 16 bit data

0011H Memory Test Segment R, 16 bit data

0012H Software Reference Pulse W, 0 bit data

After writing the appropriate control function and address to the Control and Address channel, the I/O cycle must be completed by either writing data to channel 2, or by reading data from channel 3.

Fig. 3 Host I/O Controller Block Diagram

2.4 Modes of Operation

The SIM can operate in three distinct modes: IDLE, TEST, and MEASURE. Specific operations are associated with each. Bits 17 and 23 ( I/O lines 18 and 24 ) in the Control and Address channel are used to set the mode. Refer to Table 3.

Table 3 Working Modes

WORKING MODE CONTROL AND ADDRESS CHANNEL

MODE SELECT Bit 17, I/O line 18 TEST MEMORY Bit 23, I/O line 24

IDLE 0 0

MEASURE 1 0

TEST 0 1

INVALID 1 1

Whenever an I/O WRITE is performed on the Mode Select register (I/O address 0x000E), the values on Bits 17 and 23 in the Control and Address Channel get latched in. To select the operation mode, first set Bits 17 and 23 appropriately. Bit 18 should then be set for I/O WRITE, and Bits 0-15 should be set to 0x000E for the mode register address. Write this 24 bit value to the Control and Address channel. Finish the I/O Cycle by writing dummy data to channel 2.

1.1.1 IDLE

The device comes up in the IDLE mode, and can also be placed there by pressing the front panel RESET button, or by raising Bit 22 ( I/O line 23 ) in the Control and Address channel. While in the IDLE mode, the host computer has unrestrained access to all memory and I/O on the SIM. It is from this mode that the host computer should configure the device for future measurements.

1.1.2 TEST

From IDLE, a full memory test can be performed by changing the mode to TEST. While the exercises are underway, there can be no external access to the internal memory. The Test Memory Controller ( See section 4.5.2 Test Memory Controller ) will attempt to verify that all memory is functioning properly. When the exercises are completed, the mode will default back to IDLE. If the tests fail Bit 0 in the VXI status byte will be raised. The Memory Test Segment register ( I/O address 0x0011 ) and the Memory Test Address register ( I/O address 0x0010 ) can be read to determine where the tests failed.

1.1.3 MEASURE

Once placed in MEASURE mode, the device will wait for a reference pulse, then accept triggers and write V-f and encoder data into memory. External memory access is completely blocked while in this mode. However there is no block on I/O. Software must be written to prevent an errant program from changing the active segment and address during the course of a measurement.

For more information, refer to Section 5 Operation.

1.2 Memory Organization

The module employs CYM1831 64K x 32 Static RAM Module with 35 ns access time from CYPRESS SEMICONDUCTOR as its primary memory chip.

The memory is organized as four segments, each of which has four blocks of 8K X 16 bit words. Each of the four blocks is reserved for data from one of the four available data sources (2 V_F 32 bit counters, and 2 Encoder 16 bit counters). Since the data may be up to 32 bits wide, each block can hold up to 4096 measurement points, from a particular counter. A single segment therefore, can hold all of the data, from all four counters, for a measurement containing 4096 points. The entire memory accommodates four such segments.

To access data, first write the appropriate value into the Segment register ( I/O address 0x0003 ).

* 0000H - segment 0 * 0002H - segment 2

* 0001H - segment 1 * 0003H - segment 3

The function that is to be performed must then be written to the upper 8 bits of the Control and Address channel. To WRITE MEMORY, bit 19 ( I/O line 20 ) must be raised. To READ MEMORY, bit 21 ( I/O line 22 ) must be raised. The desired memory address should then be written into the lower 16 bits of that same channel. After writing this 24 bit value to the Control and Address channel, the MEMORY cycle must be completed by either writing data to channel 2, or by reading data from channel 3.

Table 4 gives an example of how the measurement cycle data is stored in memory. Because the Encoders are 16 bit counters only the EVEN memory addresses are used.

The Memory Map is shown in Figure 4.

Table 4 Data Storage

MEMORY SEGMENT 0 thru 3

Cntr. Name First Synch Second Synch Third Synch Fourth Synch

Encoder #0 Addr. - 0000H Addr. - 0002H Addr. - 0004H Addr. - 0006H

Encoder #1 Addr. - 2000H Addr. - 2002H Addr. - 2004H Addr. - 2006H

V_F Counter #0 LB Addr - 4000H LB Addr - 4002H LB Addr - 4004H LB Addr - 4006H

HB Addr - 4001H HB Addr - 4003H HB Addr - 4005H HB Addr - 4007H

V_F Counter #1 LB Addr - 6000H LB Addr - 6002H LB Addr - 6004H LB Addr - 6006H

HB Addr - 6001H HB Addr - 6003H HB Addr - 6005H HB Addr - 6007H

Fig. 4 SIM Memory Map

There are three memory controllers in the SIM that share one memory bus. They are:

* internal memory controller;

* test memory controller;

* host memory controller.

1.1.1 Internal Memory Controller

The internal memory controller is a finite state machine that performs six subsequent memory operations (one operation includes both write and read cycles). The block diagram is given in Figure 5. It consists of:

* 2-bit mode register;

* mode buffer;

* overflow trigger;

* 5-bit cycle counter;

* cycle trigger;

* cycle decoder;

* read/write 12-bit memory address counter;

* 8-bit control register;

* read/write logic;

* 8-bit control buffer;

* 16-bit data buffer;

* 16-bit memory address buffer.

The Mode register ( I/O address 0x000E ) stores the current mode programmed by the host computer, and the mode buffer allows this mode to be read back. See section 4.4 Modes of Operation for more information.

Each incoming synchro pulse sets the cycle trigger, and initializes the cycle counter. When the cycle trigger is set, the data bus is reserved for transcribing the data into memory. All external I/O access is blocked, preventing possible data corruption. Once initialized, the cycle counter will start monitoring pulses from the 16 MHz clock line. A total of 32 pulses from this line are necessary to complete one full measurement cycle, consisting of accessing and reading the counters, and writing the data into memory. The overflow signal from the cycle counter sets the cycle trigger back to 0, releasing the data bus.

The cycle counter states are decoded by the cycle decoder. The use of each state is shown in the timing diagram given in Figure 6.

The first data word will be written into the present segment, at the address stored in the address counter. By design, this address will always represent a location within the first block of the segment. Successive writes are placed into locations pointed to by the sum of the address counter, and the cycle decoder. Together, these two form a full 14 bit memory address within the segment. This has the effect of incrementing the address by blocks, such that successive data values will be written into successive blocks, starting at the same offset within each block.

The address counter is buffered, and can be read by the host computer. The value obtained will show the address (or offset) within the first block, of the present segment, where the module will begin storing the next full cycle of data.

The overflow trigger checks the memory boundaries, if exceeded, the status controller alarms. This removes the SIM from the MEASURE mode and places it back into the IDLE mode.

The memory write and read logic together with the control register form the control subsystem which supplies all of the needed signals to control the data flow during this cycle.

Fig.5 Internal Memory Controller Block Diagram

Fig.6 Internal Memory Controller Timing Diagram

1.1.2 Test Memory Controller

The Test Memory Controller generates memory operations for the full range of memory address space. The test consists of writing to each address a data word equal to the address, and then verifying its presence. This is performed at boot-up, or whenever the mode is set to TEST. The device will be in TEST mode for the duration of the exercise. While in that mode, all other operations are prohibited. The block diagram is given in Figure 7. It includes:

* cycle trigger;

* 4-bit cycle counter;

* cycle decoder;

* data enable trigger;

* 17-bit address counter;

* segment decoder;

* control buffer;

* segment buffer;

* segment data buffer;

* data buffer;

* address buffer.

In the TEST mode, the cycle counter monitors pulses from the 16 MHz clock. Output from the cycle decoder is then used to form memory addresses and the equivalent data. It also produces the memory read and write signals. Data enable triggers determine the time interval during a memory operation when data is stable.

The memory is traversed sequentially, instead of jumping around from one block to the next. All four segments are tested. During the test, the status controller checks the validity of the data. As soon as a failure is recognized, Bit 0 in the VXI status byte will be pulled high, and the test will cease. The host computer can then read the Memory Test Address register ( I/O address 0x0010 ) and the Memory Test Segment register (I/O address 0x0011 ) to determine were the failure occurred. If no errors were detected, then upon termination, the address counter issues the overflow signal. This resets the cycle trigger, and ends the test process.

Fig.7 Test Memory Controller Block Diagram

Fig.8 Host Memory Controller Block Diagram

1.1.3 Host Memory Controller

The host memory controller provides direct access to the memory from the host computer. It is disabled during measurements. The block diagram is given in Fig. 8. It is comprised of data, segment, and address registers, segment decoder, memory write/read logic, and VXI handshake logic.

The handshake logic is done in accordance with the requirements for the VXI-5523 and employs the inhibit signal to prevent memory write and read signals from occurring during the measurement mode. The inhibit signal, is shown as the mode signal in the signal integrator block diagram.

1.2 Encoder Interface

The encoder interface is responsible for rejecting noise, and preventing module components from being damaged by spikes on incoming quadrature encoder signals. It consists of four identical channels each of which is built according to the block diagram given in Figure 9.

Fig.9 Encoder Interface Block Diagram

The detailed description of this kind of filter and requirements to the system design are given in the Hewlett Packard Quadrature Decoder Counter Interface IC HCTL-2000 specification. The rule of thumb is that clock frequency should be at least 4 MHz.

1.3 ECL Interface

The ECL interface converts ECL triggers to TTL triggers.

1.4 Encoder Up-Down Counter

The encoder counter block diagram is given in Figure 10. It includes:

* Quadrature Encoder Decode Circuit;

* Clocked Counter Data Register;

* Data Read Encoder;

* 16-bit Encoder Counter;

* 16-bit Position Counter;

* 16-bit Comparator;

* Trigger Pulse Gate Logic;

* Data Read Multiplexor;

* Reference Register.

The quadrature decoder, the encoder counter, position counter, comparator, and trigger pulse gate logic comprise a filter whose model and timing diagram are shown in Fig. 11.

The measurement test stand will provide the SIM with input from a quadrature encoder. The input will be in the form of two pulse trains ( 0-5V ) whose relative phase indicates the direction of travel. If the filter is enabled, then this phase relationship is monitored, and only those pulses corresponding to an absolute change in position, in a preferred direction of travel, will be considered to be valid. These valid pulses will be forwarded to the Encoder Counter. With this technique we are removing any backlash pulses which could occur due to mechanical vibrations or encoder backlash. The individual filters and encoder counters can be read out at the following I/O register addresses:

Encoder Filter 0 0x000A

Encoder Filter 1 0x000B

Encoder Counter 0 0x0004

Encoder Counter 1 0x0005

The host computer can choose to preload any of these registers with a particular value. To operate Encoder Filter 0, it must first be enabled, by raising Bit 12 in the Trigger Source register ( I/O address 0x0000 ). To choose the preferred counting direction, the PREDIR1 bit in the Reference register must be set appropriately. In a similar manner, to operate Encoder Filter 1, enable it by raising Bit 13 in the Trigger Source register, and then choose the preferred counting direction by setting the PREDIR2 bit appropriately. Details of the PREDIR bits and the Reference register ( I/O address 0x000D ) can be found in Table 5. Further details of the Trigger Source register can be found in section 4.9 Trigger Source Controller.

Table 5

REFERENCE REGISTER - ADDR 0x000D

Description Bit # 0 1

REFERENCE SELECT 0 FROM ENCODER 0 FROM ENCODER 1 ReadWrite

PREDIR0 1 ENCODER 0 COUNT DOWN ENCODER 0 COUNT UP Read Write

PREDIR1 2 ENCODER 1 COUNT DOWN ENCODER 1 COUNT UP Read Write

REFERENCE RECEIVED 3 NO REFERENCE RECEIVED REFERENCE RECEIVED Read Only

The reference received bit is used to indicate if a reference pulse was received. The counters will be allowed to count data only after the SIM is put into the MEASURE mode and a reference pulse is received. The reference can come from either one of the encoder reference pulses, or by way of a software reference pulse. (Writing to I/O register #18.) This bit will be cleared automatically when the SIM module is placed back into the IDLE mode.

The four triggers and the logic associated with them as shown in the filter model given in Fig. 11 constitute the quadrature decoder from the block diagram shown in Fig. 10. The scaler in Fig. 11 is the 16-bit encoder counter shown in block diagram Fig. 10. The logic identified with both the comparator and the position counter, as shown in Fig. 11, is the trigger pulse gate logic from the block diagram given in Fig. 10.

The data read encoder and the data read multiplexor will distinguish among these four devices. The Clocked Data register stores the current counter data information when a Synchro pulse is received. This data will then be written into memory by the internal memory controller. (See Section 4.5.1 Internal Memory Controller.)

Fig.10 Encoder Counter Block Diagram

Fig.11 Encoder Filter

1.1 Trigger Source Controller

The Trigger Source Controller chooses the source of incoming trigger pulses, prescales them with the programmable coefficient, and generates the output stream of synchro pulses at the programmed frequency and pulse number. The block diagram is given in Figure 12, and contains:

* 8-input source multiplexor

* 16-bit pre-scaler divider

* 16-input pre-scaler multiplexor

* synchro-pulse enable trigger

* 20-bit synchro pulse frequency divider ;

* 8-input synchro pulse frequency multiplexor ;

* 8-bit synchro pulse frequency divider ;

* 8-input synchro pulse frequency multiplexor ;

* 8-bit synchro pulse counter;

* 16-bit Trigger Source, pre-scaler, and control I/O register

* 16-bit Synchro Pulse I/O register

1.1.1 Trigger Source Register

The bits in the Trigger Source Register, at I/O address 0x0000 are defined as follows:

D03...D00 - channel number for the trigger source;

0000 = VXITRIG0 0001 = External TTL Trig 0

0010 = External TTL Trig 1 0011 = External TTL Trig 2

0100 = External ECL Trig 0 0101 = External ECL Trig 1

0110 = Encoder 0 0111 = Encoder 1

D07...D04 - trigger pulse frequency divisor:

0000 = 1 0001 = 2 0010 = 4 0011 = 8

0100 = 16 0101 = 32 0110 = 64 0111 = 128

1000 = 256 1001 = 512 1010 = 1024 1011 = 2048

1100 = 4096 1101 = 8192 1110 = 16384 1111 = 32768

D8 - Encoder Counter 0 enable;

D9 - Encoder Counter 1 enable;

D10 - V-f Counter 0 enable;

D11 - V-f Counter 1 enable;

D12 - Encoder Filter 0 enable;

D13 - Encoder Filter 1 enable;

D15...D14 - channel number for V-f source;

00 = V-f config 0 01 = V-f config 1

10 = V-f config 2 11 = V-f config 3

Of the 4 V-f sources which are available at the front panel, only 2 can be measured and recorded to memory. Bits 15 and 14 in the Trigger Source register multiplex between these 4 sources. The configurations are given in Table 6.

Table 6

TRIGGER SOURCE REGISTER - ADDR 0x0000

SIG_SEL1 D15 SIG_SEL0 D14 V-f Ch# 0 V-f CH# 1 CONFIG. #

0 0 Input 0 Input 2 0

0 1 Input 1 Input 3 1

1 0 Input 2 Input 0 2

1 1 Input 3 Input 1 3

1.1.1 Synchro Pulse Register

The bits in the Synchro Pulse register, at I/O address 0x0002, are defined as follows:

D15 - Synchro bypass ( Trigger pulse in = pulse out)

D8...D14 - Synchro pulse frequency;

D0...D7 - number of synchro pulses. (Warning a zero in this register will result in NO synchro pulses. Zero is an invalid number. The number must be between 1 - 255.)

Correspondence between D8...D14 and synchro pulse frequencies is given in Table 7. In order to align on nibble boundaries data bit D11 is not used.

The output synchro pulses may be produced by the internal synchro pulse generator upon receiving any one of the predefined input trigger pulses. Optionally, the synchro pulse circuitry can all be bypassed, and the input trigger pulses can be fed directly to the output. To do this, bit D15 must be set to 1. This will bypass the internal synchro pulse frequency counter and direct the selected trigger pulse frequency divisor to the synchro output. This will use only phase one of the trigger source controller. By default this bit is set to 0, so the output synchro pulse gets generated from both phases of the trigger source controller.

Table 7 Synchro Pulse Frequency (I/O Address 0x0002)

D14..D12 D10...D8

000 001 010 011 100 101 110 111

000 250 KHz 62.5 KHz 3.9 KHz 244 Hz 122 Hz 61 Hz 30.5 Hz 15.25 Hz

001 125 KHz 31.25 KHz 1.95 KHz 122 Hz 61 Hz 30.5 Hz 15.75 Hz 7.625 Hz

010 62.5 KHz 15.62 KHz 975 Hz 61 Hz 30.5 Hz 15.75 Hz 7.9 Hz 3.812 Hz

011 31.25 KHz 7.81 KHz 487 Hz 30.5 Hz 15.75 Hz 7.9 Hz 3.95 Hz 1.906 Hz

100 15.62 KHz 3.9 KHz 243.5 Hz 15.75 Hz 7.9 Hz 3.95 Hz 1.98 Hz 0.953 Hz

101 7.81 KHz 1.95 KHz 122 Hz 7.9 Hz 3.95 Hz 1.98 Hz 0.99 Hz 0.476 Hz

110 3.905 KHz 975 Hz 61 Hz 3.95 Hz 1.98 Hz 0.99 Hz 0.5 Hz 0.238 Hz

111 1.952 KHz 487 Hz 30.5 Hz 1.98 Hz 0.99 Hz 0.5 Hz 0.25 Hz 0.119 Hz

Fig.12 Trigger Source Controller Block Diagram

1.1 V-f Counter

The V-f Counter block diagram is given in Figure 13. It contains:

* signal and direction multiplexors;

* 32-bit up-down counter;

* clocked data register;

* data read encoder and multiplexor.

The data register and the up-down counter can be loaded and read externally. The data read encoder and multiplexor will distinguish between these two devices.

The counters contents will be clocked into the data register upon receiving a synchro pulse, It will then be written into memory by the internal memory controller. (See Section 4.5.1 Internal Memory Controller .)

There are 2 channels for V-f signals, each with its own counter. For the V-f counters to work, and for the data to be recorded, they must be individually enabled. To enable V-f Counter 0, raise Bit 10 in the Trigger Source register. To enable V-f Counter 1, raise Bit 11 in the Trigger Source register. Additionally, the host computer should choose which 2 of the 4 V-f signals available at the front panel will actually be multiplexed into channels 0 and 1. The source selection is controlled by Bits 14 and 15 in the Trigger Source register. Consult section 4.9.1 Trigger Source Register for further information regarding the source signal multiplexing, and the enabling of the V-f counters.

Fig.13 V-f Counter Block Diagram

1.2 Status Controller

The main purpose of the status controller is to monitor the SIM module's functionality "on the fly" and to inform the host computer of malfunctions in any of the modules subsystems. It checks memory boundaries, the validity of data written into memory, and the presence of synchro pulses during measurement periods.

The block diagram for the status controller is given in Figure 14. It contains:

* overflow register;

* data read and write registers;

* data comparator;

* result trigger;

* status register;

* synchro pulse recording logic;

* error logic;

* Input Data buffers.

The data read and write registers clock the data transfers to and from memory. In MEASURE or TEST mode, the data comparator examines these registers. The output (if false) is stored in the result trigger register.

The synchro pulse recording circuitry produces an error if the SIM is placed into the IDLE mode, from MEASURE mode, with no synchro pulses being issued.

An incoming overflow signal, an output signal from the result trigger, or an output from the synchro pulse recording logic will cause Bit 0 in the VXI status byte to be pulled high. Using the *STB? command, the host computer can then detect that an error has occurred. The host should then read the data in the status register, at I/O address 0x000F, to help diagnose the occurrence. The status bits are defined as follows:

BIT ERROR DESCRIPTION

0 No synchro pulse during measurement

1 Memory write error

2 Memory boundary violation

3 Spare

4 Encoder 0 Counter Overflow

5 Encoder 1 Counter Overflow

6 V-f 0 Counter Overflow

7 V-f 1 Counter Overflow

Fig.14 Status Controller Block Diagram

2. Operation

On every boot up, the SIM goes through the reset state. This can also be initiated by pressing the front panel RESET button, or through a software command from the host computer. All I/O registers and counters will be zeroed, and the working mode will be set to IDLE.

The host computer can control the device configuration and operation by loading the appropriate I/O registers on the module. Both memory and I/O access use the VXI-5523 handshake protocol.

A self test can be performed by changing the working mode to TEST. In this mode, the test memory controller will write data to each memory location, with a value equal to the memory address. It will then read the data, and compare it to the desired value. If the comparison fails, then BIT 0 in the VXI status byte will be pulled high. The host computer can read this status byte of the module by sending the GPIB488.2 command, *STB? . If the status byte indicates that an error has occurred, then the host computer can query the status I/O register on the board itself, in which each bit will represent a different error condition. Reading this register will also clear it.

Once the module is configured as desired, it should be placed into MEASURE mode, where it will wait to receive the first reference pulse. Until this reference pulse is received, all counters will be inhibited, and no data will be recorded. Upon receipt of the first reference pulse, the trigger circuitry will be enabled. In addition, any of the four data counters which were specifically enabled in the configuration, will be enabled at this time, allowing encoder and V-f pulses to be monitored.

Each synchro pulse that is then produced by the Trigger Source Controller will cause a single measurement to be recorded to memory. Each measurement requires obtaining data from each of the four counters. Data transfers are 16 bits wide. Two of the counters are 16 bits, while the other two are 32 bits. Therefore, for each measurement, the internal memory controller must execute 6 data transfers, consisting of both READ and WRITE operations. The period of each data transfer is fast enough to allow a maximum synchro pulse frequency of 250 KHz.

The data will be written into the segment and starting point specified by the configuration. These values are stored in the segment register, and in the internal memory counter address register. While in the MEASURE mode, no external call can read or write the onboard memory. However, these I/O registers can be modified. A software flag will be used prevent alteration of the memory segment and memory address registers, while the device is in this mode. Only when the module is in IDLE mode, can the host computer have free access to the memory, and all I/O registers.

The module will continue counting trigger pulses, issuing synchro pulses, and recording data, until it receive a stop command, or until the status controller determines that an error has occurred. It will check for errors in the data transfer from counters to memory. It will also check for violations of memory boundaries, counter overflows, the presence of no synchro pulses, occurring prior to finishing the previous measurement cycle. It will inform the host computer of any abnormality by pulling high BIT 0 in the VXI status byte.

3. Packaging Information

In the intermediate prototype of the Waveform Capture System, the WCS Signal Integrator is made from two separate boards:

* the VXI-5523 Adapter Card with the dimensions 5.036" - length and 9.187" - width

* the User's Board with the dimensions of 8.045" - length and 9.187" - width

* The User's Board will be done on a Robinson Nugent quick wire board.

The two cards are mated together by a right angle DIN connector and mechanically fastened together with a metal bracket. When assembled, they form a full 'C' size VXI board.

To assemble a complete 'C' size VXI module the VXI-KIT from ICS Electronics Corporation is used. It includes a blank front panel with ejectors, side shields and all the necessary hardware to assemble the module.

In the final design, the WCS Signal Integrator will be done as a full 'C' size VXI printed circuit board which will incorporate the DT9110 Interface Daughter-Card, from interface technology. The same VXI-KIT will be used to assemble the complete module.

4. Front Panel

The module's front panel includes:

* three test points to monitor outputs from the trigger source multiplexor, pre-scaler, and synchro pulse generator;

* four LEDs to indicate module status: MEASURE, IDLE, MEMORY TEST, and ERROR;

* one push-button RESET switch;

* 6 pin LEMO type connectors to provide inputs from V/F and encoder sources;

* two LEDs: SELFTST and VXIERR, to indicate the mode and status of the VXI-5523 interface board.

SELFTST shows that the interface board is performing its self-test procedure, and VXIERR - that an error has been discovered during this test or when sending a command the interface does not recognize.

Appendix A

Appendix A provides schematic for the Signal Integrator & Memory module.

Appendix B

Appendix B provides pinouts for all PLDs used in the Signal Integrator & Memory module.

Appendix C

Appendix C list all front panel connectors and defines pinouts.

Appendix D

Appendix D provides a quick reference for I/O addresses.

Appendix E

Appendix E provides a quick reference for the upper bits in the Control and Address channel.

Appendix F

Appendix F provides a quick reference for the status register bits.

Appendix A

Appendix A

Appendix A

Appendix A

Appendix A

Appendix A

Appendix B

Title: SIM MEMORY CONTROLLER

A M A A A

/ / / S D R E A A D D D A A

R R S S E D D M D D D D D D D

E A E E G R _ I D D R R R D D

S M G G E _ V M N R G R _ _ _ R R

E O L R N 1 C E H _ N _ 1 1 1 _ _

T E D D A 5 C M B 1 D 2 2 1 0 9 8

_

/ 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 |

RESERVED | 10 60 | ADDR_7

RESERVED | 11 59 | ADDR_6

CLK16 | 12 58 | ADDR_5

IORDY1 | 13 57 | RESERVED

ADDR_13 | 14 56 | RESERVED

ADDR_14 | 15 55 | D01

GND | 16 54 | VCC

WR_MEM | 17 53 | D00

MEMAD0 | 18 EPM5128 52 | RESERVED

MEMAD1 | 19 51 | RESERVED

VCC | 20 U-1 50 | GND

/IOSTB1 | 21 49 | RESERVED

/IOSTB2 | 22 48 | RESERVED

MEMAD2 | 23 47 | /RMCE3_4

MEMAD3 | 24 46 | /RMCE1_2

/IOSTB0 | 25 45 | /RAMWE

MEMAD4 | 26 44 | RESERVED

|_ 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 _|

M M M M M I G I A A V M M M M M M

E E E E E O N O D D C E E E E E E

M M M M M R D R D D C M M M M M M

A A A A A D D R R A A A A A A

D D D D D Y Y _ _ D D D D D D

5 6 7 8 9 0 2 4 3 1 1 1 1 1 1

0 1 2 3 4 5

Appendix B

Title: TRIGGER SOURCE PRESCALE

/ / /

E E E E S S S

N N C C Y Y O

C C L L C N N U R

T T T T L C C R E

T R R T T K V H H C G S D D D D D

P G G L L 1 C L R L N E 1 0 0 0 0

1 1 0 1 0 6 C D D D D T 0 9 8 7 3

_

/ 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 |

RESERVED | 10 60 | V_FENA0

RESERVED | 11 59 | ENCENA1

D05 | 12 58 | ENCENA0

D06 | 13 57 | TTLTRG1

RESERVED | 14 56 | TRGDVOUT

RESERVED | 15 55 | TTLTRG0

GND | 16 54 | VCC

RESERVED | 17 53 | TTLTRG2

D04 | 18 EPM5128 52 | /VXITRGO

TP2 | 19 51 | TRGOUT

VCC | 20 U-2 50 | GND

RESERVED | 21 49 | TP3

RESERVED | 22 48 | D02

SYNCH | 23 47 | D01

D15 | 24 46 | D00

RESERVED | 25 45 | V_FSIGS0

RESERVED | 26 44 | FILTEN1

|_ 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 _|

R R R R V G G M T / V V D D D D F

E E E E _ N N E R S C _ 1 1 1 1 I

S S S S F D D M G O C F 1 2 3 4 L

E E E E S I R U E T

R R R R I N S R N E

V V V V G H T C A N

E E E E S B R 1 0

D D D D 1 D

Appendix B

Title: ENCODER & FILTER

/

S M E /

O E N / / R / P /

F M C R E E S E R R E

T I R E N N Y F E E N

R N D D D D V E S C G C N _ F D C

E H 0 0 0 0 C F E L N O C L R I R

F B 4 3 2 1 C 1 T D D E H D D R D

_

/ 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 |

RESERVED | 10 60 | ENCENA

RESERVED | 11 59 | ENCB

AGTB | 12 58 | ENCA

ALTB | 13 57 | RESERVED

DNPULSE | 14 56 | RESERVED

UPPULSE | 15 55 | RESERVED

GND | 16 54 | VCC

RESERVED | 17 53 | ENCREFOUT

RESERVED | 18 EPM5128J 52 | ENCTRG

RESERVED | 19 51 | RESERVED

VCC | 20 50 | GND

TRG_RST | 21 49 | PREDIR1O

RESERVED | 22 U-3 / U-4 48 | PREDIR0O

RESERVED | 23 47 | ENCOVRF

D09 | 24 46 | D00

D10 | 25 45 | RESERVED

D11 | 26 44 | D15

|_ 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 _|

D R R R R E G E / F V D D D D D D

1 E E E E N N N F I C 0 0 0 0 1 1

2 S S S S C D C I L C 5 6 7 8 3 4

E E E E R R L T

R R R R E E T E

V V V V F F R N

E E E E 0 I D

D D D D N

Appendix B

Title: V/F COUNTER

V V R R

/ _ _ E E

V V V V F F S S

F F F F S S S E E

R I I I Y I I R R

D N D D D N V N N G G G V V D D D

H P 0 0 0 P C P C S N S E E 1 1 1

I 3 4 3 2 2 C 1 H 0 D 1 D D 5 4 3

_

/ 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 |

/VFRDLO | 10 60 | D12

V_FDIR0 | 11 59 | D09

V_FDIR1 | 12 58 | D07

V_FDIR2 | 13 57 | RESERVED

V_FDIR3 | 14 56 | RESERVED

MEMINHB | 15 55 | RESERVED

GND | 16 54 | VCC

/SOFTREF | 17 53 | RESERVED

RESERVED | 18 EPM5128J 52 | RESERVED

RESERVED | 19 51 | RESERVED

VCC | 20 50 | GND

RESERVED | 21 U-5 / U-6 49 | RESERVED

RESERVED | 22 48 | RESERVED

RESERVED | 23 47 | RESERVED

RESERVED | 24 46 | V_FOVRF

RESERVED | 25 45 | RESERVED

/VFLDHI | 26 44 | D11

|_ 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 _|

/ / / R R V G R E V V D D D D D D

V V V E E _ N E N F C 0 0 0 0 0 1

F F F S S F D S C I C 0 1 5 6 8 0

L O O E E E E R N

D E E R R N T E P

L L H V V A F 0

O O I E E I

D D N

Appendix B

Title: SIM REGISTER CNTLR

/ / / / / /

V / A S S I / A / A /

F M / D Y Y O A A A D T D T

L O S 1 N N R I D D D 1 S 1 A

D D E 0 C C D N D D 1 7 E 6 D

H E G W H H V _ H R G R 9 W G W D

I L L R R L C I I _ N _ R R R R R

0 D D T D D C O B 1 D 2 D T D T D

_

/ 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 |

/VFLDHI1 | 10 60 | /SEGRD

/VFLDLO0 | 11 59 | /STATRD

CLK16 | 12 58 | /MODERD

IORDY1 | 13 57 | /VFRDLO1

HW_RST | 14 56 | /VFRDLO0

RSTIN | 15 55 | /VFRDHI1

GND | 16 54 | VCC

WR_IO | 17 53 | /VFRDHI0

/IMCADRD | 18 EPM5128 52 | /VFLDLO1

/REFRD | 19 51 | RESERVED

VCC | 20 50 | GND

/IOSTB1 | 21 U-7 49 | /IORST

/IOSTB2 | 22 48 | /SOFTREF

RESET | 23 47 | /AD18RD

/ENCRD1 | 24 46 | ADDR_5

/IOSTB0 | 25 45 | /AD19WRT

/AD11WRT | 26 44 | /ENCRD0

|_ 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 _|

/ / / / / I G I A A V / / / / / /

F A F A A O N O D D C S S E E I R

I D I D D R D R D D C O O N N M E

L 1 L 0 0 D D R R U U C C C F

T 5 T 1 1 Y Y _ _ R R L L A L

R W R W R 0 2 4 3 C C D D D D

D R D R D L R 0 1 W

0 T 1 T D D T

Appendix B

Title: INTERNAL MEMORY CTL

/ M M M M

M M M M T M E E E E

E E E O E C O M M M M

M M M D S L D A A A A

A A A D D D V E T K G E D D D D D

D D D 0 0 0 C L I 1 N I 1 1 1 1 1

2 1 0 2 1 0 C D N 6 D N 4 3 2 1 4

_

/ 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 |

TESTCYC | 10 60 | D13

IMCOVRF | 11 59 | D12

TEST | 12 58 | D11

MEMINHB | 13 57 | IOINHIB

IDLELED | 14 56 | /VFOEHI0

MEASLED | 15 55 | /ENCOE1

GND | 16 54 | VCC

/IMCADWT | 17 53 | /ENCOE0

/VFOEHI1 | 18 EPM5128J 52 | D15

/VFOELO0 | 19 51 | RESERVED

VCC | 20 50 | GND

D00A | 21 U-8 49 | SEGENA

D01A | 22 48 | /VFOELO1

MODE | 23 47 | /RAMWE

D03 | 24 46 | /RAMOE

D04 | 25 45 | MEMAD10

D05 | 26 44 | MEMAD9

|_ 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 _|

D M M M M / G / S R V D D D D M M

0 E E E E M N I Y E C 0 0 0 1 E E

6 M M M M O D M N S C 7 8 9 0 M M

A A A A D C C E A A

D D D D E A H T D D

3 4 5 6 R D 7 8

D R

D

Appendix B

Title: STATUS CONTROLLER

S I / S

D D P M S D I T

0 0 A S C R T 0 O A

2 1 R Y O E A 0 R T

I I E N V D V S T I G D U D D D D

N N S C R 0 C E R N N Y S 0 0 0 0

P P T H F 1 C T D P D 1 0 7 6 5 4

_

/ 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 |

D03INP | 10 60 | D03

D04INP | 11 59 | D02

TESTCYC | 12 58 | D00

TEMP4 | 13 57 | D14INP

TEMP1 | 14 56 | D13INP

TEMP2 | 15 55 | D12INP

GND | 16 54 | VCC

TEMP5 | 17 53 | D11INP

D09 | 18 EPM5128JC 52 | D10INP

D10 | 19 51 | D09INP

VCC | 20 50 | GND

RESERVED | 21 U-9 49 | D08INP

RESERVED | 22 48 | D07INP

RESERVED | 23 47 | D06INP

D08 | 24 46 | D05INP

D15INP | 25 45 | STATLED

V_FOVRF0 | 26 44 | ENCOVRF1

|_ 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 _|

V T R R R / G / M / V D D D D D E

_ E E E E R N R O I C 1 1 1 1 1 N

F M S S S A D A D O C 1 2 3 4 5 C

O P E E E M M E S O

V 3 R R R W O T V

R V V V E E B R

F E E E 1 F

1 D D D 0

Appendix B

Title: MEMORY TEST CONTROLLER

/ /

/ T T R R

M T E E M M

E S C S S C C

M E L M T T E E

A D D D D D V G G K G O E C 3 1 D

D 0 0 0 0 0 C R N 1 N D N Y _ _ 1

3 6 5 4 3 2 C D D 6 D E D C 4 2 5

_

/ 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 |

MEMAD4 | 10 60 | D14

MEMAD5 | 11 59 | D13

RESERVED | 12 58 | D01A

RESERVED | 13 57 | MEMAD2

RESERVED | 14 56 | MEMAD1

RESERVED | 15 55 | MEMAD0

GND | 16 54 | VCC

RESERVED | 17 53 | D01

RESERVED | 18 EPM5128J 52 | D00

RESERVED | 19 51 | RESERVED

VCC | 20 U-10 50 | GND

RESERVED | 21 49 | TESTLED

RESERVED | 22 48 | MEMAD14

RESERVED | 23 47 | /RAMWE

D07 | 24 46 | /RAMOE

D08 | 25 45 | MEMAD15

D09 | 26 44 | MEMAD13

|_ 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 _|

D M M M M T G / S R V D D D M M M

1 E E E E E N T T E C 0 1 1 E E E

0 M M M M S D A A S C 0 1 2 M M M

A A A A T D T E A A A A

D D D D D U T D D D

6 7 8 9 R S 1 1 1

D 0 0 1 2

Appendix B

Title: ENCODER DIGITAL FILTER

EPM5032

GND |1 28| CLK16

GND |2 27| ENC0AINP

ENCA0 |3 26| RESERVED

ENCA1 |4 25| RESERVED

ENCB0 |5 24| RESERVED

ENCB1 |6 23| RESERVED

VCC |7 22| VCC

GND |8 21| GND

RESERVED |9 20| RESERVED

RESERVED |10 19| RESERVED

RESERVED |11 18| RESERVED

RESERVED |12 17| RESERVED

RESET |13 16| ENC0BINP

ENC1BINP |14 15| ENC1AINP

U-11

Appendix C

ECLTRG 0 & 1

PIN # SIGNAL

1 ECL -

2 ECL +

3 GND

ECL Trigger input is a TWO pin Lemo Connector which is wired for differential ECL input signals.

Encoder Input Connectors

Encoder Inputs 0 & 1

PIN # Wire Signal

1 GND

2 GND

3 REFERENCE

4 ENCODER A PHASE

5 ENCODER B PHASE

6 N.C.

The encoder input connectors are 6 Pin Lemo. Part # FGG1B306CNAD62. A total of two Encoder connectors are required per module.

Appendix C

V_F Input Connectors

V_F Inputs 0 & 2

PIN # Wire Signal

1 GND

2 V_F Dir 0

3 V_F Input 0

4 V_F Input 2

5 V_F Dir 2

6 GND

V_F Input 1 & 3

PIN # Wire Signal

1 GND

2 V_F Dir 1

3 V_F Input 1

4 V_F Input 3

5 V_F Dir 3

6 GND

The V_F input connectors are 6 Pin Lemo. Part # FGG1B306CNAD62. A total of two V_F connectors are required per module.

Appendix C

Front Panel

Appendix D

I/O Registers

ADDRESS NAME FUNCTION

0000H Trigger Source R/W, 16 bit data

0001H Spare ( Not Used )

0002H Synchro Pulses R/W, 16 bit data

0003H Memory Segment R/W, 2 bit data

0004H Encoder Counter 0 R/W, 16 bit data

0005H Encoder Counter 1 R/W, 16 bit data

0006H V-f Counter 0, Low Byte R/W, 16 bit data

0007H V-f Counter 0, High Byte R/W, 16 bit data

0008H V-f Counter 1, Low Byte R/W, 16 bit data

0009H V-f Counter 1, High Byte R/W, 16 bit data

000AH Encoder 0 Filter R, 16 bit data

000BH Encoder 1 Filter R, 16 bit data

000CH Internal Memory Counter R/W, 14 bit data

Address ( Even Only )

000DH Reference Source R/W, 2 bit data

000EH Mode R/W, 2 bit data

000FH Status R, 8 bit data

0010H Memory Test Address R, 16 bit data

0011H Memory Test Segment R, 16 bit data

0012H Software Reference Pulse W, 0 bit data

Appendix E

Upper 8 bits of Control and Address Channel

BIT FUNCTION

16 Spare

17 Mode Select

18 Write I/O

19 Write Memory

20 Read I/O

21 Read Memory

22 Reset SIM

23 Test Memory

Appendix F

Status Register Bits - I/O Address 0x000F

BIT ERROR DESCRIPTION

0 No synchro pulse during measurement

1 Memory write error

2 Memory boundary violation

3 Spare

4 Encoder 0 Counter Overflow

5 Encoder 1 Counter Overflow

6 V-f 0 Counter Overflow

7 V-f 1 Counter Overflow

Distribution: MTF RD/EED

Mazur, Peter Trendler, Robert

Brown, Bruce Czarapata, Paul

Glass, Henry DeMaat, Robert

Sim, James Watts, Therese

Walbridge, Dana Kramper, Brien

Bleadon, Miriam

Kozlovsky, Mark

O'Brien, Terrence

Legan, Al