Fermilab Digital Delay Card
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The Digital Delay Card provides a time varying delay and notch filter. The input signal is digitized by an A/D and stored in two dual port memories. The data from the two memories is output at different times, the two outputs are subtracted and sent to a digital output. Each side of the memories can be clocked independent of each other, so a time varying delay is created by connecting a frequency varying clock to each side of the memory, delayed by different amounts.
 

General Description
Each delay card contains a fast digitizer, two 8x8k dual port memories, and two fast, 13 bit counters. The digitizer and Input Address Counter are triggered by the Pick-Up clock input, and the Output Address Counter is triggered by the Kicker clock input. Each signal digitized by the A/D is stored in both memories at the memory location specified by Input Address Counter. Data is stored in the memory until the Output Address Counter or the Output Address Counter minus the notch offset matches the address of the data. The outputs of the two memories are subtracted and produces a digital output and an analog output with a D/A converter.

The number of trigger delays between the input and output can be varied using the Bucket Offset register. The notch offset is actually a variable value which uses 13x1k memory look-up table. This table changes value after the number of triggers set by the Change Notch register.

The Booster Digital Delay card is completely VXI compatible. All of its registers and memory locations are accessible through the backplane. It uses the VXI P2 TTL triggers to change it from operating mode to rest mode. A block diagram of the circuit is shown in Figure 2.

VXIbus Interface
The Booster Digital Delay card uses an Interface Technology DT9110 interface card to provide the proper VXI backplane specifications. It must be configured properly for the desired application by adjusting the DIP switches on the card.4 The ID register switches allow the user to change the memory configuration from A24 address space to A32 address space. This card must have at least 32 kBytes of memory space to operate effectively. The figure below shows the ID register and its respective parts. This device must be configured as a register based device, but it may be configured as either an A24 or A32 address space device. The manufacturer ID should be Fermilab's standard VXI address. The default setting is $ebf.

The Device Type register switches must also be configured for proper operation. The first four significant bits determine the amount of memory reserved for the card, and these are set to a maximum of 8 for 32 kbytes in A24 space or set to 15 for 64 kbytes in A32 space. The minimum amount of memory used by a card in A32 address space is 64 kbytes. The model code is defaulted to 257, but this should be compatable with Fermilab VXI standards.


This card is dynamically configurable by the VXI bus, because all the pins of the logical address register are tied high. This means that the resource manager must provide the card with a logical address to run properly.
 

The table below shows the relative addresses of the registers and memory for the card.
 
Register Addresses
Offset From Logical Address
Description
$20 
Bucket Delay
$22 
Change Notch Delay
$24 
Card ID
$28 
Stop Address 

(Read Only)

Memory Addresses
Offset Address
Description
$0 
8k Dual Ports
$4000 
1k Dual Ports
 
Bucket Delay Register
This register stores the value to which the Output Address Counter 1 resets itself when the card is placed in stand-by mode. The value is controlled exclusively by the VXIbus Interface and can be changed during any mode of operation.

Change Notch Delay Register
This register stores the value to which the Change Notch Delay Counter resets itself when the card is placed in stand-by mode or every time the counter reaches terminal count. The value is controlled exclusively by the VXIbus Interface and can be changed during any mode of operation.

Card ID Register
This register stores decimal values which are displayed on the LED's on the front panel. The lower 4 bits of this 8 bit value control the "Delay #" LED and the upper 4 bits control the "# of Delays" LED. The upper byte of this value is meaningless. Any set value greater than nine clears the LED.

This register and LED's are strictly for programming and diagnostics. They do not affect the independent operation of the card in any way.

Stop Address Register
This register stores the final value of the input address counter after the delay is stopped by the off trigger. It is used for diagnostics purposes and it is read only.

8k x 8 Dual Port Memories
The 15ns 8k dual port memories store information provided by the A/D and release the information at the proper times for a digital difference to be calculated. Left side inputs are loaded in to addresses determined by the Input Address Counter, and right side outputs are read from addresses determined by the Output Address Counters. The information from the A/D is inverted before entering the memory clocked by counter1, which makes subtraction at the output easier. The two memories should contain the exact same values at each memory location but opposite logic polarities. Thus, the only nonredundant information is stored in the upper 8 bits of a VXI memory read.

1k x 16 Dual Port Memory
The 1k x 16 Dual Port Memory is a cascade of two 1k x 8 memories which store the offset values between Output Address Counter 1 and Output Address Counter 2. Because the counters count only 13 bits, only the first 13 bits of the data are significant. The right port output +2 becomes the difference between the two counters. The +2 is needed, because it requires two clock pulses to take the 13 bit difference between the numbers. The right port address is determined by the Notch Delay Pointer Counter which is incremented every time the Change Notch Delay Counter resets.

The left side of the 1k x 16 Dual Port Memory is controlled exclusively by the VXIbus Interface. This allows the bus to read and write to the memory in stand-by and operational mode. Writing to a location while the operation requires a read from the same location will negate a write. Thus, when writing during operation mode, a read should be performed to compare the desired values to what is actualy in memory.

The digital delay card has two power-on modes: operating mode and stand-by mode. During operating mode, the digitizer writes its values to the dual port memories and the digital output is read from the memories according to the value of the counters; all VXI read and write functions to the 8k dual ports are locked out. During the stand-by mode, the 8k dual ports are controlled by the VXI interface, and the counters are locked out. All other registers and memories can be accessed by the VXI interface during both modes of operation. The VXI backplane triggers determine when the delay is in operating mode and when it returns to stand-by mode. They are configurable by adjusting the jumpers to the proper TTL trigger lines for starting and stopping the delay. The default setting is the TTLTRG0* line connected to the start trigger line and TTLTRG1* connected to the stop trigger line. When the delay card is triggered to stop, the value of Counter 1 is stored in the Stop Address memory location.

A/D
The Booster Digital Delay card uses an AD9012 100MSPS 8-bit analog to digital converter. Front end circuitry level shifts the input by -1 volt in order to bring the input level within the 0 to -2 volt input range of the A/D. The maximum input voltage before saturation is 1V and the minimum voltage is -1V. The front end circuitry has two pots which adjust the offset level (R108) and the input impedance (R118). Adjust the offset level pot until an AC sine wave input is centered in the memory. Adjust the input impedance pot for smallest return loss. There are two pots for the A/D not accessable with the cover on. These are the negative reference pot (R117) and the middle reference pot (R115) which keep the A/D negative reference at -2V and the mid reference at -1V respectively. There is a 13ns delay between the time the pickup clock signal enters the delay card and the time it actually samples the data at the A/D.

Input Address Counter
The Input Address Counter is a cascade of two 8 bit counters that point to the left port address of the 8k dual port memories. It is reset to zero before the card goes in to operating mode and counts at the rate dictated by the pickup clock. When the delay card is triggered to stop, the value of this counter is stored in the Stop Address register. An internal dip switch can change the direction of the count from up to down. The configuration of these dip switches is discussed later.

Output Address Counter 1
The Output Address Counter 1 is a cascade of four 4 bit counters that point to the right port address of one 8k dual port memory. It is reset to the value stored in the Bucket Delay Register before the card goes in to operating mode and counts at the rate dictated by the kicker clock. During stand-by mode, this counter may be disabled, so the VXIbus Interface can read and write directly to the memory. An internal dip switch can change the direction of the count from up to down. The configuration of these dip switches is discussed later.

Output Address Counter 2
The Output Address Counter 2 is a cascade of four 4 bit counters that point to the right port address of one 8k dual port memory. Its value is a fixed number of counts less than the Output Address Counter 1 value. This fixed number comes from the 1k x 16 Dual Port Memory and is updated every time the Change Notch Delay Counter resets. When the Notch Delay Counter resets, it sends a clock pulse which loads the current value of the Output Address Counter 1 value and the current value on the output of the 1k x 16 Dual Port in to registers. The difference between these values is loaded in to the Output Address Counter 2 and the counter continues to count from this new value at the rate dictated by the kicker clock. It takes two clock cycles to take the difference of these two 13 bit numbers, so the value loaded in the 1k x 16 Dual Port must be less than the desired offset value by two.

During stand-by mode, this counter may be disabled, so the VXIbus Interface can read and write directly to the memory. An internal dip switch can change the direction of the count from up to down. The configuration of these dip switches is discussed later.

Notch Delay Pointer Counter
The Notch Delay Pointer Counter is a cascade of two 8 bit counters that point to the right port address of the 1k x 16 Dual Port Memory. It is reset to zero before the card goes in to operating mode and counts every time the Change Notch Delay Counter resets. An internal dip switch can change the direction of the count from up to down. The configuration of these dip switches is discussed later.

Change Notch Delay Counter
The Change Notch Delay Counter is a cascade of two 8 bit counters that determine when the offset between Output Address Counter 1 and Output Address Counter 2 are updated. It is reset to the value set in the Change Notch Delay Register and counts at the rate dictated by the kicker clock. An internal dip switch can change the direction of the count from up to down. The configuration of these dip switches is discussed later.

When the counter reaches zero (or all ones for count up mode), it sends a signal to the Notch Delay Pointer Counter to count and resets itself to the value of the Change Notch Delay Register. It also sends a signal to latch the current value of the Output Address Counter 1 and the output of the 1k x 16 Dual Port in to the difference registers. After a two clock pulse delay, this difference is loaded in to Output Address Counter 2.

D/A and Digital Output
The digital output is the digital difference between the outputs of the right side of the two 8k x 8 Dual Port memories. This output is created by inverting the left inputs to one of the memories from the A/D, and then adding the right right inputs with a carry. The output has 9 bits of resolution, because the carry from the subraction is the new MSB. The D/A has 10 bits of resolution, but the LSB is tied low. It can convert at a rate of 400 MSPS. The D/A pot (R116) zeros out the DC offset on the output which should be terminated in to 50?.
Count Up/Down Configuration
All of the counters in the card can be configured for counting up or down using internal dip switches. This allows an extra degree of freedom for the programmer. In order to change the counting direction of the 8k Dual Port pointers, all of them must count in the same direction, and the ALU which provides the offset between the two output counters must be configured correctly. When counting up (default), the ALU subtracts the address from the offset, and the bucket delay is a negative number. When counting down, the ALU must add the address and the offset, and the bucket delay must be a positive number.

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