CAMAC C032 - Serial Memory Buffer

N. Lau
November 1, 1974

Table of Contents

• General Description
• CAMAC Functions
• Internal Memory Jumper Function F(14)A(0) and F(12)A(0)
• Front Panel
• Operating Description
• I/O Signals

^General Description

This single width module transfers data (duplex, serial) between two CAMAC interfaced computer systems or between a CAMAC interfaced computer system and a SWIC scanner. In the case of two computer systems, the 032 is used in pairs, one 032 being plugged into a CAMAC crate of each system, with the two modules physically interconnected by four 50 ohm coaxial cables; two data lines and two control lines. For the case of interfacing to the SWIC scanner only one 032 would be needed, it being plugged into a CAMAC crate of the computer system, with the module connected to the scanner by two data lines and two control lines.

Each module contains two 256 words x 16 bits memories, combined with suitable logic to interface inter-module serial data transfers with the parallel formatted CAMAC dataways. In addition, a front panel port interfaces the module to the MDCX channel so that the module can receive block transfers independent of the CAMAC dataway.

A software maskable LAM bit is set, following a time-out at the conclusion of a Receive DATA (RD) serial block-transfer to indicate that data is available to be read via the dataway. Software readable status provided for each memory includes content (binary word count) and "full" and "empty" flags.

There is a self test mode on the 032 which internally connects the R Data to the T Data port on the module. This mode allows field testing of the 032 module through any CAMAC system terminal.

^CAMAC Functions

^Internal Memory Jumper Function F(14)A(0) and F(12)A(0)

The purpose of function code F(14)A(0) is to internally "jumper" or "strap" the transmit data line and transmit request line to receive data line and receive ready line respectively within an 032 module.

This function facilitates the remote testing of an 032 module by allowing a write command and a read command to an 032 module without any interconnection physically to another module and without the need of someone to locate the module and physically jumper the internal memories.

F(14)A(0) also disables the front panel ports and I/O ports so that is will isolate itself from any external system that might try to write to or read from the 032 module while an internal self test is being performed. Any data written to an isolated 032 will not be accepted and data read will be all logic false except through the CAMAC dataway.

Because F(14)A(0) isolates the 032 module, it is designed to disable after approximately 200 milliseconds. After initiating an F(14)A(0), every subsequent F code beginning before the 200 millisecond timer has elapsed will restart the timer. This permits a self test of any length to be performed and prevents a test operator from negligently leaving the module disabled.

F(12)A(0) in an F code that will disable the internal jumper if for any reason the 200 millisecond F(14) is too long, such as an automated test procedure.

^Front Panel

^Operating Description

Each 032 contains two operationally independent static RAM memories [Designated F(16) and F(0)]. Data to be transferred from computer 1 to computer 2 enters the computer 1 F(16) memory via CAMAC dataway write commands [F(16)A(X)] or through the MDCX port.

Transmit block transfer is obsolete, ignore MDCX stuff

Data to be transferred from the experimenters 032 is accessed from the F(0) memory via dataway read commands [F(0)A(X)]. the MDCR (BTR) mode is a special case, wherein a block of data of known length may be set up for access by first requesting the 032 module's status using a F(1)A(0) command. This interrogation puts the word count content of both buffer memories on the dataway read lines. The frontend can then arrange to read the exact number of words from the F(0) memory via its MDCR (BTR) channel, which is under control of the crate controller. The crate controller determines when the F(0) memory id empty by a "no Q" response.

Intermodule transfers utilize a di-phase code, which transfers data at a one MHz bit rate. A transition exists at the beginning of each bit cell. If the bit in that 1 microsecond cell is zero, there is no transition in that cell. If the data is a 1 there is a transition in the cell. Thus when idling (i.e. sending all zeroes) the output signal is an approximately one MHz square wave. When all ones are sent the signal ix an approx. two MHz square wave.

^I/O Signals