C073 Block Transfer ControllerC073 Block Transfer Controller
Available Documentation
[DUCAR.DOC]CMC073.TXT CAMAC 073 OP CODES (RJD 8-8-90)
[DUCAR.DOC]CMC073.TXT BLOCK TRANSFER TESTING (RJD 9-24-84)
Note: Please see Ann Mason or Bob Ducar for more information.
CAMAC 073 OP CODES
All codes return module Q and X immediately unless otherwise noted. This module never asserts LAM.
F(0) A(0) Read Received Word Count --------- R16 - R1 ------------------------------- Received Word Count
F(0) A(1) Read Received Crate Address and Target Slot --------- R16 - R9 | R8 - R6 | R5 - R1 ---------------------------------------------- Crate Address 0 Target Slot
F(0) A(2) Read Desired Crate Address and Target Slot --------- for the Selective Listener Mode
R16 - R9 | R8 - R6 | R5 - R1 ---------------------------------------------- Crate Address 0 Target Slot
F(0) A(3) Read Received Block Transfer Word --------- R16 - R1 --------------------------- Received BT Word
Q is conditional for this operation. DRE must be true, TPC must be false, and data must be stored on board from the DRDY/DACK cycle. It is assumed that a BTRI cycle was executed prior to the first receipt of data.
F(1) A(0) Read BTR Status --------- R16 - R9 | R8 - R1 -------------------------- 0 BTR Status
R8: BTSLA BT Serial Line Active R7: BTRMOF BTR Memory Overflow (8K Words) R6: BTRFE BTR Frame Error R5: BTRTO BTR Timeout R4: BTTWC BT Terminated on Word Count R3: BTTNQ BT Terminated on No Q Count R2: BTTTO BT Terminated by TSCC Timeout R1: BTTBC BT Terminated by Command
F(6) A(0) Read Module Number --------- R16 - R9 | R8 - R1 ---------------------------- 0 49 Hex, 73 Dec
F(16) A(0) Generate Initialize to BTR (BTRI) ---------- Data are irrelevant. 250 nsec pulse.
F(16) A(1) Write Control Register ---------- W16 - W14 | W13 | W12 - W10 | W9 | W8 - W3 | W2 W1 --------------------------------------------------- 0 DRE 0 RALL 0 FM2 FM1
DRE: Data Ready Enable - Allows transfer of data from Receiver to Controller. RALL: Receive All Block Transfers - When RALL is false, the BTR is in selective listener mode. FM(0): One Word Mode FM(1): Two Word Mode FM(2): Packed Byte Mode FM(3): Not used
F(16) A(2) Write Desired Crate Address and Target Slot for ---------- the Selective Listener Mode.
W16 - W9 | W8 - W6 | W5 - W1 ---------------------------------------------- Crate Address X Target Slot
This operation will also generate a BTRI within the BTR.
F(16) A(3) Generate Initialize to BTR (BTRI) ---------- Data are irrelevant.
CMC073.TXT RJD 8-8-90
CMC073.TXT RJD 9-24-84
BLOCK TRANSFER TESTING
The following is some helpful information relative to testing of Block Transfer facilities. For these tests the Block Transfer Con- troller is not used, a CAMAC kluge controller is used in its place. The op codes for this controller are as follows:
CAMAC 073 OP CODES __________________
All codes return module Q and X immediately unless otherwise noted. This module never asserts LAM.
F(0) A(0) Read Received Word Count --------- R16 - R1 ------------------------------- Received Word Count
F(0) A(1) Read Received Crate Address and Target Slot --------- R16 - R9 | R8 - R6 | R5 - R1 ---------------------------------------------- Crate Address 0 Target Slot
F(0) A(2) Read Desired Crate Address and Target Slot --------- for the Selective Listener Mode
R16 - R9 | R8 - R6 | R5 - R1 ---------------------------------------------- Crate Address 0 Target Slot
F(0) A(3) Read Received Block Transfer Word --------- R16 - R1 --------------------------- Received BT Word
Q is conditional for this operation. DRE must be true, TPC must be false, and data must be stored on board from the DRDY/DACK cycle. It is assumed that a BTRI cycle was executed prior to the first receipt of data.
F(1) A(0) Read BTR Status --------- R16 - R9 | R8 - R1 -------------------------- 0 BTR Status
R8: BTSLA BT Serial Line Active R7: BTRMOF BTR Memory Overflow (8K Words) R6: BTRFE BTR Frame Error R5: BTRTO BTR Timeout R4: BTTWC BT Terminated on Word Count R3: BTTNQ BT Terminated on No Q Count R2: BTTTO BT Terminated by TSCC Timeout R1: BTTBC BT Terminated by Command
F(6) A(0) Read Module Number --------- R16 - R9 | R8 - R1 ---------------------------- 0 49 Hex, 73 Dec
F(16) A(0) Generate Initialize to BTR (BTRI) ---------- Data are irrelevant. 250 nsec pulse.
F(16) A(1) Write Control Register ---------- W16 - W14 | W13 | W12 - W10 | W9 | W8 - W3 | W2 W1 --------------------------------------------------- 0 DRE 0 RALL 0 FM2 FM1
DRE: Data Ready Enable - Allows transfer of data from Receiver to Controller. RALL: Receive All Block Transfers - When RALL is false, the BTR is in selective listener mode. FM(0): One Word Mode FM(1): Two Word Mode FM(2): Packed Byte Mode FM(3): Not used
F(16) A(2) Write Desired Crate Address and Target Slot for ---------- the Selective Listener Mode.
W16 - W9 | W8 - W6 | W5 - W1 ---------------------------------------------- Crate Address X Target Slot
This operation will also generate a BTRI within the BTR.
F(16) A(3) Generate Initialize to BTR (BTRI) ---------- Data are irrelevant.
Testing installed systems is most conveniently conducted at the console in the library area of the Main Control Room. A nearby crate hooked to the system under test is necessary. Tevatron and P-Bar can be tested from this location. Crate $19 may be moved to Switchyard or Booster for tests of those systems. Install the 073 module in the appropriate crate. Wire the BTR signal to the BTR Receiver chassis. Testing will be executed from the CAMAC test page (T98) in the following approximate sequence:
For the sake of this example; let us assume that the TSCC under test is in the Tevatron system and has address $A1, that the target slot is N4 (an 080 module), and that the 073 module is installed in crate $DC N8. Dial up the CAMAC test page and make sure you are on the proper node (24 for Tevatron).
1) A1 4 0 6 x x D Execute this CNAF to verify that your target
is alive and well. Notice the last word in
the extended status field (0806 for this ex-
ample), it will be used later.
2) DC 8 1 16 x x Writes control register in the BTR. Generally
run test with DRE true and RALL false. FM(0)
Data= 1000,1001, and FM(1) are advised. FM(2) can be confusing.
1002,110m, Therefore, Data usually equals 1000 or 1001 for
010m,000m. this instruction. Asserting RALL is useful if
the TSCC is not sending proper header or tailer.
3) DC 8 2 16 x x Writes Crate Address and Target Slot for selective
listener mode. Generally, tests should be done in
Data= A104 this mode. Remember that CA and N are in hex.
Remember also that this operation forces a BTRI.
4) A1 24 15 16 This instruction starts the Block Transfer at the
TSCC. Additional entries as follows:
Under ARB: Desired (CAMAC) Word Count in hex.
TSCC returns that many plus one.
1FFF is the maximum before BTRMOF
when in single word mode.
Under NQR: Enter Max No Q Retry number. 0 to
255 decimal. Fun to play with when
using an invalid code or empty slot.
Under DATA: Enter Target NAF. 0806 for this
example. This info comes from the
first instruction executed in this
sequence.
After this execution, it's all over. Observe idiot lights on the BTR front panel and execute any or all of the following for additional gratification.
5) A1 4 0 6 x x D If the block is big enough, an ARBCON error
should be returned here.
6) DC 8 0 0 x x D Reads the received word count. 1 more than
requested if in single word mode.
7) DC 8 1 0 x x D Reads received CA and N. A104 for this test.
8) DC 8 0 1 x x D Reads BTR Status. 0008 is returned for a
normal word count termination.
9) DC 8 3 0 x x D Reads received word. Do several of these if
the word count is low and you should see some
again & again no Q returns on this operation.
PALS DOCUMENTATION
module 07307b title ' CAMAC 073 TDH/RJD 8-2-90 ' 07307b device 'f153';
S1, S2, X, QD, BTRI pin 1,2,3,4,5; NA2, NA1, F16, RQ pin 6,7,8,9; CI, CW, CC, NC14, NC15 pin 11,12,13,14,15; NC16, NC17, NC18, NC19 pin 16,17,18,19;
H,L,X,Z = 1,0,.X.,.Z.; "Use standard PALASM operators @ALTERNATE equations
CC = NA2*/NA1*/F16*/S1 ;" N F(16) A(1) S1
/CW = /NA2*NA1*/F16*/S1 + " N F(16) A(2) S1
/NA2*/NA1*/F16*/S1 ;" N F(16) A(3) S1
/CI = NA2*NA1*/F16*/S1 ;" N F(16) A(0) S1
/RQ = /NA2*/NA1*F16*/S2*/QD*/X + " N F(0) A(3) S2
/BTRI;
"DESCRIPTION:
Decodes all function codes that include S1, S2, or pulsed signals
for the BTR Tests Module 073.
end 07307b
module 07308b title ' CAMAC 073 TDH/RJD 8-2-90 ' 07308b device 'f153';
N, A2, A1, QD, F16 pin 1,2,3,4,5; F4, F2, F1, F6A0 pin 6,7,8,9; PR, PW, F0A3, F1A0, F16A pin 11,12,13,14,15; NA1, NA2, Q, X pin 16,17,18,19;
H,L,X,Z = 1,0,.X.,.Z.; "Use standard PALASM operators @ALTERNATE equations
/Q = /N*A2*A1*F16*F4*F2*F1 +
/N*A2*/A1*F16*F4*F2*F1 +
/N*/A2*A1*F16*F4*F2*F1 +
/N*/A2*/A1*F16*F4*F2*F1*/QD +
/N*A2*A1*F16*F4*F2*/F1 +
/N*A2*A1*F16*/F4*/F2*F1 +
/N*A2*A1*/F16*F4*F2*F1 +
/N*A2*/A1*/F16*F4*F2*F1 +
/N*/A2*A1*/F16*F4*F2*F1 +
/N*/A2*/A1*/F16*F4*F2*F1;
/X = /Q + /N*/A2*/A1*F16*F4*F2*F1
/NA2 = /N*/A2 " N A(2) + N A(3)
/NA1 = /N*/A1 " N A(1) + N A(3)
/F16A = /N*/F16*F4*F2*F1 ;" N F(16) A(0-3)
/F1A0 = /N*A2*A1*F16*F4*F2*/F1 ;" N F(1) A(0)
/F0A3 = /N*/A2*/A1*F16*F4*F2*F1*/QD ;" N F(0) A(3)
/PW = /N*A2*/A1*/F16*F4*F2*F1 + " N F(16) A(1)
/N*/A2*A1*/F16*F4*F2*F1 ;" N F(16) A(2)
/F6A0 = /N*A2*A1*F16*/F4*/F2*F1 ;" N F(6) A(0)
/PR = /N*A2*A1*F16*F4*F2*F1 + " N F(0) A(0)
/N*A2*/A1*F16*F4*F2*F1 + " N F(0) A(1)
/N*/A2*A1*F16*F4*F2*F1 ;" N F(0) A(2)
"DESCRIPTION:
Decodes all function codes not including S1, or S2 and provides
Q and X for the BTR Tests Module 073
end 07308b
