The primary function of the 080 Module is to provide interface from the CAMAC environment to the ZILOG parallel interface controller (PIO). The PIO is operated in the bi-directional mode (Mode 2). Data are one byte wide (8 bits) and are wired to the A port. Port B must be set to the bit mode (Mode 3). The A handshake lines are used for data transfers from the PIO to the CAMAC module. The B lines are used for data transfers from the CAMAC module.
In addition to facilitating communications with a PIO, the module also provides one byte of static control lines and capability of reading one byte of external static input status. Four of the control lines are assigned to block transfer, on, enable, and time-out functions.
Communications with the PIO are initiated only by the host computer via the CAMAC facility. All communications are preceded by the transmission of a four byte header to the PIO which serves to classify the transaction and to verify the integrity of the data path.
Data transmissions to the PIO are buffered by a 192 byte FIFO. Data transmissions from the PIO are buffered by a separate 64 byte FIFO. All data transmissions are in multiples of there bytes, thus using the full capability of the CAMAC data path.
The LAM line is restrictively used to indicate device associated fault conditions. One on-board fault condition is wired to the LAM generator. Additional fault conditions may be wire to to the LAM generator from the external static input status.
The full potential of the 080 module is probably best realized by connections to two separate PIOs.
The following CAMAC function codes are accepted by the module. All of these codes return X. Return of Q is conditional for some of the codes.
F(0)A(0) | Read output register, non block transfer
reads. Q is conditional |
F(1)A(0) | Read module status. Always Q |
F(4)A(0) | Read output register, block
transfer reads. Q is conditional |
F(6)A(0) | Read module number: $50 hex Always Q |
F(9)A(0) | Clear module EXPHDR is set true Always Q |
F(16)A(0) | Write data to FIFO
Q is conditional |
F(17)A(0) | Writes bottom nibble of the control
register. Always Q |
F(20)A(0) | Write header register and
initiate a four byte transfer to the PIO. Also clears FIFOs
Q is conditional |
F(22)A(0) | Writes additional header information to the PIO
in groups of three bytes. Q is conditional |
F(24)A(0) | Resets control register bit 5 (Disable
Mode). Always Q |
F(26)A(0) | Sets control register bit 5 (Enable
Mode). Always Q |
F(28)A(0) | Resets control register bit 6 (Off
Mode). Always Q |
F(30)A(0) | Sets control register bit 6 (On Mode) Always Q> |
R16: | ES7 | These static status lines from the associated PIO subsystem are assigned by the user. |
R15: | ES6 | |
R14: | ES5 | |
R13: | ES4 | |
R12: | ES3 | The convention of good status=1 should be maintained. Any of these lines can be switched into the LAM generator |
R11: | ES2 | |
R10: | ES1 | |
R9: | ES0 |
Set CR7: | F(20)A(0)*W24. In other words, values of HR byte 1 from $80 to $FF hex will set CR7. |
Reset CR7: | F(20)A(0)*!W24. In other words, values of HR byte 1 from $00 to $7F hex will reset CR7. Also reset by module CLEAR |
F(0) Operation: | The F(0) operation receives a Q response iff ORRDY is true and CR7 and TTO are false. |
F(4) Operation: | The F(4) operation receives a Q response iff ORRDY and CR7 are true and TTO is false. |
F(16) Operation: | The F(16) operation receives a Q response iff TTO, ORRDY, ORSEQ, and CR7 are false. Additionally FIFOIR must be true and EXPHDR must be false. |
F(20) Operation: | The F(20) operation receives a Q response iff the logic states are false for TPEND, TTO, and ORRDY. |
F(22) Operation: | The F(22) operation is subject to the same conditions as the F(16) operation, except that the state or CR7 is not checked. |
HINT: | Hint is either a 2uSec pulse or a level indicating the module's acceptance of the F(20) operation which loads the header register. /HINTACK is an active low signal which resets the HINT level. If /HINTACK is grounded, HINT will always be a 2uSec pulse. An onboard patching option allows the transfer of the first byte of the four byte header 2uSec after the rising edge of HINT or at the falling edge of HINT. Transmission of the 4th byte of the header will always cause HINT to be reset. |
/AIP | A static line buffered from patch line P1 of the CAMAC dataway. A logic 1 state indicates that a machine abort is not in progress. |
This module uses a 36 pin VIKING card-edge connector. Position allocations are as follows:
1L | BP/!AIP |   | 1R | COMMON |
2L | BTR |   | 2R | ARDY |
3L | ON |   | 3R | COMMON |
4L | ENABLE |   | 4R | !ASTR |
5L | TRANS TO |   | 5R | COMMON |
6L | CR3 |   | 6R | BRDY |
7L | CR2 |   | 7R | COMMON |
8L | CR1 |   | 8R | !BSTR |
9L | CR0 |   | 9R | COMMON |
10L | HINT |   | 10R | !HINTACK |
11L | D7 |   | 11R | ES7 |
12L | D6 |   | 12R | ES6 |
13L | D5 |   | 13R | ES5 |
14L | D4 |   | 14R | ES4 |
15L | D3 |   | 15R | ES3 |
16L | D2 |   | 16R | ES2 |
17L | D1 |   | 17R | ES1 |
18L | D0 |   | 18R | ES0 |
CABLE END TRIM TRIO G6F22-38SNE | SIGNAL | CAMAC I/O 36 POSITION VIKING |
---|---|---|
A | COMMON | 1R, 3R, 5R, 7R, 9R |
B | D7 (MSB) | 11B |
C | D6 | 12L |
D | D5 | 13L |
E | D4 | 14L |
F | D3 | 15L |
G | D2 | 16L |
H | D1 | 17L |
J | D0 (LSB) | 18L |
K | BTR | 2L |
L | ON | 3L |
M | ENABLE | 4L |
N | TRANS TO | 5L |
P | CR3 | 6L |
R | CR2 | 7L |
S | CR1 | 8L |
T | CR0 | 9L |
U | ES7 | 11R |
V | ES6 | 12R |
W | ES5 | 13R |
X | ES4 | 14R |
Y | ES3 | 15R |
Z | ES2 | 16R |
a | ES1 | 17R |
b | ES0 | 18R |
c | ARDY | 2R (COAX) |
d | !ASTR | 4R (COAX) |
e | BRDY | 6R (COAX) |
f | !BSTR | 8R (COAX) |
g | HINT | 10L (COAX) |
h | !HINTACK | 10R (COAX) |
j | BP/!AIP | 1L (COAX) |
k | SPARE 1 | -- (COAX) |
m | SPARE 2 | -- (COAX) |
n-s | NOT USED | -- |