Fermilab
Serial Crate Controller

C. W. Needles, W. R. Knopf
RD/Controls

June 30, 1989

I. INTRODUCTION

The Beamline Serial Controller BSC24/25 is a triple ported Serial CAMAC Crate Controller for use in the Fermilab Beam Lines and Experimental Areas. The controller consists of a module occupying two slots; the Controller Station (slot 25) and a Normal Station (slot 24). It is the interface between the serial transmission system and the parallel CAMAC dataway.

In the normal (serial) mode of operation the crate controller monitors the serial transmissions. If a match in the crate address field is detected, the slot address, sub-address and function code as well as any associated data is read from the serial bitstream, converted to parallel and stored in registers. A CAMAC dataway cycle is then executed and module responses such as Q, X, and data latched in registers. A reply message is assembled from this data and shifted out on the serial return link.

Access to crate controller functions is also provided via a byte-wide data path through a front panel connector to allow for local access; this feature provides execution of CAMAC cycles by a local master. Full support of an Auxiliary Controller Bus (ACB) allows the use of multiple controllers in a crate. Arbitration is of the R/G type, that is, serial arbitration through a Grant In / Grant Out daisy chain. In order to grant the controller access to the dataway a coaxial jumper from the front panel REQUEST to the GRANT IN Lemo connector has to be provided.

Secondary functions supported by the controller are:

A Tevatron Clock decoder circuit and
monitoring of temperature and the main crate voltages (+- 6 VDC), with provisions for remote readback.

II. THE SERIAL INTERFACE

a) The Serial Protocol:

The present serial communications protocol consists of 70 bits transmitted (transmit data) from the master to a crate controller and 35 bits in the response message (receive data) generated by the crate controller.

Start bit ( 1 bit ) - always '1', start of message
Crate address ( 8 bits)
Multi crate ( 1 bit ) - not used
Branch ( 7 bits)
- D6-D4 = not used
- D3 = No-Q retry bit
- D2 = Aux. controller lockout
- D1 = Initialize - not used
- D0 = Graded LAM - not used
Slot number ( 5 bits)
Sub-address ( 4 bits)
Function code ( 5 bits)
Parity ( 1 bit ) - command parity, odd
Timing ( 2 bits) - 2 usec for Control or Read cycle

The data and status stream is common to both transmitted data as well as received data with the exception of the start bit.

Start bit ( 1 bit ) - always '1', part of response only
Write/Read data (24 bits) - filled by linkdriver on write, by crate controller on read.
Parity ( 1 bit ) - data parity, odd
Timing ( 1 bit ) - 2 usec for Write cycle
Timing/status ( 1 bit ) - timing on transmitted data,
Inhibit status on returned data
Status word ( 5 bits) - Status from dataway cycle
- D5 = Q-response of last dataway cycle
- D4 = OR of the LAM's
- D3 = X-response of last dataway operation
- D2 = Dataway Arbitration Time Out.
- Local/Remote on old controller.
- D1 = Parity error on the incomming data
Parity ( 1 bit ) - Status parity
End bit ( 1 bit ) - End of message

Serial receive and transmit lines are separate clock and data signals, using differential drivers and receivers (RS-485).

b) Controller Addressed Function Codes:

In addition to executing CAMAC commands on the dataway the crate controller responds to the following commands:

Read Crate volt, temp N(28) * F(0) * A(0) Q=0 X=1
Generate Dataway Z N(28) * F(26) * A(8) Q=0 X=1
Generate Dataway C N(28) * F(26) * A(9) Q=0 X=1
Read Crate LAM Status N(30) * F(0) * A(0) Q=1 X=1
Remove Dataway I N(30) * F(24) * A(9) Q=0 X=1
Set Dataway I N(30) * F(26) * A(9) Q=0 X=1

Any commands not handled by the controller will return status with Q=0 and X=0; all valid Controller commands return X=1.

Note: Only functions 'Generate Z' and 'Generate C' will result in a dataway cycle.

c) The No-Q Retry Function:

Local No-Q retries are supported by the controller; if the No-Q retry bit is set to a 1 and the Camac cycle returns a Q = 0 response, the controller will execute up to three more dataway cycles to get a Q = 1 from the addressed module. After this the controller will return status with Q indicating the response of the last operation. The time between retries is set to 10 microseconds. No-Q retries are available on the serial interface only.

d) The ACC Lockout:

The Lockout bit, if set to 1, reserves the GRANT OUT after the dataway cycle to prevent the Auxiliary Crate Controller from accessing the CAMAC dataway. This condition will remain in effect until on of two events take place:

A serial command is received with the lockout bit set to'0' or
A watchdog timer times out. ( 5 ms).

e) Bus Access Time Out:

There is a time limit for accessing the CAMAC bus. If no access is granted within 50 microseconds the controller will return status, with the bus time out bit set and a Q = 0.

Note: The Initialize command ( N(28)*F(26)*A(8) ) will access the dataway even if the arbitration is locked; this allows for remote reset of an auxiliary controller locking up the dataway

The Inhibit is set on power up and can only be cleared by a CAMAC function to the crate controller ( N(30)*(F26)*(A9) ).

Module Demands (LAM requests) are returned as a 24-bit LAM status word via N(28)*F(0)*A(0). A data bit = 1 corresponds to a LAM request from that particular slot, i.e R1 = slot 1, R2 = slot 2 etc.

III. SECONDARY FUNCTIONS:

a) Parallel port.

This front panel connector (J3) allows reading and writing a set of registers in the crate controller to facilitate access to Camac functions. Data transfer is byte wide; address and control lines determine the particular register accessed (see mapping below). Access to the dataway is granted on a lower priority basis than the serial access. Addresses and functions of these dual ported register are as follows:

Reg Address Bus Data Bus Data
BA8 BA4 BA2 BA1 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 L L L L W24 W23 W22 W21 W20 W19 W18 W17 Write Data
1 L L L H W16 W15 W14 W13 W12 W11 W10 W9 " "
2 L L H L W8 W7 W6 W5 W4 W3 W2 W1 " "
3 L L H H A8 A4 A2 A1 A Address
4 L H L L F16 F8 F4 F2 F1 F Command
5 L H L H N16 N8 N4 N2 N1 N Station
6 L H H L L-O Command
7 L H H H ----ANY VALUE---- Trigger
8 H L L L P-E 1 1 X NoB Q OrL Par Status Reg.
9 H L L H R24 R23 R22 R21 R20 R19 R18 R17 Read Data
10 H L H L R16 R15 R14 R13 R12 R11 R10 R9 " "
11 H L H H R8 R7 R6 R5 R4 R3 R2 R1 " "
12 H H L L

Reg	Address Bus	Data Bus	Data
0	L	L	L	L	W24	W23	W22	W21	W20	W19	W18	W17	Write Data
1	L	L	L	H	W16	W15	W14	W13	W12	W11	W10	W9	" "
2	L	L	H	L	W8	W7	W6	W5	W4	W3	W2	W1	" "
3	L	L	H	H		A8	A4	A2	A1	A Address
4	L	H	L	L		F16	F8	F4	F2	F1	F Command
5	L	H	L	H		N16	N8	N4	N2	N1	N Station
6	L	H	H	L		L-O		Command
7	L	H	H	H	----ANY VALUE----	Trigger
8	H	L	L	L	P-E	1	1	X	NoB	Q	OrL	Par	Status Reg.
9	H	L	L	H	R24	R23	R22	R21	R20	R19	R18	R17	Read Data
10	H	L	H	L	R16	R15	R14	R13	R12	R11	R10	R9	" "
11	H	L	H	H	R8	R7	R6	R5	R4	R3	R2	R1	" "
12	H	H	L	L

For proper synchronization it is recommended that register 8 be loaded with 0xFF before executing a Camac cycle (writing to register 7 initiates the request to the crate controller to start the cycle). When the crate controller has completed the dataway cycle and returned data, register 8 will then contain a value other than 0xFF.

b) Clock decoder circuit.

This circuit converts a Manchester encoded clock (10 MHz Tevatron clock) to a local TTL level clock and data output. These signals are distributed via the P1 (clock) and P2 (data) patch lines to all Normal Stations. P1 is the clock signal, centered in the data so that either clock edge can be used, P2 is data having positive true logic. These signals are driven on the dataway by a 3-state line driver ('ALS541).

(Note: The TEV clock in the idle state transmits 1's, with a 0 defined as the start bit).

To remove these signals from the patch lines on the dataway remove U20 from the socket.

c) Crate Monitor:

Three 8-bit A/D converters provide monitoring of temperature and main crate supply voltages ( +6VDC, -6VDC ). They are read back as a 24-bit packed word with an N(28)*F(0)*A(1). This function is available for the serial interface only.

Crate Temperature (R24-R17) - 0 to 333 degrees K.: (0 to 0xFF unsigned; this converts into 1.3 degrees / bit).
-6 VDC Crate Power (R16-R9) - A/D input range = -10 to +10 VDC.: (0 to 0xFF unsigned number).
+6 VDC Crate Power (R8 -R1) - A/D input range = 0 to +10 VDC.: (0 to 0xFF unsigned number).

d) Dataway Access Arbitration:

The Request/Grant protocol used requires two signals from the auxiliary controller bus and two on the front panel. These are Request (REQ), Request inhibit (RI), Grant-out and Grant-in. The REQ is bussed to each Controller via the Auxiliary Controller Bus (ACB) and is accessible through a front panel connector at each controller; the Grant signal, which is daisy-chained, that is,the Grant-out of one controller is connected to the Grant-in of another controller by front panel connectors; and the Request Inhibit signal which is also bussed on the ACB. Signal definition:

RQ = Request: signal on ACL bus and front panel LEMO. Generated by controller requesting dataway.
Not asserted if other controller asserts RI.
Removed when GRANT IN is asserted.
RI = Request Inhibit: signal on ACL bus. Generated by requesting controller in response to asserting RQ and receiving GRANT IN. Held until dataway cycle is completed. The CC places the encoded N lines onto the dataway for the duration of RI.
GI = Grant In: signal on a front panel LEMO. In the CC this signal is jumpered to the RQ to give the controller the highest priority.
GO = Grant Out: signal on a front panel LEMO. Removed by CC when generating a request or if the GI line is de-asserted.

I.C. U38 is a state machine that handles the arbitration, lock out and arbitration time out. A timer chip (U44) is employed to prevent the BSC from locking up trying to gain access to the Camac dataway while an auxiliary controller has control.

Arbitration States:

A dataway cycle request begins with the crate controller asserting BRQ25.

A) Taking control of the dataway:

De-assert GO
Generate GI if RI is de-asserted.
Assert RI if RI is de-asserted.
De-assert RQ.

B) Releasing control of the dataway:

De-assert RI line (if no lockout).

IV. CIRCUIT OPERATION AND DESCRIPTION.

All crate controller operations are implemented in a synchronous state machine. The center of this circuit is an erasable, progammable Stand Alone Micro sequencer (SAM), an Altera EPS448 (slot 25 U1), thus allowing definition of all controller operations via an assembly language program. This program listing is included to aid in the understanding of the module functions.

1. RECEIVE SECTION.

The incoming serial clock and data are monitored for a start bit ('1); this will initiate a serial shift-in of the first byte, the crate address. When the full count is reached, the address is compared against the address switch setting and a flag (MYSAM) is raised on a match. This is a signal for the SAM to start a serial cycle. The bit count of each successive word is loaded by the SAM into U4, causing a ready signal (BYTE) as soon as the received number of bits reaches this count. The parallel data is then strobed into the appropriate register (F, N, A, or data registers) in preparation for a Camac dataway cycle.

Control bits for No-Q retries and arbitration lockout are latched in U13 and U38 respectively for later use. Odd data parity is monitored on the incomming data and the Camac cycle is aborted on a control parity error, that is, no actual dataway cycle takes place. The returned status word contains the parity error flag.

Function code bits F8 and F16 determine if a read, control, or write cycle is requested. For read and control cycles the actual dataway cycle is initiated as soon as the control functions are received, for write cycles the following 24 bits of data are loaded into the write data buffers before a dataway cycle is initiated.

Dataway access arbitration is then requested by the SAM, and if the arbiter (U38) sends a grant signal the BUSY signal is asserted for one microsecond. A hardware counter (slot 24 U11) generates the necessary signals such as S1, S2, and strobe and enable control signals for the registers to perform a dataway cycle. The state of the dataway read lines and the Q and X responses are latched during S1 strobe time. If the lockout bit was not set and QOUT signals that no retries are necessary, the request for dataway access is now de-asserted. A retry counter, preset to a count of three during idle time (no serial I/O in progress), the latched state of the No-Q retry bit and the actual Camac Q response are used to determine if a request for another dataway cycle should be generated (slot 25 U13, QOUT).

Status lines NS0 and NS1 define the type of cycle to perform as decoded from the N-lines:

NS1 NS0 Function

0 0 Standard dataway request, 0 < N < 25.
0 1 N = 28
1 0 N = 30
1 1 No Dataway Cycle; generated by all non-recognized f unctions. Return status Q = 0, X = 0.

NS1	NS0	Function
0	0	Standard dataway request, 0 < N < 25.
0	1	N = 28
1	0	N = 30
1	1	No Dataway Cycle; generated by all non-recognized f unctions. Return status Q = 0, X = 0.

2. TRANSMIT SECTION.

The transmit section is comprised of the register address decoder U13, the sequence controller U21, and the serial shift register U16.

The sequence is initiated by the SAM loading the response data in parallel by selecting the proper register address and starting the shift-out sequencer. This sequencer requests the next byte by asserting NBYTE once a byte has been shifted out. The first byte load command de- asserts NBYTE and starts the transmit operation.Signals between slot 24 and slot 25 are passed via a 34 connector pin and socket (J3) arrangement, thus allowing separation of the boards for troubleshooting and repair through the use of a flat ribbon cable.

V. FRONT PANEL CONNECTORS AND INDICATORS.

a) Crate Address switch.

The 8 bit DIP switch on the module's front panel selects the crate address. The eight switches represent a binary number from 0 to 255. The MSB is on the top; ON (right) represents a 0 and OFF (left) represents a 1.

b) LEMO Connectors.

LEMO connectors for Request In, Grant In and Grant Out are provided for Auxiliary Crate Controller support. Request In is an open-collector signal with the pull up resistor provided in the crate controller.

The front panel Request signal output of the crate controller is normally connected to its front panel Grant-in signal input, thus granting it the highest priority. The front panel Grant-out signal is then connected to the front panel Grant-in signal input of the next highest priority auxiliary controller.

c) Front Panel LED's.

PWR = 5 Volt power monitor

The following displays are stretched:
EXT ACC = Auxiliary Crate Controller access
LINK BUSY = Serial Transmit Monitor
PR REQ = Parallel access request
CRATE ACC = Crate number match
B* = Dataway Busy
B = Crate Controller Busy
X = Dataway X, latched by S1 strobe
Q = Dataway Q, latched by S1 strobe

d) 40-pin connector for local access / control.

This connector is the byte-wide parallel interface to the crate controller providing local access to CAMAC functions.

It carries all signals on odd pin numbers 1 - 27, 29 - 29 unused, with even numbered pins connected to ground (pin 1 at the bottom).

PIN# SIGNAL DESCRIPTION

29 BQ3/ Data Strobe
27 BA8 Address register, MSB
25 BA4 Address register
23 BA2 Address register
21 BA1 Address register, LSB
19 BDS/ Device select
17 BR/W Read/write status line
15 DB7 Data bit, MSB
13 DB6 Data bit
11 DB5 Data bit
9 DB4 Data bit
7 DB3 Data bit
5 DB2 Data bit
3 DB1 Data bit
1 DB0 Data bit, LSB

PIN#	SIGNAL	DESCRIPTION
29	BQ3/	Data Strobe
27	BA8	Address register, MSB
25	BA4	Address register
23	BA2	Address register
21	BA1	Address register, LSB
19	BDS/	Device select
17	BR/W	Read/write status line
15	DB7	Data bit, MSB
13	DB6	Data bit
11	DB5	Data bit
9	DB4	Data bit
7	DB3	Data bit
5	DB2	Data bit
3	DB1	Data bit
1	DB0	Data bit, LSB

VI. REAR I/O CONNECTOR PIN ASSIGNMENTS.

a) Slot 24: 36-pin Viking connector:

1L	TEV Clock -	1R	TEV Clock +
15L	Receive Data -	15R	Receive Data +
16L	Receive Clock -	16R	Receive Clock +
17L	Transmit Data -	17R	Transmit Data +
18L	Transmit Clock -	18R	Transmit Clock +

b) Slot 25: Auxiliary Controller Bus (ACB).

The standard ACB is available in slot 25; a circuit board converts the 36-pin Viking card edge connector (mounted to the crate) to the 40- pin ACB connector as defined in ANSI/IEEE Std 675-1982.

SAM Program Listing.

Each Instruction, including a 3-way branch, is executed in one clock cycle = 200 ns.

REVISION D
EPS448
Serial Crate Controller BSC25-U1
PART: EPS448

INPUTS:
% Input Sense Lines in descending order %
% Each signal has two inputs connected via a multiplexer. %
% Group selection is determined by output line 'INP_SEL'. %

ARBGNT, I6, I5,
I4, I3, SHORT
CRATE, BYTE_READY,

OUTPUTS:
% Output Control Lines. %
% Labels are assigned sequentially in descending order as %
% required by the assembler %

ARBREQ, A4, A2, A1, WRRA1, RDRA1,
PRGNT, SLOT25, RCVCLR, BUSY, INP_SEL,
READREG, WRTREG, REG4, REG2, REG1,

MACROS:
% These bitpatterns define the state of the output lines. %
% A 16-bit value is generated by concatenating several patterns %

IDLE = "1111111111111111"
TIMEOUT = "1111111101111111"

% Address lines for various register selection %
% Used in conjunction with R/W control and function select %
SRLATCH = "111"
QLCONT = "011" %WRITE Q AND LOCKOUT BITS%
TBREG = "000"
SLREG = "101"
SMREG = "100"
SHREG = "011"
DLREG = "010" %CAMAC REGISTERS%
DMREG = "001"
DHREG = "000"
NREG = "101"
FREG = "100"
AREG = "011"
RSREG = "111"
WRT_PR = "110"
% Read/Write control lines %
READREG = "01"
WRTREG = "10"
WATREG = "11"
GATE = "111"
% Function Select %
RGATE = "110" % ENABLE READ INPUT %
BLANK = "11111111"
FILL = "1111"
PRSLOT24 = "0111"
SLOT24 = "1101"
RSLOT24 = "1111"
PWSLOT24 = "1011"
SLOT25 = "1100"
RSLOT25 = "1110"
PRSLOT25 = "0110"
PWSLOT25 = "1010"

% Bit count (n-1), loaded into serial shift-in register; %
% Causes BYTE_READY to go active when count is reached %
CP_COUNT = "1010"
F_COUNT = "1100"
A_COUNT = "1011"
N_COUNT = "1100"
S_COUNT = "1001"
MSFILL = "1111"
FLCONT = "1111"
DISCARD = "1100"

BUSREQ = "0111"
CAMAC = "10011111"
SETX = "10111111"
TESTIN = "11011111"
RDBYTE = "1111111111011111"
CLRPAR = "1111001111111111"

EQUATIONS:

CRATEZ = /I4 * I3 * /SHORT;
CRATEC = I4 * /I3 * /SHORT;
READSTAT = I4 * I3 * /SHORT;
WHAT = I5 * I6;
STCAMAC = /I5 * /I6;
N30 = I5 * /I6;
INHIBIT = I4 * /I3 * SHORT 
+ /I4 * I3 * SHORT;

%********************************************%
% Start of MAIN program loop %
%********************************************%

PROGRAM:

% ---- BOOT STATE ----%

OD: [ IDLE ] CONTINUE;

% Power up clear; generate BZ after wait of 1 ms. %
[ IDLE ] LOADC 20D;
PWRWAIT: [ IDLE ] PUSHLOADC 255D; % wait for power to come on %
LPWAIT: [ IDLE ] LOOPNZ LPWAIT;
[ IDLE ] POPC;
[ IDLE ] LOOPNZ PWRWAIT; % output Busy for the Z of crate %
[ IDLE ] LOADC 5D;
ZPWRON: [ BLANK CAMAC ] LOOPNZ ZPWRON;

% clear PR_REQ at power up %
GETRDY: [CLRPAR] LOADC 254D;
WATRDY: [IDLE] LOOPNZ WATRDY;

%Test if receiver is busy; when not busy load crate COUNT=8 %
READY: IF /I6 THEN [IDLE] JUMP RCVBSY;
ELSE [IDLE] JUMP START;

% Test for parallel access %
RCVBSY: IF I4 THEN [IDLE] CALL PRLOAD;
ELSE [IDLE] JUMP READY;

% On return from parallel stay in wait loop %
PRSTRT: [IDLE] JUMP READY;

% Load crate COUNT=8 %
START: [FLCONT SLOT25 SRLATCH WRTREG SRLATCH] CONTINUE;

% Wait for start bit to turn receiver on %
STBYTE: IF /I5 THEN [IDLE] JUMP SERST;
ELSEIF I4 THEN [IDLE] CALL PRLOAD; %TEST FOR PARALLEL ACCESS%
ELSE [IDLE] JUMP STBYTE;

RESTRT: [IDLE] JUMP STBYTE;

% Wait for incomming serial crate address byte; %
% Check for match with address switch. %
SERST: [IDLE] CALL NBYTE;
[DISCARD SLOT25 SRLATCH WRTREG SRLATCH] CONTINUE;
[DISCARD SLOT25 BLANK] CONTINUE;
IF CRATE THEN [DISCARD SLOT25 BLANK] JUMP READY;
ELSE [DISCARD SLOT25 BLANK] CONTINUE;
[IDLE] CALL WBYTE; 

% read 5 bits (branch) and discard %
[IDLE] CALL NBYTE;
[DISCARD SLOT25 SRLATCH WRTREG SRLATCH] CONTINUE;
[IDLE] CALL WBYTE;

% Read 5 bits, latch lock bit (D2) and No-Q retry bit (D3) for later use %
% Set bit count to 5 (N_COUNT) to receive Slot Number %
[IDLE] CALL NBYTE;
%write No-Q retry & Lock-out%
[ N_COUNT SLOT25 SRLATCH WRTREG QLCONT] CONTINUE;
[IDLE] CALL WBYTE;

% Read 5 bits of Slot number (N) and write into N-register %
% Set bit count to 4 (A_COUNT) to receive subaddress %
[IDLE] CALL NBYTE;
[ A_COUNT SLOT25 SRLATCH WRTREG SRLATCH] CONTINUE;
[ A_COUNT SLOT25 GATE WRTREG NREG] CONTINUE;
[IDLE] CALL WBYTE;

% Read 4 bits of Subaddress (A) and write into A-register %
% Set bit count to 5 (F_COUNT) to receive function code % 
[IDLE] CALL NBYTE;
[ F_COUNT SLOT25 SRLATCH WRTREG SRLATCH] CONTINUE;
[ F_COUNT SLOT24 GATE WRTREG AREG] CONTINUE;
[IDLE] CALL WBYTE;

% Read 5 bits of function code (F) and write into F-register %
% Set bit count for command parity detect %
[IDLE] CALL NBYTE;
[ F_COUNT SLOT24 GATE WRTREG FREG] CONTINUE;
[ F_COUNT SLOT25 SRLATCH WRTREG WRT_PR] CONTINUE;
[ CP_COUNT SLOT25 SRLATCH WRTREG SRLATCH] CONTINUE;
[IDLE] CALL WBYTE;

[IDLE] CALL NBYTE; 
[ FLCONT SLOT25 SRLATCH WRTREG SRLATCH] CONTINUE;
[ FLCONT SLOT25 GATE WRTREG TBREG] CONTINUE;
[IDLE] CALL WBYTE;

% Test for parity error; quit if there is one and return status %
IF /I3 THEN [ IDLE] JUMP RDCAMAC;
ELSE [IDLE] CONTINUE;

% Test if CAMAC Read or Control cycle; if true do dataway cycle %

IF /SHORT THEN [ IDLE ] JUMP DATAWAY;
ELSE [IDLE] CONTINUE;

% We get here if it is a CAMAC write cycle; strobe write data into registers
% 
[IDLE] CALL NBYTE;
[ FLCONT SLOT25 SRLATCH WRTREG SRLATCH] CONTINUE;
[ FLCONT SLOT24 GATE WRTREG DHREG] CONTINUE;
[IDLE] CALL WBYTE;

[IDLE] CALL NBYTE;
[ FLCONT SLOT25 SRLATCH WRTREG SRLATCH] CONTINUE;
[ FLCONT SLOT24 GATE WRTREG DMREG] CONTINUE;
[IDLE] CALL WBYTE;

[IDLE] CALL NBYTE;
[ FLCONT SLOT24 GATE WRTREG DLREG] CONTINUE;
[ FLCONT SLOT25 SRLATCH WRTREG WRT_PR] CONTINUE;
[ CP_COUNT SLOT25 SRLATCH WRTREG SRLATCH] CONTINUE;
[IDLE] CALL WBYTE;

[IDLE] CALL NBYTE;
[ S_COUNT SLOT25 SRLATCH WRTREG SRLATCH] CONTINUE;
[ S_COUNT SLOT25 GATE WRTREG TBREG] CONTINUE;
[IDLE] CALL WBYTE;

% Test for data parity error and quit if there is one and return status %
IF /I3 THEN [ IDLE] JUMP RDCAMAC;
ELSE [IDLE] CONTINUE;

[IDLE] CALL NBYTE;
[BUSREQ SLOT25 GATE WRTREG SRLATCH] CONTINUE;
[IDLE] CALL WBYTE;

% Test if crate controller addressed command %
% or unimplemented function code %

DATAWAY: [BLANK TESTIN] CONTINUE;

CAMACT: IF WHAT THEN [ IDLE] JUMP RDCAMAC;
% Separate into bus cycle or local status read commands %
ELSEIF STCAMAC THEN [ BUSREQ FILL BLANK ] CALL GETBUS;
ELSEIF N30 THEN [ BLANK TESTIN ] JUMP RDLAM;
ELSE [ BLANK TESTIN] JUMP RDSTATS;

%------ Read the CAMAC 24-bit read lines and status register -------%

RDCAMAC: [RDBYTE] CALL RBYTE;
[FILL RSLOT24 RGATE READREG DHREG] CONTINUE;
[RDBYTE] CALL RWBYTE;

[RDBYTE] CALL RBYTE;
[FILL RSLOT24 RGATE READREG DMREG] CONTINUE;
[RDBYTE] CALL RWBYTE;

[RDBYTE] CALL RBYTE;
[FILL RSLOT24 RGATE READREG DLREG] CONTINUE;
[RDBYTE] CALL RWBYTE;

[RDBYTE] CALL RBYTE;
[FILL RSLOT25 RGATE READREG RSREG] CONTINUE;

RECVWAT: [IDLE] LOADC 65D;
% WAIT for end of serial receive (3.25us) %
LOPWAT: [IDLE] LOOPNZ LOPWAT;

ENDSER: [IDLE] JUMP READY;

%***************************************************************%
% This is the end of the MAIN program loop. %
% The following functions are either CALLED or JUMPED into, %
% in which case they need a known jump address for return. %
% This is normally the start of MAIN (JUMP READY) %
%***************************************************************%

% Read LAM register %

RDLAM: [BUSREQ FILL BLANK] CALL GETBUS;

[A [RDBYTE] CALL RBYTE;
[FILL RSLOT25 RGATE READREG DHREG] CONTINUE;
[RDBYTE] CALL RWBYTE;

[RDBYTE] CALL RBYTE;
[FILL RSLOT25 RGATE READREG DMREG] CONTINUE;
[RDBYTE] CALL RWBYTE;

[RDBYTE] CALL RBYTE;
[FILL RSLOT25 RGATE READREG DLREG] CONTINUE;
[RDBYTE] CALL RWBYTE;

[RDBYTE] CALL RBYTE;
[FILL RSLOT25 RGATE READREG RSREG] CONTINUE;

[IDLE] JUMP READY;

%----------------------------------------------------------- %
% Read the 8-bit A/D's for Crate voltage & temperature %
%----------------------------------------------------------- %

RDSTATS: IF CRATEZ THEN [IDLE] CALL ZCYCLE;
ELSE [ BLANK TESTIN ] JUMP ADOK;
[IDLE] JUMP SRSTRD;

ADOK: IF CRATE THEN [BLANK TESTIN ] JUMP ADOK;
ELSE [ IDLE ] CONTINUE;

WASTIME: [ IDLE ] LOADC 15D; % WAIT for end of A/D Convert %
WTIME: [ BLANK SETX ] LOOPNZ WTIME;


% Load three bytes, voltage and temp. %
SRSTRD: [RDBYTE] CALL RBYTE;
[FILL FILL RGATE WATREG SHREG] CONTINUE;
[FILL RSLOT25 RGATE READREG SHREG] CONTINUE;
[RDBYTE] CALL RWBYTE;

[RDBYTE] CALL RBYTE;
[FILL FILL RGATE WATREG SMREG] CONTINUE;
[FILL RSLOT25 RGATE READREG SMREG] CONTINUE;
[RDBYTE] CALL RWBYTE;

[RDBYTE] CALL RBYTE;
[FILL FILL RGATE WATREG SLREG] CONTINUE;
[FILL RSLOT25 RGATE READREG SLREG] CONTINUE;
[RDBYTE] CALL RWBYTE;

[RDBYTE] CALL RBYTE;
[FILL RSLOT25 RGATE READREG RSREG] CONTINUE;

[IDLE] JUMP READY;

%----------- CAMAC Dataway Cycle -----------------%

% LOAD COUNT FOR ARBITRATION TIME OUT %

GETBUS: [BUSREQ FILL BLANK ] LOADC 255D;
%WAIT to get bus for 12.75us%
TESTGNT: IF /ARBGNT THEN [ BUSREQ FILL BLANK ] JUMP LDCYCLE;
%test bus grant%
ELSE [BUSREQ FILL BLANK] CONTINUE;
[BUSREQ FILL BLANK] LOOPNZ TESTGNT; %time out on no grant%
[TIMEOUT] RETURN;
%no bus access, return stat.%

% Dataway cycle duration is determined by the length of %
% the local BUSY signal generated. The duration of this %
% signal is the product of the SAM clock cycle period and %
% the loaded/pushed count -> 200 ns * 5 = 1 us. %

LDCYCLE: [BUSREQ FILL BLANK ] LOADC 5D;
% !! This is the dataway BUSY loop !! %
DOCAMAC: [BUSREQ FILL CAMAC] LOOPNZ DOCAMAC;

%------------------------------------------------------------%
% Load No-Q retry wait counter with count of 50 -> 10 usec. %
% If (~Q & QCOUNT & NQ) as determined in hardware, execute %
% another dataway cycle. %
%------------------------------------------------------------%
TEST_Q: IF /ARBGNT THEN [BUSREQ FILL TESTIN] RETURN;
ELSE [BUSREQ FILL BLANK] LOADC 50D;
%WAIT BEFORE DOING A NO Q RETRY%
QWAIT: [BUSREQ FILL BLANK] LOOPNZ QWAIT;
[BUSREQ FILL BLANK] JUMP LDCYCLE;

%-----------------------Z CRATE------------------------------%
% NOTE: ! There is no arbitration request for CAMAC access ! %
%------------------------------------------------------------%
ZCYCLE: [IDLE] LOADC 5D;
ZBCYCLE: [BLANK CAMAC] LOOPNZ ZBCYCLE;
[IDLE] RETURN;

%-------------- WAIT LOOPS FOR RECEIVER--------------------- %

NBYTE: [IDLE] LOADC 100D;
N1BYTE: [IDLE] LOOPNZ T1OUT;
[IDLE] POPC;
[IDLE] JUMP OD;
T1OUT: IF BYTE_READY THEN [IDLE] JUMP N1BYTE; % WAIT FOR BYTE READY %
ELSE [IDLE] RETURN;

WBYTE: [IDLE] LOADC 100D;
W1BYTE: [IDLE] LOOPNZ T2OUT;
[IDLE] POPC;
[IDLE] JUMP OD;
T2OUT: IF /BYTE_READY THEN [IDLE] JUMP W1BYTE;
ELSE [IDLE ] RETURN; % WAIT BYTE NOT READY %

RBYTE: IF BYTE_READY THEN [RDBYTE] JUMP RBYTE; % WAIT FOR BYTE READY %
ELSE [RDBYTE] RETURN;

RWBYTE: IF /BYTE_READY THEN [RDBYTE] JUMP RWBYTE;
ELSE [RDBYTE] RETURN; % WAIT BYTE NOT READY %

%--------------------------------------------------------------------%
% Function to read the registers from the parallel port, transfer %
% the data into the proper CAMAC registers, do a dataway cycle and %
% transfer the return data back into the parallel register. %
%--------------------------------------------------------------------%

PRLOAD: IF /I5 THEN [IDLE] RETURN;
ELSE [IDLE] CONTINUE;
% Write N %
[ FILL PRSLOT25 GATE WRTREG NREG] CONTINUE;
IF /I5 THEN [IDLE] RETURN;
ELSE [IDLE] CONTINUE;
% Write A %
[ FILL PRSLOT24 GATE WRTREG AREG] CONTINUE;
IF /I5 THEN [IDLE] RETURN;
ELSE [IDLE] CONTINUE;
% Write F %
[ FILL PRSLOT24 GATE WRTREG FREG] CONTINUE;
IF /I5 THEN [IDLE] RETURN;
ELSE [IDLE] CONTINUE;

% Now test if it is a non-write cycle and do dataway op if true %
IF /SHORT THEN [ IDLE ] JUMP DATWAY;
ELSE [FILL PRSLOT24 GATE WATREG DHREG] CONTINUE;
% For Write functions load 24-bit data %
[ FILL PRSLOT24 GATE WRTREG DHREG] CONTINUE;
[ FILL PRSLOT24 GATE WATREG DHREG] CONTINUE;
IF /I5 THEN [IDLE] RETURN;
ELSE [FILL PRSLOT24 GATE WATREG DMREG ] CONTINUE;

[ FILL PRSLOT24 GATE WATREG DMREG] CONTINUE;
[ FILL PRSLOT24 GATE WATREG DMREG] CONTINUE;
IF /I5 THEN [IDLE] RETURN;
ELSE [FILL PRSLOT24 GATE WATREG DLREG ] CONTINUE;

[ BUSREQ PRSLOT24 GATE WRTREG DLREG] CONTINUE;
[ BUSREQ PRSLOT24 GATE WATREG DLREG] CONTINUE;

% TEST IF CONTROLLER COMMAND i.e. READ LAM OR READ STATUS %
% Z =NO Bus Request or C ? NEEDS bus Request %

DATWAY: [BLANK TESTIN] CONTINUE; %USE SEL. FOR TEST%
IF WHAT THEN [BUSREQ FILL BLANK] JUMP CAMACRD;
ELSEIF STCAMAC THEN [BUSREQ FILL BLANK] CALL PGETBUS;
ELSEIF N30 THEN [ BLANK TESTIN] JUMP PRDLAM;
ELSE [ BLANK TESTIN] JUMP PRDSTAT; 

CAMACRD: [FILL PWSLOT24 GATE READREG DHREG] CONTINUE;
[FILL PWSLOT24 GATE READREG DMREG] CONTINUE;
[FILL PWSLOT24 GATE READREG DLREG] CONTINUE;
[FILL PWSLOT25 GATE READREG RSREG] CONTINUE;
[CLRPAR] RETURN;

%----------------------- Parallel Read LAM ------------------------%

PRDLAM: [ BUSREQ FILL BLANK ] CALL PGETBUS;

[FILL PWSLOT25 GATE READREG DHREG] CONTINUE;
[FILL PWSLOT25 GATE READREG DMREG] CONTINUE;
[FILL PWSLOT25 GATE READREG DLREG] CONTINUE;
[FILL PWSLOT25 GATE READREG RSREG] CONTINUE;

[CLRPAR] RETURN;
%-------------------- Parallel Read Status ------------------------%

PRDSTAT: IF CRATEZ THEN [IDLE] CALL ZCYCLE;
ELSEIF CRATEC THEN [BUSREQ FILL BLANK] CALL PGETBUS;
ELSE [ BLANK TESTIN ] JUMP ADDON;
[IDLE] JUMP PRSTRD;

ADDON: IF /CRATE THEN [BLANK TESTIN ] JUMP MORTIME;
ELSE [ IDLE] CONTINUE;

IF /I5 THEN [ IDLE ] RETURN;
ELSE [BLANK TESTIN] JUMP ADDON;

MORTIME: [IDLE] LOADC 155D; % WAIT for end of A/D Convert %
TIME: [IDLE] LOOPNZ TIME;

PRSTRD: [FILL FILL GATE WATREG SHREG] CONTINUE;
[FILL PWSLOT25 GATE READREG SHREG] CONTINUE;
[FILL FILL GATE WATREG SMREG] CONTINUE;
[FILL PWSLOT25 GATE READREG SMREG] CONTINUE;
[FILL FILL GATE WATREG SLREG] CONTINUE;
[FILL PWSLOT25 GATE READREG SLREG] CONTINUE;
[FILL PWSLOT25 GATE READREG RSREG] CONTINUE;

[CLRPAR] RETURN;

% LOAD COUNT FOR ARBTRATION TIME OUT %

PGETBUS: [BUSREQ FILL BLANK ] LOADC 255D;
%WAIT to get bus for 12.75us%
TESTGNP: IF /ARBGNT THEN [ BUSREQ FILL BLANK ] JUMP LDCYCLP;
ELSE [BUSREQ FILL BLANK] CONTINUE;
[BUSREQ FILL BLANK] LOOPNZ TESTGNP; %time out on no grant%
[TIMEOUT] RETURN;

% --------------- Do CAMAC dataway cycle --------------%
LDCYCLP: [BUSREQ FILL BLANK ] LOADC 5D;
DOCAMAP: [BUSREQ FILL CAMAC] LOOPNZ DOCAMAP; %BSY%
[BUSREQ FILL BLANK] RETURN;

END$

Security, Privacy, Legal

Read Crate volt, temp	N(28) * F(0) * A(0)	Q=0 X=1
Generate Dataway Z	N(28) * F(26) * A(8)	Q=0 X=1
Generate Dataway C	N(28) * F(26) * A(9)	Q=0 X=1
Read Crate LAM Status	N(30) * F(0) * A(0)	Q=1 X=1
Remove Dataway I	N(30) * F(24) * A(9)	Q=0 X=1
Set Dataway I	N(30) * F(26) * A(9)	Q=0 X=1

Fermilab Serial Crate Controller

C. W. Needles, W. R. Knopf RD/Controls