CAMAC 1010 Module

RDMADC Interface

M. Kuplic

1.0 INTRODUCTION

The CAMAC C1010 module provides an interface between Research Division MADC (RDMADC) systems and the EPICURE control system. The RDMADC system is a 64 input Multiplexed Analog to Digital Converter and is described in RD Controls Hardware Release 27

The C1010 module reads 8 channels of the RDMADC every millisecond and pools this information for the EPICURE system to read. The module has an ARCNET interface which allows it to send this pooled information to a central storage point. This point will be located in the front-ends of the EPICURE system to allow them to access pooled information without tying up the CAMAC link. Each C1010 module supports a maximum of 10 fast time plots (FTPs) with a maximum frequency of 100Hz.

2.0 MODULE DESCRIPTION

The C1010 is a CAMAC module designed to interface between the control system and the RDMADC.

2.1 C1010 CONFIGURATION

The C1010 is a single board computer with the following characteristics:

2.2 PROCESSOR INITIALIZATION

On power up, a Dallas Semiconductor DS1232 (U12) holds the reset lines in the RESET state for a minimum of 250mS to allow the power supply and processor to stabilize. If VCC is above 4.75V, the DS1232 will release the reset lines and allow the proces sor to start up. The DS1232 also serves as a RESET button debouncer and will generate a 250mS reset signal if the button is pressed.

During the time that the RESET* pin is asserted on the 80960CA (U33), the processor is in a quiescent reset state. All external pins are inactive, and the internal state of the processor is forced to a known condition. The processor begins its initializ ation when the RESET* pin is deasserted.

When the initialization begins, the 80960CA executes an internal self-test p rogram which is designed to check the basic functionality of its internal data paths, registers, and memory arrays on-chip. The internal self test is not intended for a full validation of the processor's functionality, but rather to detect catastrophic i nternal failures.

The 80960CA then executes a bus-confidence test by reading eight words from the Initialization Boot Record (IBR) located at 0xFFFFFF00 and performing a checksum on the words and the constant 0xFFFFFFFF. If the processor calculates a su m of 0, the test passes. The external bus-confidence test can detect catastrophic bus failures such as shorted address data or control lines in the external system.

The IBR consists of the following words:

On completion of the bus-confidence test, the 80960CA then reads the PRocessor Control Block (PRCB), the Control Table, the Non Maskable Interrupt (NMI) vector and then begins execution at the location pointed to by the First Instruction Pointer. This process is as follows:

READ ADDRESS DESCRIPTION NMEMO

------------------- ---------------------------------- -----

RESET* goes high.

FAIL* goes high.

FFFFFF00 Initial Bus Configuration, Byte 0 IBC

FAIL* goes low.

FFFFFF04 IBC Byte 1

FFFFFF08 IBC Byte 2

FFFFFF10:FFFFFF13 First Instruction Pointer FIP

FFFFFF14:FFFFFF17 PRCB Pointer PRCB

FFFFFF18:FFFFFF2F Bus Confidence Self-test,6 words

PRCB+0000:PRCB+0003 Fault Table Base FTB

PRCB+0004:PRCB+0007 Control Table Base CTB

PRCB+0008:PRCB+000B AC Register Initial Image

PRCB+000C:PRCB+000F Fault Configuration Word

FAIL* goes high.

PRCB+0010:PRCB+0013 Interrupt Table Base ITB

PRCB+0014:PRCB+0017 System Procedure Table Base SPTB

PRCB+0018:PRCB+001B Reserved

PRCB+001C:PRCB+001F Interrupt Stack Pointer

PRCB+0020:PRCB+0023 Instruction Cache Configuration Word

PRCB+0024:PRCB+0027 Register Cache Configuration Word

ITB+03E4:ITB+03E7 NMI Vector (Entry 248)

SPTB+000C:SPTB+000F Supervisor Stack Pointer Base

CTB+0000:CTB+0003 IP Breakpoint 0 IPB0

CTB+0004:CTB+0007 IP Breakpoint 1 IPB1

CTB+0008:CTB+000B Data Address Breakpoint 0 DAB0

CTB+000C:CTB+000F Data Address Breakpoint 1 DAB1

CTB+0010:CTB+0013 Interrupt Map 0 IMAP0

CTB+0014:CTB+0017 Interrupt Map 1 IMAP1

CTB+0018:CTB+001B Interrupt Map 2 IMAP2

CTB+001C:CTB+001F Interrupt Control ICON

CTB+0020:CTB+0023 Memory Region 0 Configuration MCON0

CTB+0024:CTB+0027 Memory Region 1 Configuration MCON1

CTB+0028:CTB+002B Memory Region 2 Configuration MCON2

CTB+002C:CTB+002F Memory Region 3 Configuration MCON3

CTB+0030:CTB+0033 Memory Region 4 Configuration MCON4

CTB+0034:CTB+0037 Memory Region 5 Configuration MCON5

CTB+0038:CTB+003B Memory Region 6 Configuration MCON6

CTB+003C:CTB+003F Memory Region 7 Configuration MCON7

CTB+0040:CTB+0043 Memory Region 8 Configuration MCON8

CTB+0044:CTB+0047 Memory Region 9 Configuration MCON9

CTB+0048:CTB+004B Memory Region A Configuration MCONA

CTB+004C:CTB+004F Memory Region B Configuration MCONB

CTB+0050:CTB+0053 Memory Region C Configuration MCONC

CTB+0054:CTB+0057 Memory Region D Configuration MCOND

CTB+0058:CTB+005B Memory Region E Configuration MCONE

CTB+005C:CTB+005F Memory Region F Configuration MCONF

CTB+0060:CTB+0063 Reserved

CTB+0064:CTB+0067 Breakpoint Control BPCON

CTB+0068:CTB+006B Trace Controls TC

CTB+006C:CTB+006F Bus Configuration Control BCON

FIP+0000:FIP+0003 First Instruction

Program execution begins.

Further information on the 80960CA can be found in the 80960CA Microprocessor Users Manual from INTEL (ISBN 1-55512-099-7).

2.3 PROCESSOR SECTION

Address decoding is accomplished by two chips: a 22V10 (U38) for upper address decoding, and part of an EPM5128 (U5). The 22V10 generates the select lines for the RAM and ROM banks, exte rnal I/O, and select lines for the 8 and 16 bit peripherals. The EPM5128 uses the IO8 and IO16 lines to generate select lines for the NVRAM, ARCNET interface, TCLK decoder, RS232 controller, front panel LEDS and the CAMAC interface.

Address lines A23..00 are buffered with 74ALS573 transparent latches (U40, U43, U44) before they are sent to the peripherals on the board. D31..00 are likewise buffered with 74ALS645s (U27, U28, U30, U34). Write strobes for the 32bit wide RAM banks (U19 , U23, U26, U29, U31, U35, U37 & U39), are generated from byte enables BE3..0 in another 22V10 (U36). This chip also generates read and write strobes for the other peripherals.

2.4 RS-232

RS-232 communication is handled by a Signetics 2692 DUART (U41) and a Maxim MAX233 RS-232 interface chip (U46). The MAX233 chip converts the TTL level signals from the 2692 to +-10V signals. The 2692 is also used for front panel LEDS (LAM, LAM Enable, a nd TCLK present) and generates a 1Khz scheduling interrupt for the processor. The 2692 communications chip is configured for 9600 baud, 8 data bits, 1 stop bit, and no parity.

2.5 ARCNET

ARCNET communication is via SMGs COM20200 ARCNET controller (U14) and can either be via high level signals using the HYC9068 level shifter (U20) or via multi-drop twisted pair using a 75157 as a driver/receiver (U13).

2.6 NVRAM

The C1010 has 32Kb of Non Volatile RAM (U16). This RAM can be used to keep setup information such as ARCNET node ID.

2.7 TCLK Decoder

TCLK decoding is accomplished by using an EP600 (U17) to decode the TCLK clock and data lines from the CAMAC back plane. When the EP600 detects a valid TCLK event, it sets the CLKDAV signal high for one TCLK cycle (50nS?) and outputs the event on CD7..0. The CLKDAV signal i s sent to a 16V8 (U24) which checks if the event has been enabled. Enabling is done by setting the corresponding bit in a 256bit register (U21). If the event is enabled, the 16V8 writes it to a FIFO (U22). The FIFO's output ready line is connected to one of the 80960CA's interrupt inputs.

2.8 CAMAC Interface

The CAMAC interface consists of a 16bit data buffer (U6) and the CAMDEC section of the EPM5128 (U5).

2.9 External I/O

The C1010/1080 interfaces to the outside world via the 36 pin Viking I/O connector. The interface consists of an 8 bit address buffer (U3), a 16 bit data buffer (U1, U2) and six user programmable control lines.

3.0 FIRMWARE OVERVIEW

The FLASH EPROM in the C1010 contains two separate routines, the LOADER and the regular C1010 code. The source code for both routines can be found on the WARNER cluster in the [HDWDOCS.C1010.CODE] sub-directory.

On startup, the LOADER checks a flag in the NVRAM to determine if there is a valid C1010 program stored in the lower section of EPROM. If a valid program is found, it is loaded to RAM and executed. If no valid program is found, the LOADER continues into a load/program routine which is used to load and program new C1010 code into the FLASH EPROM. When the load/program routine is running, the lower 8 front panel LEDs flash alternately at a 5 Hz rate. The LOADER can be invoked by writing 0x4D4B to the CAMAC write registers (F19A3) before resetting the module (F9A0).

3.1 LOAD/PROGRAM ROUTINE

The load/program routine (LOADER) implements the following commands:

3.2 RS-232 INTERRUPT

The RS-232 interrupt reads a character from the UART and places it in a buffer.

3.3 ARCNET INTERRUPT

The ARCNET interrupt routine only handles console input (NTI=0x81). It takes the characters from the ARCNET chip and places them in a buffer.

3.4 TICKER INTERRUPT

The ticker interrupt routine flashes the LEDs, keeps the watchdog chip from resetting the module, and handles the ARCNET transmissions for console output.

3.5 DOWNLOADED CODE FORMAT

Programs downloaded and programmed into the C1010 via the LOADER must be loaded to 0xE0020000, start execution at 0xE0000000 and be in the Microtec INITDATA format, which is as follows:

0x53 - Start byte

0x43 - Copy flag

LWORD - Byte count

LWORD - Destination address

BYTE(S) - Data

0x43... - Extra program sections

0x45 - End flag

See the Microtec linker manual for information on creating an INITDATA section.

4.0 C1010 FIRMWARE OVERVIEW

The background task is an 80960 debugger. Other tasks are entered via interrupts.

On startup, the C1010 code initializes the system peripherals and sends out an ARCNET request for initialization. This request uses NTI=0x28. The listener should then send the current clink count(NTI=0x04). Clinks are the number of seconds that have elapsed since 00:00:00 UT (Universal Time) January 1,1972.

4.1 BACKGROUND DEBUGGER

The debugger implements the following commands:

While in the Modify Memory routine, the following options exist instead of entering a new value.

4.2 RS-232 INTERRUPT

The RS-232 interrupt routine reads a character from the DUART and places it in a buffer.

4.3 CAMAC INTERRUPT

The CAMAC interrupt routine handles read operations over the CAMAC dataway for the RDMADC system as well as other read, write and control functions. A typical CAMAC interrupt does the following:

1) Read the CAMINT chip to determine the type of operation to be performed.

2) Use this value to look up the address of its routine in a lookup table.

3) Execute routine.

4.4 ARCNET INTERRUPT

The ARCNET interrupt routine allows the module to accept incoming commands via the ARCNET interface.

4.5 1KHz (TICKER) INTERRUPT

The 1KHz ticker interrupt routine does the following:

1) Toggles HEARTBEAT.

2) Increments time_into_cycle counter.

3) Increments clink counter

4) Checks for LAM conditions.

5) Reads 8 RDMADC channels.

6) Checks for presence of ARCNET and TCLK signals and sets LEDs accordingly.

7) If ARCNET is connected, sends any pending ARCNET messages.

8) Sends data pool block.

9) Collects data for active FTPs and returns data.

4.6 TCLK INTERRUPT

The TCLK interrupt routine does the following:

1) Reads event ID from TCLK FIFO.

2) Sets flag corresponding to incoming event.

3) Resets TCLK time-out counter.

4) Checks to see if incoming event is a T-TIME.

5) If event is a T-TIME, saves T-TIME value

6) If T-TIME is T1, resets time_into_cycle counter.

7) Checks to see if any Fast Time Plot is triggered by event.

5.0 SUMMARY OF SUPPORTED CAMAC FUNCTIONS

F0 A0-15 : Read Channels 0-15

F1 A0-15 : Read Channels 16-31

F2 A0-15 : Read Channels 32-47

F3 A0-15 : Read Channels 48-63

F5 A2 : Read module status.

F6 A0 : Read Module ID.

F6 A1 : Read software version.

F6 A3 : Read FOP status.

F6 A4 : Read FOP data.

F6 A5 : Read module serial number.

F6 A6 : Read ARCNET address.

F6 A13 : Read LAM mask.

F6 A14 : Read LAM request register.

F8 A0 : Check LAM.

F9 A0 : Hardware reset.

F10 A0 : Clear LAM.

F14 A0 : Set LAM.

F19 A2 : Write FOP command.

F19 A3 : Write FOP data.

F19 A6 : Set ARCNET address.

F19 A12 : Clear LAM (Sel BITS).

F19 A13 : Write LAM mask register.

F19 A14 : Write LAM request register.

F24 A15 : Disable LAM.

F26 A15 : Enable LAM.

6.0 DETAILED EXPLANATION OF FUNCTION CODES

6.1 F0-F3 A0-15: READ RDMADC DATA

6.2 F5 A2 : READ MODULE STATUS

Status when bit set:

D15:D05 - Unused

D04 - Clink counter set

D03 - Data pooling active

D02 - LAM Enabled

D01 - ARCNET Missing

D00 - TCLK Missing

6.3 F6 A0 : READ MODULE ID

Returns a value of 1010 for this module.

6.4 F6 A1 : READ SOFTWARE VERSION

D15:D08 - Major Rev

D07:D00 - Minor Rev

6.5 F6 A3 : READ FOP STATUS

Read FOP status word.

D15:D08 - Status

greater than 0 - Partial or qualified success.

equal to 0 - Success

less than 0 - Error

D07:D00 - FOP Type code

8-bit type code with which the status in the high byte is associated. 0 implies status is from last command transmission on F19A3.

6.6 F6 A4 : READ FOP DATA

Type code specific data to be returned to the host. The amount of data which is available is also type code specific.

6.7 F6 A5 : READ MODULE SERIAL NO

6.8 F6 A6 : READ ARCNET ADDRESS

D07:D00 - ARCNET node address

6.9 F6 A13 : Read LAM Mask

Status when bit set:

D15 - Set by F14A0 (Latched)

D14:D06 - Unused

D05 - Clink counter not set

D04 - ARCNET Duplicate Node (Latched)

D03 - ARCNET Transmitter Message ACK Time-out (Latched)

D02 - ARCNET Excessive NAKs (Latched)

D01 - ARCNET Missing

D00 - TCLK Missing

6.10 F6 A14 : READ LAM REQUEST REGISTER

See section 8.8 for bit definitions.

Latched bits must be cleared by the host.

6.11 F8 A0 : Check LAM

Returns Q if LAM is set.

6.12 F9 A0 : HARDWARE RESET

6.13 F10 A0 : CLEAR LAM

Clears the LAM request register.

6.14 F14 A0 : SET LAM

Sets bit 15 of the LAM request register.

6.15 F19 A2 : WRITE FOP COMMAND

This function is used to begin and/or end a command to the modules type code processor.

D15 - SNM - Start receiving new data on F19A3.

Current contents of the received message buffer are lost.

D14 - XEQ - End of message to module, execute

requested action with supplied data (if any).

D13:D08 - Unused

D07:D00 - TC - 8-bit command code. Type codes 1-15 are reserved for functions common to all modules. All other type codes are implementation specific and are assigned by the module programmer. The same type code should be specified on both the SNM and XEQ transmissions.

Note that if the SNM and XEQ bits are both set then there is no message data to be transmitted on F19A3, all meaning is implicit in the type code itself and execution of the type code handler will be gin immediately. In that case any data previously transmitted via F19A3 is lost.

6.16 F19 A3 : WRITE FOP DATA

Up to 32 words of 16-bit data will be accepted via this function code following a FOP command to start a new message on F19A2. This data will be placed in a temporary buffer and is available to the type code handler routine when an execute command is rec eived on F19A2.

6.17 F19 A6 : SET ARCNET ADDRESS

D07:D00 - New node number

6.18 F19 A12: CLEAR LAM (SEL BITS)

D15:D00 - Bit mask for LAM register. Setting a bit causes the corresponding bit in the LAM register to be cleared.

6.19 F19 A13: WRITE LAM MASK REGISTER

See section 8.8 for bit definitions.

6.20 F19 A14: WRITE LAM REQUEST REGISTER

See section 8.8 for bit definitions.

6.21 F24 A15 : DISABLE LAM

6.22 F26 A15 : ENABLE LAM

7.0 FOP TYPE CODES

The C1010 module responds to the following FOP type codes:

001 - Echo message

003 - Read extended status

004 - Set clink counter

017 - Read debugger output

018 - Write debugger input

7.1 FTC001 - ECHO MESSAGE

Set up subsequent read of previously transmitted command data for testing purposes.

7.2 FTC003 - READ/CLEAR EXTENDED STATUS

Set up subsequent read of extended status registers. If ANY command data has been supplied (i.e. SNM and XEQ bits not both set on call to F19A2), then the diagnostic counters will be zeroed upon receipt of XEQ. The format of the return array is:

Word Definition

1 Restart Counter

2 Current T-Time

3 Clink counter, low word

4 Clink counter, high word

5 Time into cycle, low word

6 Time into cycle, high word

7 ARCNET Reconfiguration counter

8 ARCNET Reconfigurations caused by the C1010

9 ARCNET Unknown NTI counter

10 NULL

7.3 FTC004 - SET CLINKS

Write new value into clink counter. Clinks are the number of seconds that have elapsed since 00:00:00 UT (Universal Time) January 1, 1972.

7.4 FTC017 - READ DEBUGGER OUTPUT

Set up subsequent read of debugger output buffer. The status return is the number of bytes available to read. The characters are transferred two at a time, with the first character in the upper byte (Big endian).

7.5 FTC018 - WRITE DEBUGGER INPUT

Write characters to the debugger input buffer. The characters are transferred two at a time, with the first character in the upper byte (Big endian). Non ASCII characters are ignored.

8.0 ARCNET NTIs

All communication via the ARCNET interface is done using EADNET protocol. This protocol defines a packet header consisting of 12 bytes.

BYTE DATA

0,1 System Code (Defined by ARCNET dudes) 0x8201

2 Destination House

3 Destination Node

4 Destination NTI

5 Pad count

6 Source House

7 Source Node

8 Source NTI

9 Source message sequence #

A Max. packets: This packet (4 bits each)

B Data type code (See EADNET description)

After the EADNET header, up to 497 bytes of data may follow. The data size is NTI specific.

The C1010 module responds to the following NTIs:

0x00 - Display configuration

0x01 - Echo attached message

0x08 - Console interface

0x09 - Stop all tasks

0x0A - Reset module

0x0F - Accept packet

0x20 - Start/Stop data pooling

0x21 - Start plot

0x22 - Stop plot

0x24 - Set clink counter

8.1 0x00 : DISPLAY CONFIGURATION

Returns an array of strings with keywords as follows:

MODULE=C1010

VERSION=1.00

8.2 0x01 : ECHO ATTACHED MESSAGE

Returns a copy of the data following the EADNET header.

8.3 0x08 : CONSOLE INTERFACE

The data field after the EADNET header contains a line of characters to be transferred to the debugger input buffer. The debugger will the then send its output to the source house.node.nti until the next command request. The line must be terminated with a carriage return (0x0D) in order for the debugger to begin processing the line.

8.4 0x09 : STOP ALL TASKS

Stop all tasks running on the module, these include fast time plots, data pooling and ARCNET console routines.

8.5 0x0A : RESET MODULE

Causes hardware reset.

8.6 0x0F : ACCEPT PACKET

Ignore packet received. Used for testing purposes (ARCMAP).

8.7 0x20 : START/STOP DATA POOLING

The data field after the EADNET header contains two words. The first word is the Device ID used by the front-end data pooler to locate the incoming data in the pool. The second word is the rate of the data pool return packets , in milliseconds. Both words are in little endian format (Low Byte, High byte). Selecting a period of zero will stop the data pool process.

The data pool data is returned in the following format:

struct DATAPOOL_RETURN
{
word device_id; /* 0x00-Device ID */
dword timestamp; /* 0x02-uSecs into cycle */
word data[64]; /* 0x06-64 channels */
}

8.8 0x21 : START PLOT

The data field after the EADNET header contains the following structure:

struct FTP_REQUEST (NTI=0x21)
{
dword handle; /* 0x00-Device handle */
word rate; /* 0x04-Msecs between reads */
byte channel; /* 0x06-Channel to plot */
byte reserved; /* 0x07-Reserved */
struct FTD start; /* 0x08-Start time */
struct FTD stop; /* 0x0C-Stop time */
};

Plot data is returned at 500mSec intervals while data is being collected. The plot data is returned in the following format:

struct FTP_RETURN
{
dword handle; /* 0x00-Device handle */
dword ts_clinks; /* 0x04-Timestamp clinks */
dword ts_usecs; /* 0x08-Timestamp usecs */
word points; /* 0x0C-Number of points */
word reserved; /* 0x0E-Reserved */
word plot_data[points]; /* 0x10-Plot data */
}

8.9 0x22 : CANCEL PLOT

The data field after the EADNET header contains the handle of the plot to cancel.

8.10 0x24 : SET CLINK COUNTER

Load clink counter with data following the EADNET header.

9.0 FRONT PANEL FEATURES

9.1 LEDS

N indicates that the crate controller has initiated a dataway cycle addressed to this module. This LED is stretched to 10 ms to aid viewing.

LAM indicates that the module is asserting the dataway LAM signal for this slot. The host must read the LAM request register F6A14 in order to identify the nature of the request.

LAMEN indicates that any unmasked bits in the LAM request register may cause the module LAM to be asserted. When off, module LAM will never be asserted. LAM source bits which are set by module firmware will be latched and may cause LAM to be asse rted when the LAM is enabled at some later time. F24A0 and F26A0 are provided to set the state of the LAM enable gate. After power-up or reset, LAM is disabled.

HBT indicates, when blinking, that the module is running and accepting interrupts. This line is also tied to the DS1232 micromonitor chip which will reset the module if this signal does not occur for 600mS. This LED is stretched to 10mS to aid viewing.

TCLK indicates that the module has received a TCLK event within the last sixty seconds.

FAIL indicates that a failure has occurred in the 80960 processor. This LED will light after restart when the 80960 is performing its self test, and then go out while the module is running properly.

ARC indicates that the module is receiving an ARCNET token.

POOL indicates that the module is sending its information to the front-end data pooler.

CLINKSindicates that the module clink counter has been set.

UNUSED LEDS: There is one (1) unused LED on the front panel.

TTIME: The four (4) T-TIME LEDs display the current T-TIME in binary format.

9.2 RESET PUSH-BUTTON

The RESET push-button, when pressed, resets the processor, peripheral chips and other circuits. The CAMAC function F9A0 activates the same sequence.

9.3 RS232 CONNECTION

The RS-232 connection allows an external terminal to interface with the C1010 module. Pinouts, viewed from front, are as follows:

GND -1 4- GND
TX -2 3- RX

10. I/O CONNECTOR DEFINITION

The I/O connector used is of the 36-pin Viking type.

Left(L) and right(R) are viewed from the front of the crate

C1010 I/O Signals
PinSignalPinSignal
1L GND 1R GND
2L D2 2R D1
3L D4 3R D3
4L D6 4R D5
5L D8 5R D7
6L D10 6R D9
7L D12 7R D11
8L D14 8R D13
9L D16 9R D15
10L /XDS10RXA6
11L/XINT11RXA5
12L XR/W12RXA4
13L /BHE13RXA3
14L/XACK14RXA2
15L/XSEL15RXA1
16L XRES16RXA0
17L 5VDC17RXA7
18L ARC+18RARC-

11. MEMORY MAP


FFFE0000-FFFFFFFF : EPROM
E0000000-E003FFFF : SRAM
D0000006 : CAMAC Interrupt Acknowledge
D0000004 : LAM ENABLE
D0000002 : LAM
D0000000 : CAMAC Data Buffers
C0000800-C0000FFF : NVRAM
C0000300-C000030F : DUART
C0000200 : TCLK FIFO
C0000100-C00001FF : TCLK Mask RAM
C0000000-C0000007 : COM20020 ARCNET Interface
B0000200-B0000280 : RDMADC

12. JUMPERS

JP1 - Viking I/O Clock select

Position A: 1Khz

Position B: External (Default)

JP2 - TCLK CLK Input

JP3 - TCLK DATA Input

Installed: TCLK decoder Enabled. (Default)

Removed: TCLK decoder Disabled.

JP4 - FLASH ROM Program Enable/Disable

JP5 - FLASH ROM Program Enable/Disable

JP4 Installed: FLASH Programming Enabled (Default)

JP5 Installed: FLASH Programming Disabled

JP6 - 80960 Clock Mode Select

Installed: 1X clock

Removed: 2X clock (Default)

JP7 - RAM Type Select

Position A: 128K x 8 RAMs

Position B: 32K x 8 RAMs (Default)

JP8 - Watchdog timer input select

Position A: Heartbeat output (Default)

Position B: 3.6864MHz clock. (Watchdog Disable)

13. PAL SOURCE FILES

.

14. SCHEMATIC

The C1010 schematic drawing (0880-ED-172995) can be found on the WARNER cluster in the [HDWDOCS.C1010.PCAD] directory in the file C1010F.SCH.

APPENDIX A - ACRONYMS USED

APPENDIX B - TRADEMARKS