Hardware Design Note xx.0

Specification for the C1045 Motor Controller Interface

M. Larwill, R. Flood


The C1045 is a CAMAC module which is used to interface between the control system and 1 Motion Controller. This allows the C1045 to control 2 motors. Through the use of a predefined set of F and A codes the C1045 can control motors or monitor motor status. The C1045 maintains a local data pool which allows it to response to status and position reads from CAMAC within 20us.

When not responding to CAMAC interrupts or status/position interrupts from the Motion Controller the C1045 requests parameter information from the Motion Controller. A dummy parameter request is sent after every 10 parameter requests for a communications link check.

The C1045 contains a Z8002 microprocessor with 32k of RAM, 32K ROM, Z8036 CIO, ARCnet interface, and 2681j DUART. The CAMAC interface uses a 50C32 EPLD for sequencing and a PROM to select the FNA response codes. The C1045 uses a 32 data bit serial block transfer protocol to communicate with the motion controller.

C1045 Memory Configuration Table

0002Z8002 initial FCW
0004Z8002 initial PC
0006Jump addr for ctl-c
0400Length of NVRAM in longwords
0E0EMachine code for breakpoint instruction
4000Initial fcw
6802Start of non-volatile RAM (byte-size)
8300Start of ROM based PSAREA
8600Start of system variables
F3FETop of system stack
F400ARCnet RAM
FC00ARCnet Com
FD01Cio Z8036 base
FD81Duart base
FDE1High speed serial link
FDF1Tclk fifo (byte address)
FE01Start of tclk mask ram

Memory map for the C1045 implementation:

   0000-- |     Code Segment            | 
          |                             | 
          |     EPROM                   | 
   7FFF-- |                             | 
   8000-- |     PSAREA                  | 
          |                             | 
   8600-- |     RAM- Variable Storage   | 
          |                             | 
   F3FE-- |     System Stack            | 
   F400-- |     ARCnet Ram              | 
   FBFF-- |                             | 
   FC00-- |     ARCnet COM              | 
   FCFF-- |                             | 
   FD00-- |     8036 CIO                | 
   FD7F-- |                             | 
   FD80-- |     2681 DUART              | 
   FDBF-- |                             | 
   FDC0-- |     CAMAC low word          | 
   FDD0-- |     R/W CAMAC high byte     | 
   FDE0-- |     R/W block transfer      | 
   FDF0-- |     RD Tclk Fifo            | 
   FE00-- |     R/W TCLK mask           | 
          |                             | 
   FFFF-- |  256 bytes (word boundary)  | 

1 RS-232 Interface

The 2681 communications chip is configured by firmware for 8 data bits, 1 stop bit, no parity, 9600 baud, no CTS/RTS handshaking. The DUART generates a non-vectored interrupt. Both channels of RS-232 are available at the rear Viking connector. RS-232 channel 1 is available at a front panel lemo. Both channels are buffered with a MAX232 interface chip. Only the transmit and recieve signals are present. The NAK/ACK protocol is handled in software.

The following table shows the allocated address space for Signetics 2681 Dual Asynchronous Transceiver(DUART)

RS-232 Address Allocation Table
fd81Port A Mode registers(MR1A,MR2A)
fd83Port A Status Register (read)
Clock Select Register (write)
fd85Port A command register (write)
fd87Port A RX/TX holding registers
fd89Aux control register (write)
fd89Input Port Change Register (read)
fd8bInterrupt mask register
fd8dCounter/Timer Upper Register
fd8fCounter/Timer Lower Register
fd91Port B mode registers(MR1B,MR2B)
fd93Port B status(SRB)/clock select(CSRB)registers
fd95Port B command register
fd97Port B Rx/Tx holding registers
 reserved - duart + 24
fd9bOutput Port Config. Reg.
fd9dSet Output Port Bits command (write)
Start Counter Command (read)
fd9fReset Output Port Bits command (write)
Stop Counter Command (read)

Z8036 CIO Counter/timer

The Z8036 is a multifunction chip which provides system counters, status and interrupt handling. The following tables show the address space allocated to the Z8036 CIO Counter/Timer and PIO Unit.

Z8036 Main Control Registers for the CIO
fd01Master Interrupt Control Register
fd03Master Configuration Register
fd05Interrupt Vector, Port A
fd07Interrupt Vector, Port B
fd09Interrupt Vector, Counters/Timers
fd0bData Path Polarity, Port C
fd0dData Direction, Port C
fd0fSpecial I/O Control, Port C

Z8036 Command, Status and Data Registers
fd11 Command/Status, Port A
fd13 Command/Status, Port B
fd15 Command/status, Counter/Timer 1
fd17 Command/status, Counter/Timer 2
fd19 Command/status, Counter/Timer 3
fd1b Data Register, Port A
fd1d Data Register, Port B
fd1f Data Register, Port C

Z8036 Counter/Timer Registers
fd21 Current Count - MSB's for CT1
fd23 Current Count - LSB's for CT1
fd25 Current Count - MSB's for CT2
fd27 Current Count - LSB's for CT2
fd29 Current Count - MSB's for CT3
fd2b Current Count - LSB's for CT3
fd2d Time Constont - MSB's for CT1
fd2f Time Constont - LSB's for CT1
fd31 Time Constont - MSB's for CT2
fd33 Time Constont - LSB's for CT2
fd35 Time Constont - MSB's for CT3
fd37 Time Constont - LSB's for CT3
fd39 Mode Specification for CT1
fd3b Mode Specification for CT2
fd3d Mode Specification for CT3
fd3f Current Vector Register

Z8036 Port A Specification Register
fd41 Mode Specification
fd43 Handshake Specification
fd45 Data Path Polarity
fd47 Data Direction
fd49 Special I/O Control
fd4b Pattern Polarity
fd4d Pattern Transition
fd4f Pattern Mask

Z8036 Port B Specification Register
fd51 Mode Specification
fd53 Handshake Specification
fd55 Data Path Polarity
fd57 Data Direction
fd59 Special I/O Control
fd5b Pattern Polarity
fd5d Pattern Transition
fd5f Pattern Mask

CIO Ports Signal Names
Port APort BPort C

Z8036 CIO Initialization

The Z8036 is initialized to the following settings upon reset and power on. The PCLOCK input is 5MHz. CT1 is set for 1KHz repetitive one-shot mode. It is only used to trigger CT2 which then divides CT1 by 100 to get a 10Hz vectored interrupt on vector #2 with Vector Base = 00.

PORTCbit 3TXAFhigh = transmit fifo almost full or empty (input)
bit 2TXHFhigh = transmit fifo half full (input)
bit 1MODE32high = 32 bit block transfer mode (output)
bit 0/RCVRESlow = reset fifos (output)
PORTBbit 7RXAFEhigh = rcv fifo almost full or empty (input)
bit 6RXHFhigh = rcv fifo half full (input)
bit 5/TREQINhigh = ok to xmit (input)
bit 4CAMDIShigh = camac ints disabled (output)
bit 3/LAMREQlow = request a LAM (output)
bit 2/LAMENlow = enable LAMs (output)
bit 1TCLKlow = led on events have happened (output)
bit 0HRTBTlow = led on (output)
PORTAbit 7/TBEB(unused) (input) Port A bit 7 high is the Tev clock input. Tev clock high generates an interrupt on vector 31
bit 6/TBEA(unused) (input)
bit 5/DAVB(unused) (input)
bit 4/DAVA(unused) (input)
bit 3CLKINThigh = tev clk int (vector 16) (input)
bit 2SERDAVhigh = rcv fifo int (vector 14) (input)
bit 1SERDYhigh = xmt fifo has data in it (status) (input) port A bit 1 is the data available from the Motion Controller input. data available generates an interrupt on vector 18
bit 0LANIRQ(unused) (input)

Timer error will generate vector 6 (because base=0)

Background Debugger

The debugger implements the following commands
HEdisplay help menu
SB nset breakpoint at n
RB nremove breakpoint at n
LBlist breakpoints
DB/W/L m ndisplay bytes/words/long words from m to n
MB/W/L mmodify e/word/long at location m
GO mexecute program at m
MR nmodify register n
DRdisplay register contents
HLhex load (intel format)
TDset/display time of day clock
CKdisplay TCLK events
EI,DIenable/disable vectored interrupts
EC,DCenable/disable CAMAC interrupts
32,1632 or 16 bit serial (def=32)
RRepeat last command

Timer Interrupt

The timer is set to interrupt at a 10Hz rate. The timer interrupt is used to perform several low-priority tasks:
  1. Increment the time of day clock
  2. If the previous 10Hz interrupt is not finished, return
  3. Enable interrupts
  4. Do heartbeat LED
  5. If either FIFO is full, LAM
  6. Process any data received from Motion Controller
  7. Request next data pool item from Motion Controller
  8. Update LAM
Any time the LAM source or mask register is changed through CAMAC, as well as every time the 10Hz timer interrupt occurs, LAM will be set or not set according to whether LAM is enabled, and the contents of the source and mask registers.

CAMAC Slave Operation

The CAMAC slave interface is implemented using a Prom for encoding the FNA code and generation of the X response combined with a 50C32 EPLD for control of the operation. The CAMAC operations are as follows.

CAMAC Timing diagrams

This module conforms to the ANSI 583-1982 spec. for dataway cycle timing as described in the standard and as shown in figures 9 and 10 on page 54.

CAMAC Write Functions

clear bit 0 in LAM source word
clear bit 1 in LAM source word
clear bit 2 in LAM source word
clear all LAM source word bits
read LAM source register
read LAM mask register
F16 A(X)
Set Analog Position
F17 A(X)
Set Digital Position
F18 A(X) W24-17=0-15
Set Preset Position
F18 A(X) W24-17=127
Request Readback of a Preset Position
F19 A(X) W24-17=0-8 Normal Mode
Set Motor Controller Parameters
0Motor set up value
1Motor hold current
2Motor run current
3Initial velocity
4Maximimum velocity
5Acceleration value
6Slow down
7Waveform select
8Error band
F19 A(X) W24-17=0-8 Preset Mode
Set Motor Controller Parameters
F19 A(X) W24-17=9-13
Mode Control
BIT0 - normal mode
BIT1 - preset mode
BIT2 - slaved operation
BIT3 - slaved operation with presets
BIT0 - LVDT analog position
BIT1 - external analog position
BIT2 - steps (internal counter)
BIT3 - shaft encoder (external counter)
11Control Bit1 = high speed,0 = low speed
12# attemptsNumber of attempts at desired position.
13AveragesNumber of averages for analog position.
F19 A(X) W24-17=125
Target Position Readback Request
F19 A(X) W24-17=126
Waveform Readback Request
F19 A(X) W24-17=127, PARAM#=0-8 Normal Mode
Parameter Readback Request
F19 A(X) W24-17=127,PARAM#=0-8 Preset Mode
Parameter Readback Request
F19 A(X) W24-17=127, PARAM#=9-13
Mode Control Readback Request
F20 A(X) Not Restore Mode
Set Custom Waveforms
F20 A(X) Restore Mode
Dump Next Word to Box
F21 A(X)
Set Control Word
0Stop motor immediately
1Go to reference
2Go to limit switch 1
3Go to limit switch 2
4Reset save pointer
5Request next save value (for readback)
6Restore mode (if set will reset pointer)
7Save mode (if set will reset pointer)
write LAM source register
write LAM mask register
disable LAM in software
enable LAM in software

CAMAC Read Functions

F0 A(X)
Read Current Device Analog Position
F1 A(X)
Read Current Device Digital Position
F2 A(X)
Read Preset Positions
an Introduction
F3 A(X)
Read Last Requested Position to Seek
F3 A(X)
Read Waveform Values
F3 A(X)
Read Motor Control Parameters
F3 A(X)
Read Mode Control Parameters
F4 A(X)
Read Status Word
0Motor stopped: 1=stopped
11=motor stopped at desired position
21=motor is at limit switch 1
31=motor is at limit switch 2
41=motor is moving toward limit switch 1
51=motor is moving toward limit switch 1
6Local/Remote: 1=Remote 0=Local
7Motor enabled: 1=enabled 0=disabled
8Normal/Preset: 1=Preset 0=Normal
9Slaved/Not Slaved: 1=Slaved 0=Not Slaved
10Internal/External: 1=External 0=Internal
11Analog/Digital: 1=Digital 0=Analog
12not used
13Serial link down: 1=down 0=up
14Reset routine: 1=in reset routine 0=out of reset routine
15Error band exceeded: 1=exceeded 0=ok
F5 A(X)
Read Next Save Word
F6 A(0)
Read C1045 Module I.D.
F6 A(1)
Read C1045 Firmware Version Number
F6 A(2)
Read Motion Controller Firmware Version

CAMAC Control Functions

F9 A(0)
Activate Reset Output
Causes C1045 to be reset and assert its reset output.

C1045 to Motion Controller Protocol

The C1045 module communicates with the Motion Controller by sending it 32 bits at a time. The first byte sent generally contains a function code and a motor number. The function code tells the Motion Controller what to do with the 24 bits of data that will follow, and the motor number tells the Motion Controller to which motor the data applies. Byte 2 (the second byte received in the 32 bit packet) corresponds to CAMAC W8-W1 in the CAMAC write functions. Byte 3 corresponds to CAMAC W16-W9 in the CAMAC write functions. Byte 4 corresponds to CAMAC W24-W17 in the CAMAC write functions.
Code 8
Set Analog Position
Code 9
Set Digital Position
Code A Byte4=0-15
Set Preset Position
Code A Byte4=127
Request Readback of a Preset Position
Code B Byte4=0-8
Normal mode: Set Motor Controller Parameters
Code B Byte4=0-8
Preset mode: Set Motor Controller Parameters
Code B Byte4=9-13
Mode Control
Code B Byte4=125
Target Position Readback Request
Code B Byte4=126
Waveform Readback Request
Code B Byte4=127
Param#=0-8 Normal Mode: Parameter Readback Request
Code B Byte4=127
Param#=0-8 Preset Mode: Parameter Readback Request
Code B Byte4=127
Param#=9-13: Mode Control Readback Request
Code C Not Restore Mode
Set Custom Waveforms
Code C Restore Mode
Dump Next Word to Box
Code D
Set Control Word
Code 6
Request Motor Box Firmware Version Number
Code 69
Test Link Code

Motion Controller to C1045 Protocol

The Motion Controller communicates with the C1045 module by sending it 32 bits of data at a time. The first byte sent generally contains a function code and a motor number. The function code tells the C1045 what to do with the 24 bits of data that will follow, and the motor number tells the C1045 to which motor the data applies. Byte 2 (the second byte received in the 32 bit packet) corresponds to CAMAC W8-W1 in the CAMAC write functions. Byte 3 corresponds to CAMAC W16-W9 in the CAMAC write functions. Byte 4 corresponds to CAMAC W24-W17 in the CAMAC write functions. The following is a list of the Codes and thier use.
Code 0
Transfer Current Device Analog Position to C1045
Code 1
Transfer Current Device Digital Position to C1045
Code 2
Transfer Preset Positions to C1045
Code 3 Preset Mode
Transfer Motor Control Parameters to C1045
Code 3 Normal Mode
Transfer Motor Control Parameters to C1045
Code 3
Transfer Mode Control Parameters to C1045
Code 4
Transfer Status Word to C1045
Code 5
Transfer Next Save Word to C1045
Code 62
Transfer Firmware Version to C1045
Code 69
Test Link Response to C1045
Code 7
Transfer Last Requested Position to Seek to C1045
Code E
Transfer Waveform Values to C1045


This data link is capable of supporting at least 200 nodes. The network will support a length limit of not less than one mile. Nodes are able to interconnect by way of a single coax cable running from node to node. The link will use the ARCnet protocol and will employ an ARCnet Bridge to connect the Intrahouse LAN to the Interhouse network.


Details of the ARCnet controller can be found in the COM9026 specification but a brief description of the ARCnet follows. The ARCnet controller has access to a data buffer which appears to be 2Kx8 bits but is addressable by the Z8002 CAMAC processor in 16-bit words. The processor arbitrates with the COM chip for access to the ARCnet data buffer which is mapped into the memory space of the processor. The ARCnet controller registers are also memory mapped.

The ARCnet connects to the C1045 via a front panel lemo which must be adapted to the ARCNET RG59 coax. The 8-bit node address is jumper selectable and is frequently scanned by the COM9026.

When enabled, the COM9026 will generate an interrupt (LANIRQ*) to indicate the receipt of a message or the completion of sending a message. The COM chip will pass and receive tokens transparently to the processor. When a token is received the COM chip is allowed to transmit messages.

Reconfiguration is also transparent to the processor. If the COM chip has undergone reconfiguration, it will set the LAN status register (FC00H). The reconfiguration time and response time are jumper selectable using the ET1, ET2 lines. An ARCnet hybrid contains the cable interface discrete logic. This hybrid is protected from cable transients by an RC network.

COM Registers

The COM9026 LAN status register (FC00H)

The LAN status register bits are as follows


0TA Transmitter available
1TMA Transmit message acknowledge
2RECON Reconfiguration occurred
4POR Power on reset occurred
5ETS1 current value of the ET1 jumper
6ETS2 current value of the ET2 jumper
7RI Receive Inhibited, packet received

COM9026 LAN Interrupt mask register (FC00H)

The LAN interrupt mask register bits are defined as follows


0Transmiter Available (TA) Interrupt mask
1Not used
2Reconfigure (RECON) Interrupt mask
3Not used
4Not used
5Not used
6Not used
7Recieve Inhibit (RI) interrupt mask

The COM9026 LAN Control register (FC01H)

The COM9026 LAN control register bits are defined as follows

COMMAND ( see following table)

The COM9026 LAN control register accepts the following commands

00000001Disable Transmitter
000nn011Enable transmit from page nn
b00nn100Enable receive to page nn (b=1 enables broadcasts)
0000c101Define configuration (c=1 enables long packets)
000rp110Clear flags (p=1 clears POR r=1 clears RECON)



The following is a list of the front panel leds.
This led will be lit when the CAMAC N line is asserted for this module.
When lit indicates that LAMs are enabled.
When lit indicates that a LAM is asserted.
This led will be lit if the TCLK is present on the CAMAC backplane.
When the C1045 is ready to recieve data from the Serial Block transfer, this led will be lit.
When lit indicates that the C1045 is recieving a ready signal on the RRDY input and the attached module is ready to recieve data on the serial block transfer TDATA line.
Will be lit when there is +5 volt power to the module.
Will be lit when there is -5 volt power to the module.
These 8 led indicate the ARCnet address of this C1045. The leds are configured as follows.
There are 4 user defined led, which are connected to the CIO chip and can be read and writen.
This led will blink when the heartbeat routine is running.
ARCnet DSYNC active
Will be on continuously if the ARCnet has tokens passing. It will be blinking if reconfigures are ocurring. It will be off if no signal is recieved from another device.


Broadcast data Link
The broadcast data link (ARCnet) shall connect to the C1045 through this front panel lemo which must then be adapted to the coax.
Is used to indicate readiness to recieve data on the block transfer serial link.
This is the serial block transfer output data connector, which should be connected to the RDATA of another module.
Normally connected to another modules TDATA to provide an input for serial block transfer data.
The Serial block transfer fifo is ready to recieve data.


CAMAC contact allocation

This module conforms to the ANSI/IEEE STD 583-1982 spec. table 2 page 19 for CAMAC contact allocations of a normal station. No connection is made to the +12,-12,+24,-24,C,I,B,or Z lines.

SWITCHES and Jumpers

The module shall contain the following switches and jumpers.

LAN jumpers

The ARCnet controller logic requires the following jumpers.

11 74.7 840
10 283.41680
01 561.81680

The ARCnet controller also has a jumper for ECHO loop back control; when enabled this causes the module to echo any message sent to it.



As described in Fig K4.2.2 of ANSI Std 583-1982 page 16.

CAMAC board spec.

This module complies with ANSI Std 583-1982 Mechanical specs. as shown in Fig.4 page 48 and Fig.8 page 53.

CAMAC board layout

The parts selected fit on a single wide CAMAC module. The CAMAC board has 6.57in x 11in (72 sq. in.) of usable space. The P.C. card is a 6 layer board with separate power and ground layers and 4 signal layers.


CAMAC dataway

This module complies with all the CAMAC signal requirements as specified in the ANSI Std 583-1982 page 39 Table 6 and all specifications as stated in the standard under section 7. Signal Standards.

Power requirements

This module conforms to ANSI Std 583-1982 as stated in section 8 Power line standards. This board needs +6 power connection and is fused at 2A. The input power connection also has bypass caps and tranzorbs for transient protection.



A preliminary initialization program can be examined by referring to Warner::USR$DISKS:[HDWDOCS.C1045.SOFT] files C1045.Z8K, C1045.lis


This module usually should be connected to a Motor Controller box. The C1045 module must have its jumpers configured according to its specification. Note that the rear Viking connector is used for RS232 local control and may need a connector attached on the rear of the CAMAC crate.

The front panel lemos must have cables connected to the Motor controller box and one connection to the ARCnet. See the previous discription of connectors for details of how to make the interconnection.

After turning on the power the +5 power LEDs should be lit indicating that the fuses are intact and there is power on the modules. At this time the module should also have reset and performed its initialization routines. The Heart beat led should be blinking.



See Warner::USR$DISKS:[HDWDOCS.C1045]*.SCH for the PC CAPS schematics of the design. Copy all *.sch and *.sym to your area then use SYSTEM.SCH as the top level drawing.


See Warner::USR$DISKS:[HDWDOCS.C1045] for available P.C. board layout and front panel drawings. The layout was done using PC CARDS.

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