RD/Controls Hardware Release Note: 24.2
C1091 8 Channel Timing with TEV Decoding.

A. Legan, K. Dabous
February 12, 1992

Table of Contents

I. General Description.

The C1091 module is a single wide CAMAC module built around a Zilog Z8002 16 bit microprocessor running at 10 Mhz which provides 8 channels of delayed output pulses at a resolution of 1 micro second. Each channel may be programmed independently with respect to a delay and clock events.

The programmable channel may be enabled or disabled individually or as a group. The channel delay may range from a minimum of 1 micro second to a maximum of 7FFF FFFF micro seconds (35.79 minutes.) An enabled channel will begin to countdown when one of its clock events occurs. The clock events are selectable and may include any of the possible 256 Tev Clk events except for FF and FE. A maximum of eight events are allowed per channel.

Loading timing delays in C1091 is done in a synchronous mode. A new delays is set to a channel when the channel's pre set Tev Clk event occurs. This event is called a "SetOn" event. If the channel SetOn event is FE, the new delays is loaded immediately.

A 100 Hz background vector interrupt is available. The interrupt is used to minimize the execution time of CAMAC functions. The 100Hz background interrupt service routine execute tasks that take more than 400 micro seconds to complete. Such tasks include loading delays to the Timer chip, testing periodically of LAM registers, and generating front panel Heart Beat light.

The C1091 comes with a battery backed RAM which contains a copy of the settings for all of the timer delays, TEV clock events, and counter enabling settings. The purpose of this battery is restoring the latest module settings on a reset or powerup, thus preventing the front-ends from having to re-enable the module.

The C1091 is equipped with jumper selected outputs. The user can select between TTL or NIM type output pulses. Front panel LEDs are also provided to indicate which of those levels have been chosen.

The C1091 has a `TEV' clock event decoder, which allows the decoding of 'TEV' clock events from either the P2 connector located on the CAMAC backplane or the Viking I/O connector. When connecting to the Viking I/O connector the 'TEV' clock signal has to have separate Clock and Data signal lines. See Appendix 'A' for Board Layout Drawing.

The C1091 has an RS232 interface which allows external communication with the Z8002 microprocessor by connecting either a terminal or personal computer to the serial I/O connector on the front panel of the module or to the Viking I/O connector located on the back. This serial communication is used to run the debug help menu shown in Appendix 'B'. The help menu can also be executed remotely by running the "Console Emulator" application program from any Vax terminal.

II. Hardware Description.

1. This module is controlled by a 16-bit general purpose Microprocessor (Zilog Z8002) which operates at a clock rate of 10MHz. Memory support consists of 32 Kbyte of EPROM and 32 kbyte of static RAM. All of the S-RAM is of the non-volatile battery backed variety.

2. A 4Kx8 wide dual ported RAM which is used to setup the events. This is accomplished by setting and resetting the word bits 0 - 7. Each bit corresponds to a channel number. Addresses B000 thru B1FF are used to set the channel events. Addresses B200 thru B3FF are used to set the channel SetOn events. See Appendix 'C' for a complete Memory Address Mapping.

3. The 8 channels of delayed outputs are controlled by four - AM9513A timing chips which are logically wired so as to concatenate two 16 bit counters creating one 32 bit counter. See Appendix 'D' for complete I/O Address Mapping

4. The CAMAC dataway interface consists of two 16-bit data latches--read and write functions. Camac functions are controlled by a EP1800J (CMCSLV) controller which requires processor intervention, to decode each Camac function's interrupt addressing vector.

5. Tevatron clock decoding circuitry allows for event decoding to enable counters. (All 256 TEV events are supported)

6. An 18 pin DIP jumper block is provided on the module. This is used to select either a TTL or a NIM level output pulse. All 8 outputs can be selected for either NIM or TTL levels.

7. To ensure software execution integrity a hardware heartbeat/reset feature is provided. It requires that bit #1 of address $FFB0 be set (by software) at a periodic rate. This edge retriggers a timeout counter in the micro-monitor I.C. (Dallas DS1232). Upon timing out this chip will assert the hardware reset line.

Note: When using an in-circuit emulator to single step this module the re-trigger signal has to be moved via a jumper to the `/AS' signal to prevent continuous resets from occurring.

8. The module provides two RS 232 ports. One is accessible through the I/O connector on the front panel of the module, and the other through the rear I/O connector The Baud rate is preset to 9600 BAUD, 8 Bits, 0 Parity using X-on/X-off handshaking.

As of this writing only the Front panel RS-232 connector is supported in the DEBUG software.

III Front Panel Features


RESET The reset button, when depressed, resets the processor, peripheral chips and other circuits. The CAMAC function F(9)A(0) activates the very same sequence (no processor intervention is required to do a remote reset.)


NIndicates the CAMAC crate controller has initiated a dataway cycle addressed to this module. This LED is stretched to 10 milliseconds to aid viewing.
LAM (Look At Me)Indicates the module is asserting the dataway LAM signal for this slot. The host must read the LAM source register, F(1)A(14), in order to identify the nature of the request. (See description of Camac Function F01A14.)
LAMENIndicates any unmasked bits in the LAM source register may cause module LAM to be asserted. When off, module LAM will never be asserted. LAM source bits, which are set by module firmware, are latched and may cause LAM to be asserted when the LAM is enabled, at some later time. F(24)A(0) and F(26)A(0) are provided to set the state of the LAM enable gate.
HRTBT (Heartbeat)Indicates loss of processor when not ON. This pulse is software generated through a interrupt which writes a memory location to keep the (Dallas DS1232) Micro-monitor from timing out.
CH 0 thru 7Indicate when an output channel has fired. This is approximately 500 millisecond and pulsed only once per delayed cycle.
TTLIndicates the logic level of which all 8 outputs are set to.
NIMIndicates the logic level of which all 8 output are set to.


CH0..CH7Lemo output connectors

IV CAMAC function Codes Supported

n represents channel number, where ( 0 <= n <= 7)
x represents Tev Clk event in hex, where (00 <= x <= FF)

The above notations are adopted throughout the description of the CAMAC functions.

Summary of Supported CAMAC Functions
F00A(0+2n) Read low word of channel n timing delay
F00A(1+2n) Read high word of channel n timing delay
F01A08 Read one word of channel events buffer
F01An Read SetOn event of channel n
F01A13 Read Lam Mask
F01A14 Read Lam Request Register:
F04An Read channel n status
F04A08 Read Module status
F06A00 Read Module Number
F06A01 Read Version Number
F06A03 Read FOP status
F06A04 Read FOP data
F06A05 Read card serial number
F08A00 Test LAM
F09A00 Module Reset
F10A00 Clear LAM
F16A(0+2n) Write low word of channel n timing delay
F16A(1+2n) Write high word of channel n timing delay
F17A08 Set pointer to read channel events
F17An Select a SetOn event for channel n
F17A13 Write LAM Mask
F17A14 Write LAM Request register
F18An Add event x to channel n
F19A02 Write FOP command
F19A03 Write FOP data to buffer
F21An Delete event x from channel n
F24An Disable channel n
F24A08 Disable all channels
F24A13 Disable LAM
F26An Enable channel n
F26A08 Enable all channels
F26A13 Enable LAM
F28An Delete all events from channel n

Detailed Explanation of Function Codes


Read low 16 bits of channel n timing delay. The value is returned from Battery Backed RAM. The read value may be different from the actual running value if this timing delay value has just been written and the SetOn event has not occurred yet. Such a situation could be verified by reading channel n status using F04An. The SetOn event signals the downloading of the new delay into the AM9513 Timer chip register (see description of F17An.)

The Battery Backed RAM contains the most recent to be set/read timing delays. The actual running value is the value that has already been loaded into the Timer chip.

Average execution time = 13.5 msec


This function code is the same as F00A(0+2n) except that it reads the high 16 bits of channel n timing delay.

Average execution time = 13.5 msec


Read one word of the Tev Clk events array and auto increment the global pointer for the next read. The global pointer is set using F17A08.

Word 1:
event 2 event 1

Word 2:
event 4 event 3

Word 3:
event 6 event 5

Word 4:
event 8 event 7

The events are returned as shown in ascending order (event 1 is the smallest.) Event values range from 0x00 to 0xFF except for 0xFE which indicates no event.

Average execution time = 24.2 msec


Read the SetOn event of channel n.

Average execution time = 13.2 msec


Read the LAM mask register. The format of this register is identical to the LAM source register (see description of F01A14.) A bit which is set in the mask register will enable the generation of a Module LAM due to a set bit in the LAM source register.

Average execution time = 13.0 msec


Read the 16 bit LAM source register. The register bits are defined as follows:

15..8Not Used 
7 Events Buffer Overflow of channel 7 These bits get set when trying to add a valid event to a channel that is already full. A channel can have up to a maximum of 8 events.
6 Events Buffer Overflow of channel 6
5 Events Buffer Overflow of channel 5
4 Events Buffer Overflow of channel 4
3 Events Buffer Overflow of channel 3
2 Events Buffer Overflow of channel 2
1 Events Buffer Overflow of channel 1
0 Events Buffer Overflow of channel 0

Average execution time = 13.0 msec


Read channel n status word. The status words are stored in Battery Backed RAM.

15..4Not Used
1- SetOn event is not active
0- SetOn event is active
1- Channel n has a pending timing delay to be added when SetOn event occurs
0- Channel n has no pending timing delay
1- Channel n events buffer is not full
0- Channel n events buffer is full
1- Channel n is Enabled
0- Channel n is Disabled

Average execution time = 13.1 msec


Read the module status word.

15..1Not Used
1- LAM is Enabled
0- LAM is Disabled

Average execution time = 13.0 msec


Read the module identification number. This function returns a decimal value of 1091.

Average execution time = 13.0 msec


Read the module firmware version number. A 16 bit value is returned. The major version number (release) is in the most significant byte. The minor version number, or modification level, is returned in the least significant byte.

Average execution time = 13.0 msec


Read FOP status word.

Average execution time = 13.0 msec


Read FOP reply data. Typecode specific data to be returned to the host.

Average execution time = 24.5 msec


Read the C1091 card serial number.

Average execution time = 13.0 msec


Tests module LAM. The Q response indicates whether the module is requesting LAM (Q=true) or not (Q=false). This function is implemented entirely in hardware and does not interrupt the embedded processor. Consequently, No-Q retries are not required. A single access always returns the proper status. Note that the returned status is completely unaffected by the state of the module's LAM enable gate. It is possible for this function to return Q (LAM pending) even though a LAM request to the crate controller has not been asserted.


Reset the C1091 module. This function always returns Q. It is implemented entirely in hardware and is equivalent to pressing the reset button on the module front panel. It causes the embedded processor to be reset. The ensuing program initialization may require several milliseconds to prepare the module for communicating with the outside world. Attempts at communication before reset is complete will result in No-Q.

During the initialization process, the following tasks are performed:


Clear the LAM source register. This function is the same as F17A14 with 0 data written.

Average execution time = 0.9 msec


Write the low 16 bits of channel n timing delay. The delay value is stored in Battery Backed RAM. The new value will not be loaded into the Timer registers until the SetOn event occurs. From the time the delay is put into the Battery Backed RAM to the time the SetOn event occurs, the channel will have a pending delay (see description of F04An.)

Average execution time = 3.7 msec


This function code is similar to F16A(0+2n) except that it writes the high 16 bits of channel n timing delay. Valid delay input is checked and corrected. The minimum delay a channel can be set to is 1 msec. Writing a 32 bit value of 0 timing delay will result in a delay value of 1 msec. The maximum delay is 0x7FFF FFFF. The MSB of the delay value is always stripped off resulting in 31 bit value. For example, writing a delay of 0x8777 FFFF will result in a delay value of 0x0777 FFFF.

Average execution time = 3.7 msec


Set the global pointer to read channel n. This pointer is auto incremented after each read made by F01A08 (see description of F01A08.) The pointer calculation is based on the write word. The contents of write word is defined as follows:

15..8Offset in bytes from the top of channel n events buffer.
7..0 Channel number (0-7)

Average execution time = 3.7 msec


Select the SetOn event of channel n. The selected event can be any Tev Clk event. It signals loading timing delay values into the Timer chip. It is recommended to choose an event that is not used to trigger channels. This is so because loading the Timer with a value would result first in disabling the Channel Timer. Therefore, the disabled channel will not be triggered. Events that might not be used to trigger channels are the ones that end the Cycle. When selecting a SetOn event of FE or FF, the new delays are loaded immediately.

Average execution time = 3.7 msec


Write the LAM Mask register. See description of F01A13.

Average execution time = 3.7 msec


Write the LAM Request register. See description of F01A14.

Average execution time = 3.7 msec


Add Tev Clk event x to channel n. A maximum of eight events are allowed to be added to one channel. When trying to add a valid event to a channel that has already eight channels, the excess will be ignored and a LAM will be turned ON if LAM Mask register is setup to generate a LAM for such a channel. A valid event is an event other than FE or FF and an event that is to be added for the first time. Repeat writing of an event will not result in duplicate entries.

Once an event is added to a channel that is enabled, this channel will be triggered by such an event when it occurs. But if the channel was already triggered by some other event and still counting down and this new event that was just added occurs, this new event trigger is ignored.

Average execution time = 3.7 msec


Write FOP command. This function is used to begin and/or end a command to the module's typecode processor.

Average execution time = 3.7 msec


Write FOP data to a temporary buffer.

Average execution time = 10.83 msec


Delete Tev Clk event x from channel n.

Average execution time = 3.7 msec


Disable channel n.

Average execution time = 0.9 msec


Disable all channels.

Average execution time = 0.9 msec


Disable LAM. LAM will not be asserted to the crate controller and will not cause LAMEN light on the module front panel to be turned ON.

Average execution time = 0.9 msec


Enable channel n.

Average execution time = 0.9 msec


Enable all channels.

Average execution time = 0.9 msec


Delete all events from channel n.

Average execution time = 0.9 msec


Enable LAM. The module may assert LAM to the crate controller and LAMEN light on the module front panel will be turned ON.

Average execution time = 0.9 msec

V. Fuseware

The circuit board uses programmable logic devices such as PLA's, PAL's and fusible link PROM's in order to reduce the total chip count. The logic equations are available for U7, U28, U37, U38, U40 and U41. All files are `.ADF' except U37 and U38. These file are `.ABL'. "example C1091U7.ADF". WARNER::USR$DISK1:[HDWDOCS.C1091]

V.1 Electronic Drawings

The Drawings for this module are separated into three (3) sheets. The names of these drawings are: 'PROC.SCH', 'CNTRS_8.SCH', 'CAMAC.SCH'. All these drawing were created using P-CAD.

The drawings can be found at https://www-bd.fnal.gov/controls/camac_modules/schematics/c1091_schematic.pdf

V.2 Power Requirements

The module conforms to ANSI Std 583 1982 as stated in Section 8 Power line standards. The module requires 6VDC at 3 amps.

VI. AM9513 Timer

The AM9513 Counter is the main backbone of the module. Once setup it automatically counts down to zero before delivering its output pulse.

There are a number of special feature incorporated into this module which the programmer should know about before attempting to write code.

VI.1 Counter Enabling

Counters must be enabled before any TEV clock events will activate the source pulses and the counter starts counting down. This is done by Writing an `1' to the address $FF80 thru $FF8F. $FF80 is output channel # 0 while $FF8F is channel # 7 (Word size addressing only). Disable counters by writing a `0' to the above addresses.

Once a counter has been enabled, and the countdown process has started, disabling the counters, as per above, WILL NOT prevent the current countdown sequence from occurring. The only thing that will stop the current countdown is when a new counter delay value is being written to the counter.

VI.2 Source Pulse Enabling

The source pulses are generated by U40 or U41 which are enabled by any valid TEV clock event. Once enabled the clock output connects directly into the source pulse inputs of the AM9513.

It is recommended the source pulse inputs be disabled before a new timer countdown value is entered into the counter. This can be done by writing to address $FF90. Data `0' stops sending source pulses to channel #0 while Data `7' will disable channel #7 source pulses. This only stops the source pulses during the current countdown cycle, the pulses will continue on the very next valid TEV clock event.

VI.3 Setting New Delay Values

As explained earlier we use four AM9513 chips per C1091 module, each of these chips has five individual 16 bit counters. By concatenating two of the counters together we create one 32 bit counter or a total of two delay channels per AM9513.

When writing a new delay value into the Am9513 the following steps must be followed:

1). Determine which one of the eight output channels to load

2). Set up addressing to write to that specific counter. See chart on next page.

3). Determine if it is the EVEN (0,2,4,6) or the ODD (1,3,5,7) group.

4). Set counter to 16 bit mode by writing data byte $FFEF to the Control and Status Register.

5). Disable Counters by writing data byte $FFC6 for even counters (2 & 3) or $FFD8 for odd counters (4 & 5) to the TMSCR register.

6). Get the 32 bit delay value and strip out the high byte so as to only have the low byte 16 bit value.

V Firmware Development

Code for the embedded processor is assembled and maintained on the Research Division's Controls Development VAX cluster, WARNER, using a Zilog Z8xxx cross assembler. Absolute output is Intel Hex format. Source and related files for the C1091 module are available on: WARNER::USR$DISK1:[HDWDOCS.C1091.SOFT]

Direct download of code over a VAX terminal line to an Applied Microsystems in circuit emulator is used for code check out and debugging. The test stand is also equipped with an IBM/AT to exercise module functions via a C1000 CAMAC crate controller.

V.1 Firmware Help Menu

A Help directory is available through the RS232 Ports consisting of:
HEDisplay Help Menu
HLHex Load (Intel)
DM Display Memory (byte) <address> or <start address> <stop address>
DW Display Memory (word) <address> or <start address> <stop address>
GO Go to execute at nn
OM Output to Memory
DR Display Registers
SM Substitute Memory (byte)
SW Substitute Memory (word)
RC Read all Counter Values off the timers <32 Bit Read> & Display Status
SD Set Counter Delay Channel# <N> <Hi Wrd> <lo Wrd>
RE Read (from DP-RAM) & Display all Events
SE Set Counter Event - Event# <Hex Byte> - Channel#
CE Clear Counter Event - Event# <Hex Byte> - Channel#
CA Clear all events form a channel - Channel#
RS Read (from DP-RAM) & Display SetOn Events
LS Load SetOn - Event# <Hex Byte> - Channel#
EC Enable Counter # (N) or (A)= all
DC Disable Counter # (N) or (A) = all

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