Controls Hardware Release No. 26.5

                                   CAMAC 190 Module

                          Multimode Buffered MADC Controller

                             A. D. Thomas, J. J. Gomilar,
                          W. R. Knopf, and J. G. Smedinghoff

                                    April 22, 1988

               The CAMAC  190  module  provides  intelligent  interface
               support  for  Fermilab-standard,  multiplexed  analog to
               digital converters, MADC's.   Both  the  older  DSE  and
               newer  in-house  12-bit  MADC  versions  are  supported.
               14-bit ADCs interfaced via 1553B  and  a  companion  192
               module  are  also  supported.   The  module will support
               future MADC's with resolutions up  to  16  bits.   Timed
               collection  of  lists  of multiple channels and buffered
               collection of single channels is supported.
                                                         CAMAC 190 Module: V1.17


                  1       GENERAL DESCRIPTION  . . . . . . . . . . . . . . . . 1
                  2       SUMMARY OF FEATURES  . . . . . . . . . . . . . . . . 1
                  3       GENERAL ARM AND SAMPLE TRIGGERS  . . . . . . . . . . 1
                  4       PLOTS  . . . . . . . . . . . . . . . . . . . . . . . 2
                  4.1       Sample Triggers, All Plot Modes  . . . . . . . . . 2
                  4.2       Plot Mode A, Continuous Recording  . . . . . . . . 2
                  4.3       Plot Mode B, Post-trigger Recording  . . . . . . . 3
                  4.4       Plot Mode C, Pre-trigger Recording . . . . . . . . 4
                  4.5       Fast And Superfast Plots . . . . . . . . . . . . . 5
                  5       LISTS  . . . . . . . . . . . . . . . . . . . . . . . 5
                  6       ALARM MONITORING SYSTEM  . . . . . . . . . . . . . . 6
                  7       TIME STAMPS  . . . . . . . . . . . . . . . . . . . . 7
                  8       PROGRAMMING CONSIDERATIONS . . . . . . . . . . . . . 8
                  8.1       Writing Data To The Module . . . . . . . . . . . . 8
                  8.2       Reading Data From The Module . . . . . . . . . . . 9
                  9       FUNCTION CODES AND DATA FORMATS  . . . . . . . . .  10
                  10      SUGGESTED PROGRAMMING SEQUENCES  . . . . . . . . .  21
                  10.1      Setting Up A List  . . . . . . . . . . . . . . .  21
                  10.2      Setting Up A Plot  . . . . . . . . . . . . . . .  22
                  11      DIAGNOSTIC PROTOCOL, FOP . . . . . . . . . . . . .  22
                  12      MODULE HARDWARE DESCRIPTION  . . . . . . . . . . .  27
                  12.1      CPU, Board A . . . . . . . . . . . . . . . . . .  27
                  12.1.1      CAMAC Function Decoder . . . . . . . . . . . .  28
                  12.1.2      Accelerator Clock Interface  . . . . . . . . .  29
                  12.1.3      External Interrupt Inputs  . . . . . . . . . .  29
                  12.2      I/O Processor, Board B . . . . . . . . . . . . .  30
                  12.2.1      8089 I/O Processor . . . . . . . . . . . . . .  30
                  12.2.2      CPU To IOP Communication . . . . . . . . . . .  30
                  12.2.3      Other B-board Peripherals  . . . . . . . . . .  31
                  12.3      Address Spaces . . . . . . . . . . . . . . . . .  31
                  12.4      MADC Access Arbitration  . . . . . . . . . . . .  31
                  12.5      Front Panel Features . . . . . . . . . . . . . .  32
                  12.6      I/O Connector Definition . . . . . . . . . . . .  34
                  13      DIGITIZER INTERFACE CHARACTERISTICS  . . . . . . .  35
                  14      MODULE FIRMWARE DESCRIPTION  . . . . . . . . . . .  36
                  14.1      The Division Of Labor  . . . . . . . . . . . . .  36
                  14.2      CPU  . . . . . . . . . . . . . . . . . . . . . .  36
                  14.2.1      Data Collection State Sequencer  . . . . . . .  36
                  14.2.2      Low Priority Tasks . . . . . . . . . . . . . .  36
                  14.2.3      Reduction Of Interrupt Service Overhead  . . .  37
                  14.2.4      List Data Collection . . . . . . . . . . . . .  37
                  14.2.5      Debugger Program . . . . . . . . . . . . . . .  37
                  14.3      I/O Processor  . . . . . . . . . . . . . . . . .  38
                  14.3.1      I/O Channel 1  . . . . . . . . . . . . . . . .  38
                  14.3.2      I/O Channel 2  . . . . . . . . . . . . . . . .  38
                  14.4      Firmware Development Environment . . . . . . . .  38
                  15      FUSEWARE . . . . . . . . . . . . . . . . . . . . .  39

          CAMAC 190 Module: V1.17


                  A.1     DATA COLLECTION RATES  . . . . . . . . . . . . . . A-1
                  A.2     SUMMARY OF FUNCTION CODES  . . . . . . . . . . . . A-2
                  A.3     FOP FUNCTION SUMMARY . . . . . . . . . . . . . . . A-3
                  A.4     DEBUGGER COMMANDS  . . . . . . . . . . . . . . . . A-3
                  A.5     BIBLIOGRAPHY . . . . . . . . . . . . . . . . . . . A-5
                  A.6     FRONT PANEL LAYOUT . . . . . . . . . . . . . . . . A-6
                                                     CAMAC 190 Module: V1.17


               The CAMAC 190 module provides intelligent  interface  support
          for  Fermilab-standard,  multiplexed analog to digital converters,
          MADC's.  Both the older DSE and newer in-house MADC  versions  are
          supported.  The module will support future MADC's with resolutions
          up to 16 bits.


                -  Six channels of time-stamped recording in any combination
                   of  pre-trigger,  post-trigger,  or continuous collection
                   mode    with     elastic     buffering.      Simultaneous
                   non-interfering  collection  on  all six plot channels to
                   1.6 KHz per channel.  Single channel  rates  to  ~70  KHz
                   depending on MADC conversion rate and operating mode.

                -  Eight lists of time-stamped readings of all channels  (or
                   a   contiguous   subset   of  channels)  collected  at  a
                   specifiable time.

                -  Alarm monitoring of any data collected in list mode.

                -  Dual-level triggering  of  all  modes  (arm  and  trigger
                   style)  utilizing  combinations of external inputs, coded
                   clock events and programmable internal rate generators.

                -  Internal decoding of events on  the  10  MHz  Accelerator

                -  Data read at the full block transfer rate of the  10  MHz
                   serial CAMAC link (~285 KW/sec).

                -  Full support for MADC's with up to 128 analog inputs  (or
                   two  64-channel  units  with  the  addition  of  external
                   multiplexing hardware).


               All data collection  performed  by  the  module  is  tied  to
          hardware  events.   Most  collection  modes  make use of an ARMing
          signal which enables Sample Triggers.  Data is  collected  on  the
          occurrence  of  a  subsequent  Sample  Trigger.  This scheme makes
          possible  the  use  of  periodic  signals  for  generating  Sample
          Triggers without the need for external gating circuitry.  A number
          of general purpose signals may be selected for use as  either  Arm
          Sources  or  Sample  Triggers.   The  following  are available for

          CAMAC 190 Module: V1.17

          unrestricted use as Arm and Sample Trigger sources:

                -  Any of seven independent clock decoder sources where each
                   clock  decoder  source may be programmed to become active
                   on the logical OR of any combination of the 256  possible
                   clock events.

                -  Any of 4 external input signals.

          These are completely general in that any source may  be  specified
          as  an Arm Source or Sample Trigger by any combination of plot and
          list collection functions without  restriction.   A  given  source
          signal  may  be defined as an Arm Source for one or more functions
          while the same source signal may be defined as  a  Sample  Trigger
          for  one  or  more  functions.  The same source signal may even be
          defined as the Arm Source and the  Sample  Trigger  for  the  same
          function (not clear how useful this would be).

          4  PLOTS

               The module supports data collection for six "plot  channels".
          Except  for contention to the single ADC unit the operation of all
          plots is identical.  Logically a  plot  is  a  program  collecting
          time-stamped  data from a single MADC input and placing the values
          in memory for later retrieval over the  dataway.   Plot  data  are
          always  collected as ordered pairs in (time-stamp,reading) format.
          Appendix A contains state diagrams for data collection modes.

          4.1  Sample Triggers, All Plot Modes

               A data point will be gathered  for  each  occurrence  of  the
          selected  Sample  Trigger.   The  Sample  Trigger  source  may  be
          programmed to be any one of the general arm and trigger signals or
          ___  ______  __  _  _________  ________  ____ __________
          the  output  of  a  dedicated  internal  rate generator.  The rate
          generator operates asynchronous to the accelerator clock  and  the
          power  line and may be programmed to any period from 140 usec (7.1
          KHz) to .655 seconds (1.52 Hz) with 10 usec resolution.  (See  the
          section on timing for more detail on total bandwidth.)

          4.2  Plot Mode A, Continuous Recording

               In this mode of operation the program collects one data point
          on  the  occurrence  of each Sample Trigger which occurs after the
          selected arming event and places  it  in  a  circular  2048  point
          buffer  in  memory.  The host processor may read the buffer at any
          time and  obtain  all  previously  recorded  unread  data  points.
       |  Sixteen  data  retrieval  pointers  are  provided  for  each  plot

                                                     CAMAC 190 Module: V1.17

       |  channel, so it is possible to read the plot  data  multiple  times
       |  independently.   A  given  data point will only be returned to the
       |  host once for a given data retrieval pointer.  This  mode  implies
          that the host will empty the accumulated data points in the buffer
          at an average rate fast enough to avoid losing any.  If the buffer
          is allowed to overflow then the oldest data points are overwritten
          by newer ones.

               Data collection is armed on the occurrence  of  the  selected
          Arm Source.  The Arm Source may be programmed to be any one of the
          general arm and trigger signals or  "immediate".   "Immediate"  is
          considered  the time at which the CAMAC command specifying the Arm
          Source is received.  Until the selected Arm Source goes active all
          Sample Triggers will be ignored.  Immediate arming is probably the
          most useful for this  mode.   Once  armed,  data  collection  will
          continue  until  new  plot  specifications  are transmitted to the
          module without regard to whether the acquired data is ever read.

          4.3  Plot Mode B, Post-trigger Recording

               Data collection is armed on the occurrence  of  the  selected
          Arm Source.  The Arm Source may be programmed to be any one of the
          general arm and trigger signals or  "immediate".   "Immediate"  is
          considered  the time at which the CAMAC command specifying the Arm
          Source is received.  Until the selected Arm Source goes active all
          Sample Triggers are ignored.

               Once the Arm Source has become active the module will collect
          one data point on the occurrence of each Sample Trigger and places
          it in a linear 2048 point buffer in memory.  Special efforts  have
          been  made  to  ensure  that the first time-stamp will be recorded
          within a few milliseconds after the arming event  plus  any  delay
          time.   As  a  result,  the  first  data point will contain only a
          time-stamp.  Its associated data value  will  be  invalid.   Under
          normal conditions of module loading, if no delay is specified, the
          first time-stamp will be about 90 microseconds  after  the  arming
          event.   The  host  processor  may read the buffer at any time and
       |  obtain all the data points recorded up to  that  time.   The  host
       |  processor may also at any time reset the data retrieval pointer in
       |  use and thus reread the data from the beginning (see F19A5).  When
          2048  points  have  been collected, a status bit in the LAM source
          register is set and  data  collection  stops.   Additional  Sample
          Triggers  are  ignored  until  the  selected Arm Source once again
          becomes active.  If the Arm Disable option is selected, then  even
          subsequent  Arm  Source  signals are ignored until the last of the
          2048 collected points has been read from the buffer.

               Optionally, a programmable delay between the Arm Source event
          and the collection of the first data point may be specified.  This
          delay is specified in milliseconds.

          CAMAC 190 Module: V1.17

       |       The plot channel status word (F6A6) may be read to see if the
       |  plot  is waiting for an arm, waiting for a delay, collecting data,
       |  or inactive.

          4.4  Plot Mode C, Pre-trigger Recording

               This mode of data collection is distinctly different from all
          other  modes.  Upon receipt of the command to collect data, a data
          point will be collected on the occurrence of each  Sample  Trigger
          and  placed in a circular memory buffer.  This state will continue
          until the selected Arm Source  goes  active.   At  that  time  the
          module  will accept an additional N Sample Triggers (controlled by
          the Sample Delay parameter) and then  stop.   As  with  the  other
          modes  of  operation, the module may be optionally directed not to
          resume data  collection  until  a  new  F17  command  is  written.
          Operation  in mode C makes very little sense unless this option is
          always selected (since there would  only  be  a  very  brief  time
          during  which  the host could read the collected data).  This mode
                                         ______  ___  ______  ______
s          allows a history of  readings  before  the  arming  signal  to  be
          retained  in  memory.   (Note  that  a  sample  delay  of  2048 is
          logically equivalent to operation in mode B.  In reality, however,
          it  uses  far more of the module's resources than simply selecting
          mode B to begin with.)

               This is a common mode of data  collection.   The  only  thing
          that  is  somewhat  confusing  is  the  fact that the signal which
          causes data collection to (eventually) stop is named "arm".   This
          apparent  contradiction  exists  only  to provide consistency with
          nomenclature for all other modes of operation  when  communicating
          with the module.
       |       As soon as the arm event  happens,  any  previoulsy  recorded
       |  data  is  made  available  for reading by the host processor.  The
       |  host processor may also at  any  time  reset  the  data  retrieval
       |  pointer  in  use  and thus reread the data from the beginning (see
       |  F19A5).
       |       It is possible that fewer than 2048 points will be collected.
       |  This  can  happen  if the arm event happens before 2048 - N points
       |  are collected.  In order to give the host  enough  information  to
       |  figure  out  what  has happened, the first data point will contain
       |  the time stamp of the arm event and the offset (in bytes) from the
       |  beginning of the buffer to the first point collected after the arm
       |  event.
       |       The plot channel status word (F6A6) may be read to see if the
       |  plot is waiting for an arm, collecting data, or inactive.

.                                                     CAMAC 190 Module: V1.17

          4.5  Fast And Superfast Plots

               The  three  plot  modes  discussed  above   can   be   active
          simultaneously in any combination on all six plot channels.  While
          data is not actually collected simultaneously, the  data  requests
          for  the  six different plot channels are interleaved (round robin
          fashion).  This results  in  graceful  degradation  as  the  total
          requested  plot  data  rate  approaches saturation.  Significantly
          improved data rates are possible if the user is willing  to  allow
          the  total  suspension of service of five of the plots in favor of
          100% utilization by the remaining plot.   The  module  allows  two
          such  optimized collection rates, fast and superfast.  They may be
          optionally  specified  only  for   plot   mode   B   (post-trigger
          recording).   Both rates are dependent upon the conversion rate of
          the MADC.  Selecting the fast or superfast  conversion  rate  does
          not  change  the  arming or data readout characteristics of mode B
          operation.  These high speed modes of operation are  selected  via
          the F19An functions.

               Also, the operation of the other plots is not disturbed until
          the  arm and delay requirements for a fast or superfast collection
          have actually been satisfied.  Once satisfied  though,  plot  data
          will only be collected for that plot.  After 2048 points have been
          collected,  normal  interleaved  plot   operation   will   resume.
          Additional information on data rates may be found in Appendix A.

          5  LISTS

               The  module  supports  data  collection  for  eight  "lists".
          Except  for  contention  to  the  single ADC, the operation of all
          lists is identical.  Logically, a list  is  a  program  collecting
          time-stamped  data  from  consecutive  MADC inputs and placing the
          data in memory for later retrieval over the dataway.  List data is
          always  collected as ordered pairs in (time-stamp,reading) format.
          Appendix A contains state diagrams for data collection modes.

               Like the plots described above,  lists  use  two  signals  to
          coordinate data collection -- they may also use fewer:

               1.  A list may be collected immediately on the occurrence  of
                   the selected Arm Source.

               2.  A list may be collected on the Nth Sample Trigger after a
                   selected Arm Source.

               3.  A list may be collected N milliseconds after  a  selected
                   Arm Source.

          The selected Arm Source may also be specified  as  "immediate"  in
          which  case  options  1  and  2 above are relative to the time the
          CAMAC command specifying arm and trigger conditions is received.

          CAMAC 190 Module: V1.17

               As with  plots,  subsequent  Arm  events  may  be  optionally
          ignored  until all list data has been read by the host.  List data
          acquisition  is  always  interleaved   with   any   ongoing   plot
          collection, including fast and superfast plot collection.


               Monitoring of list data is supported.  Each  channel  reading
          of  each  list  may  be  monitored independently.  MADC values are
          considered to be signed two's  complement  numbers  by  the  alarm
          monitoring  system.   Alarm  blocks  describing the list, channel,
          minimum  and  maximum  alarm  limits  and  other  information  are
          downloaded  by  the  host using a FOP function, FTC006.  The alarm
          system is reset using the F24A1 function.  Each  time  a  list  is
          collected an alarm scan for that list will be requested.  Only the
          channels actually collected can be monitored.   Alarm  blocks  for
       |  channels  which  are  not  being collected are simply ignored.  An
       |  alarm block which is bypassed is considered  to  be  in  the  good
       |  state.   For  each alarm transition (good to bad or bad to good) a
          one word alarm report message will be placed in a circular message
       |  buffer  and  a  bit in the LAM source register will be set.  Alarm
       |  transitions can result from the alarm system seeing a change in an
       |  MADC  channel's value or from the host processor downloading a new
       |  alarm block.

               The host reads  the  alarm  reports  via  a  dedicated  CAMAC
          function  code, F6A5.  When the alarm message buffer is emptied of
          the last message, the LAM source bit will be cleared.  The  format
          of  the alarm message allows it to be used, unmodified, to perform
          a single-channel read (F16A0, F1A2 sequence) to obtain the current
          reading  of  the  channel  from  the data list associated with the

               Since the bottom four bits of the collected analog  data  may
          represent different things depending upon module configuration and
          the resolution of the connected MADC, it is necessary for the host
          to  tell  the  module (via FOP type code 008) how many bits to use
          when checking data against the alarm block values.


                                                     CAMAC 190 Module: V1.17


             Length     Symbolic
            (bytes)       Offset
            ----------  --------
                                  15      11    8 7 6           0
                2       ABCHAN   |x|x|x|x| List# |x|  Channel #  |
                2       ABFLAG   | | | |H|L| | | | | | | | | |G|B|
                2       ABMIN    |        minimum value          |
                2       ABMAX    |        maximum value          |
                2       ABHYST   |  tries_needed |  tries_now    |

                  HI      Set if reading is too high.
                  LO      Set if reading is too low.
                  GB      alarm state good (0) or bad(1)
                  BP      alarm bypassed (bit value of 0) and will not generate alarms
                  x       unused bit, will be remembered by the module

               Tries_needed and tries_now are unsigned bytes that  are  used
          to  provide  alarm  hysteresis.   The  alarm  system must detect a
          channel  reading  to  be  in  the  other  state  (bad   or   good)
          "tries_needed"  consecutive  alarm scans before it will change the
          good/bad bit and output an alarm message.  A tries_needed value of
          zero  will  behave  the  same  as a value of one.  Tries_now is an
          internal counter used to keep track of the number  of  consecutive
          scans in the other state.


                                   15      11    8 7 6           0
                2       ABCHAN   |G| |H|L| List# | |  Channel #  |
                                 |B|x|I|O| (1-8) |x|   (0-127)   |

          7  TIME STAMPS

               In order to properly position  collected  data  in  time  the
          module  always  collects  a time-stamp with every data point.  The
          time-stamp is  usually  derived  from  the  accelerator  clock  by
          dividing by a fixed prescale value.  The rate is jumper selectable
          from 100 Hz to 100 KHz.  This periodic  signal  is  counted  by  a
          simple  20-bit  counter which can be read by module firmware.  The
          act of reading the time-stamp register triggers a MADC  conversion

          CAMAC 190 Module: V1.17

          cycle.  This results in the time stamp very closely reflecting the
          actual data sample  time  (the  MADC  is  equipped  with  its  own
          internal  sample  and  hold).   A  more  quantitative  description
          requires detailed knowledge of any multiplexer settling delays  in
          a particular MADC.  In order to provide global synchronization the
          counter can be reset by any selected clock  event(s).   A  special
          clock decoder signal is provided for this purpose.

               Sixteen bits of time-stamp count are always read  whenever  a
          time-stamp is collected.  Up to four additional high order bits of
          the time-stamp scaler may be jumper selected to be returned in the
          least  significant  bits of the MADC data word.  Zero through four
          additional bits may be selected (to accommodate 14 or 16 bit  ADCs
          or  other  devices).  The resulting 32-bit longword representing a
          (time-stamp,data) pair as it would  appear  in  PDP-11  memory  is
          shown  below.  The bits shown as X are the optional bits which may
          be strapped to provide additional time-stamp range or  for  higher
          resolution MADC's.

                  second word returned           first returned word
             |       signed       | | | | |           16 bits of        |
             |     MADC data      |x|x|x|x|       time-stamp reading    |
              31                20         15                          0

               In applications where the accelerator clock is not  available
          an alternate on-board oscillator may be selected as the time-stamp
          source.  In this case there  is  no  global  significance  to  the
          returned  time stamp value.  This mode of operation is discouraged
          for all ACNET subsystems.  It is selected by a  jumper  option  on
          the A board.


               ____ __ _________                                    ________
                THIS IS IMPORTANT!  Programmers who must communicate directly
          with the 190 module should thoroughly understand the two I/O rules
          stated below.  Those readers not having  to  communicate  directly
          with the 190 module may wish to skip the section.

          8.1  Writing Data To The Module

n                                        Rule 1

                  A write operation must be retried until the module
                  returns a valid Q response.

n                                                     CAMAC 190 Module: V1.17

               If the module is idle at the time the command arrives, Q will
          be  returned and the module will begin processing the command in a
          few microseconds.  If the module is busy with some non-CAMAC chore
          at the time the write command arrives, then Q will be returned and
          the command and data stored in a one-deep buffer.  The module will
          begin  processing  the command as soon as possible.  If the module
          has not begun processing the buffered command and data by the time
          yet  another  write command arrives, then ~Q will be returned.  In
          such a  case  this  last  write  command  must  be  re-transmitted
          periodically  (at  some  convenient  rate).  Note that Accelerator
          Division CAMAC hardware has been designed  with  Q-retry  hardware
          for this very purpose.

               For purposes of communication, the control functions F24  and
          F26 are treated as data write commands.

          8.2  Reading Data From The Module

                                         Rule 2

                  A read operation must be retried until a  valid  Q
                  response is returned.

               Beginning  with  firmware  version  1.12,  it  is  no  longer
          necessary,  when emptying a data buffer, to read the entire buffer
          at once (without any  intervening  different  function  codes)  to
          avoid losing data.  A read operation (on a function code different
          from the last) will always return at least one ~Q response.   This
          is  because  the  module cannot respond with the requested data in
          the 200 nanoseconds required by the CAMAC  dataway  protocol.   In
          the best of cases (module is idle at time read request arrives) 10
          to 15 microseconds is required to return data.  If the  module  is
          busy with data collection or other work then the read request will
          not be processed as quickly.  Also, the F0 read functions  require
          the  module to initialize a DMA channel.  This requires additional
          time (though once set up the DMA is fairly rapid).

               There is an additional restriction when reading from  the  F0
          function codes.  The modified rule states:

                                        Rule 2A

                  When reading  from  F0  function  codes,  an  even
                  number  of  words must be read as a group, without
                  any intervening different function codes.

          Note that both the plot and list data collection mechanisms always
          make  data  available  to  be  read  via  the F0 function codes in
          multiples of 2 words.  If an odd number of words is read  from  an

          CAMAC 190 Module: V1.17

          F0 function and a different function code is executed, then a word
          of data may be lost  once  the  F0  reads  resume.   This  can  be
          disastrous when expecting data as ordered pairs.


          9.1  F0An

          Read data in (TimeStamp, Reading) format.  Data for lists  1-8  is
          available on subaddresses 1-8.  Plot channel data for plots 1-6 is
          available on subaddresses 9-14.  An even number of words  must  be
          read  in  order to avoid losing data.  Both the plot and list data
          collection mechanisms always make data available  to  be  read  in
          multiples  of  2  words.   The format is as described above in the
       |  time stamps section.  The most recently  selected  data  retrieval
       |  pointer is used to access the data.  See the F19A5 description for
       |  more information on data retrieval pointers.

          9.2  F1A0

          Read  16-bit  LAM  source  register.   This  allows  the  host  to
          determine  the source of all service requests in the module with a
          single read operation.  Additional status is  available  on  other
          function codes.  The register is organized as follows:

          | A | P | P | P | P | P | P | L | L | L | L | L | L | L | L | E |
          | R | 6 | 5 | 4 | 3 | 2 | 1 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | X |
           15  14  13  12  11  10   9   8   7   6   5   4   3   2   1   0

          AR      Indicates, when set, that there are Alarm Reports waiting

          Pn      Indicates, when set, that buffered channel (plot) data and
                  time stamps are available to the host

          Ln      Indicates that list data and time stamps are available

          EX      Indicates, when set, that at least one bit is set  in  the
                  extended LAM register.

          9.3  F1A1, Read LAM Mask Register

          Bit definitions are identical to the LAM source register.   A  bit
          which  is  set  in  the  mask register will permit generation of a
          module LAM due to that LAM source.  Other bits will  not  generate
          LAM.   The  state  of  the bit as read by the F1A0 function is not

s                                                     CAMAC 190 Module: V1.17

          affected.  (In a polling application all bits might be masked  off
          but  the  status  is  still  accurately  tested by reading the LAM
          source.) In applications  using  a  TeVatron  serial  CAMAC  crate
          controller (TSCC) it is also possible to poll the concentrated LAM
          status from the crate controller.  At module reset, the  LAM  mask
          register is initialized to FFFF (hex).

          9.4  F1A2, Read Single Channel Data

          The module will return the data requested by  the  previous  F16A0
          command.   A  time-stamp  is  never returned on this function code
          (see F1A3).  If list #0 was specified by the  F16A0  command  then
          the   selected   channel   will   be   digitized  and  the  16-bit
          left-justified result will be returned  to  the  host.   On  first
          occurrence  ~Q  will  be  returned,  it  is necessary to retry the
          operation (without any  intervening  commands  to  other  function
          codes)  until a valid Q response is returned.  After a Q response,
          the module will point to the  next  (sequential)  channel  if  the
          autoincrement  feature  was  not  suppressed in the F16A0 command.
       |  The next channel will not actually  be  digitized  unless  another
       |  F1A2  function  is  executed.   At  that  time  another ~Q will be
       |  returned and retrys will be needed.  This is  different  than  all
       |  other  read  functions and F1A2's for lists 1 to 8, which prefetch
       |  the next data word to be returned.

          If the list number in the last F16A0 command was in the range 1 to
          8  then  the  module  will attempt to return the requested channel
          reading at  the  time  that  list  was  last  collected.   If  the
          collection  parameters  for  the list do not include the requested
          channel  then  ~Q  will  be  returned  (perpetually).   Also,  the
          specified  list  of  channels must actually have been collected at
          some previous time.  Otherwise, ~Q will  be  returned  until  such
          time as the list in question is actually collected.

          In both cases the low order four  bits  of  the  return  word  are
          defined  by  PC  board jumpers and may represent ADC data for high
          resolution MADCs or up to four additional high order bits  of  the
          time stamp counter.

          Time from CAMAC 'N' to data return is ~30 usec w/o contention  for
          an 11 usec MADC (list 0) and ~36 usec for lists 1 to 8.

          9.5  F1A3, Read Single Channel Time Stamp

          The module returns the 16-bit time stamp associated with the  data
          returned  by  the last single channel read to F1A2.  It is correct
          whether the reading was from a list in memory or a digitize  (list
          #0).  The readout is non-destructive, subsequent reads will return
          the  same  value  (until  after  another  F1A2  is  issued).   The

          CAMAC 190 Module: V1.17

          resolution of the time stamp value is jumper selectable and may be
          obtained from F6A2.

          9.6  F1A6, Read Extended LAM Source Register

          This allows the host to  determine  the  source  of  all  extended
          service  requests  in the module with a single read operation.  If
          any of these bits is set, indicating an extended service  request,
          then  the  least  significant bit of the basic LAM source register
          will also be set.  This allows the host to poll  for  all  service
          requests by examining the basic LAM source register.  The register
          is organized as follows:

          |   |   |   |   |   |   |   |   |   |   |   |   |   |   | I |   |
          | N | N | N | N | N | N | N | N | N | N | N | N | N | N | B | N |
          | D | D | D | D | D | D | D | D | D | D | D | D | D | D | R | D |
             15  14  13  12  11  10   9   8   7   6   5   4   3   2   1   0

          ND      These bit positions are not currently defined though  they
                  may be used for various development and debugging purposes
                  by the module developers from time to time.  New  features
                  may also make use of them.  Production applications should
                  ignore them (by masking them off).

          IBR     I've Been Reset.  Indicates, when set, that the module has
                  been  reset.   The  source  of the reset may have been the
                  front panel switch, the host  processor  via  the  dataway
                  (F9A0  or  explicitly  requested  Z-  cycle  to  the crate
                  controller) or the internal power-up sequence.

          9.7  F1A7, Read Extended LAM Mask Register

          The format is identical to the EXTENDED LAM source register  shown
          in  the  description  of F1A6.  A bit which is set in the extended
          mask register will permit generation of a module LAM due  to  that
          extended LAM source.  Other bits will not generate LAM.  The state
          of the bit as read by the F1A6 function is not affected..   (In  a
          polling  application,  all  extended  and/or basic LAM source bits
          could be masked off but the status is still tested by reading  the
          LAM  source.)  At  module reset, the EXTENDED LAM mask register is
          initialized to FFFF (hex)

          9.8  F6A0, Read Module ID

          The module will return its  assigned  identification  number,  190

-                                                     CAMAC 190 Module: V1.17


          9.9  F6A1, Read Firmware Version Number

          A 16-bit value is returned to the requestor.   The  major  version
          number  (release)  is  in  the  most  significant byte.  The minor
          version number, or modification level, is returned  in  the  least
          significant byte.  By convention these two values are displayed in
          a (pseudo) floating point format with each byte displayed in radix
          10  separated  only  by  a  decimal  point.   For  example  a most
          significant byte of value 1 and a least significant byte of  value
          17  would be displayed as '1.17'.  This is the same format used in
          the module sign-on message to the serial port (if the  conditional
          debugging  code  has  been  selected).  The module guarantees that
          both bytes will always be in the range 0-99 (decimal).

          9.10  F6A2, Read Module Configuration/status

          Read 16-bit module configuration/status word.

                  |     not   | L| L| TSP |         CVT           |
                  |   defined | E| C|     |                       |
                   15          12 11 10  8 7                     0

       |  LE      LAM is currently enabled
          LC      MADC is currently in Local Control mode
          TSP     Time stamp period measured at module reset:
                   0=  10 usec
                   1= 100 usec
                   2=   1 msec
                   3=  10 msec
                   4= no clock present at module reset

          CVT     MADC conversion time (in microseconds)  averaged  over  20
                  samples at module initialization.  If the MADC is in LOCAL
                  at the time the module is initialized, then this value  is
                  set to FF (hex).

          9.11  F6A5, Read Alarm Message

          Read Alarm Report messages from the module's  alarm  system.   The
          messages  are  one  word  long.  This word may be passed unaltered
          back to F16A0 in order to set up a read of  the  list  data  which
          generated the alarm message.  The data would then be read on F1A2.

          CAMAC 190 Module: V1.17

       |  9.12  F6A6, Read Plot Channel Status Word
       |  Read plot channel status word.  Two bits of  status  are  reported
       |  for each plot channel.
       |          +--------------------------------------------------+
       |          |      not     | PS6 | PS5 | PS4 | PS3 | PS2 | PS1 |
       |          |    defined   |     |     |     |     |     |     |
       |          +--------------------------------------------------+
       |           15         12  11 10  9  8  7  6  5  4  3  2  1  0
       |  PS1-6   Plot channel state:
       |           0= plot channel inactive (data collection cancelled  OR
       |              data collection finished in plot mode B or C)
       |           1= waiting for arm event
       |           2= waiting for time delay (plot mode B only).
       |           3= data collection in progress and previously collected
       |              data is available for readout.
       |  9.13  F6A7, Hardware Diagnostics Read
       |  This  function,  in  conjunction  with  F16A15,  provides  a  read
       |  function  of  programmable speed, which returns known data.  After
       |  the execution of an F16A15 function, F6A7  will  return  zero  and
       |  increment  on  each successive execution.  The data sent to F16A15
       |  determines how long it takes to execute future F6A7's.

          9.14  F8A0, Test Module LAM

          The Q response indicates whether  the  module  is  requesting  LAM
          (Q=true)  or not (Q=false).  This function is implemented entirely
          in  hardware  and  does  not  interrupt  the  embedded  processor.
          Consequently, ~Q retries are not required.  A single access always
          returns the proper status.   Note  that  the  returned  status  is
          completely  unaffected  by  the  state  of the module's LAM enable
          gate.  It is possible for this function to return Q (LAM  pending)
          even  though  a  LAM  request to the crate controller has not been

          9.15  F9A0, Reset Module

           This function always returns  Q.   This  function  is  implemented
          entirely  in  hardware  and  is  equivalent  to pressing the reset
          button on the module front panel.  Among other  things  it  causes
          the   embedded  processors  to  be  reset.   The  ensuing  program
          initialization may require as much as 100 milliseconds to  prepare
          the  module for communication with the outside world.  Attempts at

w                                                     CAMAC 190 Module: V1.17

          communication before the reset sequence is complete will result in

          9.16  F16A0, Select Single Channel For Read

          Write channel number and list number for subsequent single channel
          reads.   The  module  accepts a 16-bit data word from the dataway.
          It controls the operation of the  module  when  subsequent  single
          channel read commands are received (F1A2).  It is of the form:

                  |N|           | List #   | | selected channel #  |
                  |I| x | x | x |  (0-8)   |x|     (0-127)         |
                  15 14  13  12  11       8 7 6                   0
          Bit #   Definition

             x    contents ignored

             15   NI, when set specifies that the selected channel value  is
                  not auto-incremented after each conversion.  If clear, the
                  channel number will increment after each F1A2 read (up  to
                  127 and then wrap-around to channel zero).

          List numbers 1 to 8 refer to data collected  for  lists  1  to  8.
          Specifying  a  list number of zero will cause the selected channel
          to be digitized on receipt of a subsequent F(0)A(2) read.

          9.17  F16LST, Select List MADC Channel Range

          Function codes F16A1 through and including  F16A8  write  starting
          and   ending   MADC  channel  numbers  for  subsequent  list  data
          collection.  The specified starting channel must be less  than  or
          equal  to  the ending channel (no wrap-around).  The indicated bit
          positions should be coded as zero.

                  | |   ending channel #  | | starting channel #  |
                  |0|       (0-127)       |0|     (0-127)         |
                   15                    8 7                     0

          The channel numbers must be in the range 0-127 for the 190 module.

          9.18  F16PLT, Select Plot MADC Channel

          Function codes  F16A9  through  and  including  F16A14  write  the

          CAMAC 190 Module: V1.17

          selected  MADC channel number for subsequent plot data collection.
          Unused bit positions should be coded as zero.

                  |                       |D|       channel #     |
                  |        undefined      |I|        (0-127)      |
                   15                      7 6                   0

          DI      Diagnostics flag.  If zero, normal MADC data collection is
                  used.  If set, fake plot data will be generated within the 
                  module as follows:  If channel # <= 63, the time stamps 
                  start at 0, increment by channel*4, and never reset.  
                  When channel # >= 64, real time stamps are returned. 
                  DATA = 1's complement of time stamp for both cases.

       |  9.19  F16A15, Initialize Hardware Diagnostics Read
       |  This function, in conjunction with F6A7, provides a read  function
       |  of  programmable  speed,  which  returns  known  data.   After the
       |  execution of  an  F16A15  function,  F6A7  will  return  zero  and
       |  increment  on  each successive execution.  The data sent to F16A15
       |  determines how long it takes to execute future F6A7's.

          9.20  F17An, Select Arm And Trigger Conditions

          Write the arm and trigger selection word for collection  of  lists
          1-8  (  F17A1  to  F17A8)  or  the collection of plot channels 1-6
          (F17A9 to F17A14).  The associated data available flag in the  LAM
       |  source register will be cleared.  Data retrieval pointer 0 will be
       |  selected for this list or plot channel.  This should be  the  last
          function  issued  when  setting  up  data  acquisition.  Undefined
          fields are reserved for future enhancements and must be  coded  as

                  |       |    T    |  T  |A|   P  |    A    |  A  |
                  |       |    M    |  S  |D|   M  |    M    |  S  |
                   15   13 12     10 9   8 7 6    5 4       2 1   0
           AS     Arm Source (enable Sample Triggers)
                  0= cancel data acquisition
                  1= arm immediately
                  2= arm on clock decoder source
                  3= arm on external source
           AM     Arm source Modifier
                  if AS=2, clock decoder source #(1-7)
                  if AS=3, external source #(0-3)

                                                      CAMAC 190 Module: V1.17

           PM     Plot mode (0=undefined  1=mode_A  2=mode_B  3=mode_C)
                  ignored for list collection
                  1= continuous digitize after specified arm
                  2= digitize 2048 points N milliseconds after arm
                     where 0 <= N <= 65535     (N written by F18An)
                  3= begin continuous digitize and stop N Sample Triggers
                     after arm where 0 <= N <= 2047  (N written by F18An)
           AD     Arm disable.  If  zero,  then  data  collection  will  be
                  re-armed after a complete list or plot  buffer  has  been
                  collected and the specified arm source becomes active. If
                  set then the selected arm source will  be  ignored  until
                  after all available data has been read by  the  host  (or
                  new trigger select word is written on this function code).
           TS     Sample Trigger source
                  0= trigger sample collection on internal timer
                          fixed asynchronous 1 KHz for lists
                          independently variable asynchronous rate for plots
                  1= trigger immediately (lists only)
                  2= trigger sample collection on clock decoder source
                  3= trigger sample collection on external source
           TM     trigger source Modifier
                  if TS=2, clock decoder source #(1-7)
                  if TS=3, external source #(0-3)

          9.21  F18LST, Select List Arm Delay

          Function codes F18A1 through F18A8 write the arm delay  value  for
          the corresponding list acquisition (1-8).  An unsigned 16-bit data
          word is accepted from the host and causes the module to  ignore  N
          triggers  from the selected trigger source following an ARM before
          collecting a list.  A value of zero  will  direct  the  module  to
          collect  the  corresponding  list  on  the first occurrence of the
          selected trigger  after  being  armed.   If  trigger  source  zero
          (internal timer) has been selected then a fixed asynchronous 1 KHz
          source will provide triggers for the delay count.  Trigger  source
          1 (immediate) causes the delay count to be ignored.

          9.22  F18PLT, Select Plot Arm Delay

          Function codes F18A9 through including F18A14 write the arm  delay
          value  for  plot  data  acquisition (1-6).  Supplied values should
          fall within in the  ranges  specified  in  the  F17An  description
          (above) to avoid unpredictable behavior.

          CAMAC 190 Module: V1.17

          Mode            Definition

            A     Delay count is ignored for this mode of data collection.

            B     The supplied value may be in the range 0 <= N <= 65535 and
                  will cause a delay of N milliseconds when the arming input
                  goes active until the first data point is collected.

            C     The supplied value should be in the range 0 <= N  <=  2047
                  and  sets  the  number of additional sample triggers which
                  will be accepted after the  selected  arming  source  goes

          9.23  F19A0, Write LAM Mask Register

          The contents of the LAM mask register are ANDed with the  contents
          of  the  LAM source register whenever there is a change in the LAM
          source register status.  If the result is non-zero and the  module
          LAM is enabled then LAM is asserted.

          9.24  F19A1, Configure Clock Decoder

          The  host  may  program  each  of  the   eight   decoder   sources
          independently  to  become  active on the occurrence of one or more
          clock events.  If more than one clock event is specified then  the
          decoder  source  becomes active on the logical OR of the specified
          events.  The  host  may  also  selectively  disable  clock  events
          previously  defined to activate a decoder source.  Decoder sources
          1-7 are available to the host for use in  specifying  general  arm
          and trigger conditions.  Source zero is dedicated to resetting the
          time stamp counter.  All undefined fields must be coded as zeros.

                  |     Clock Event #     |     |   DS   |   CM   |
                  |        (0-255)        |     |        |        |
                   15                    8 7   6 5      3 2      0

          CM      Command code field.  Selects the action to be performed by

              0   Reset all.  Disables all  clock  events  for  all  decoder
                  sources.   The  value of the clock event and DS fields are

              1   Reset decoder source.  Configures  the  clock  decoder  so
                  that the source specified by DS will never become active.

u                                                     CAMAC 190 Module: V1.17

              2   Reset decoder source and enable single event.   Configures
                  the clock decoder, initially, so that no clock events will
                  cause the source specified by DS to become  active.   Then
                  enables  the single clock event specified in the high byte
                  to cause that source to become active.

              3   Disable single clock event for decoder source.  Configures
                  the  source  specified  by  DS  so that it will not become
                  active when the clock event specified  in  the  high  byte
                  occurs.  No other enabling events are affected.

              4   Enable single clock event for decoder source.   Configures
                  the  decoder source specified by DS so that it will become
                  active when the specified clock event  occurs.   No  other
                  enabling clock events are affected.

             5-7  Undefined at  this  time.   The  module  treats  these  as

          DS      Decoder source field specifies the decoder source is to be
                  affected  for  command  which  may  operate  on individual
                  sources.  Valid values are  in  the  range  0-7.   Decoder
                  source  zero  is  dedicated  to  resetting  the time stamp
                  scaler.  Decoder sources 1-7  are  available  for  use  as
                  general arm and trigger sources.

          9.25  F19A4, Write Extended LAM Mask Register

          The contents of the extended LAM mask register are ANDed with  the
          contents  of  the extended LAM source register whenever there is a
          change in the extended LAM source register status.  If the  result
          is  non-zero  the  EX  bit  in  the  LAM  source  register is set,
          otherwise it is cleared.
       |  9.26  F19A5, Select/reset Data Retrieval Pointer
       |  Select and optionally reset a data retrieval pointer for a list or
       |  plot channel.
       |       There are 16 data retrieval pointers numbered  0  to  15  for
       |  each list and plot channel.  This function selects which retrieval
       |  pointer will be used by  the  next  F0An  function  code  for  the
       |  specified  list or plot channel.  After an F17 function, retrieval
       |  pointer 0 is selected by  default.   The  main  use  for  multiple
       |  pointers is so that a plot channel running a continuous plot (plot
       |  mode A) can be read out multiple times for multiple users.

          CAMAC 190 Module: V1.17

       |       In addition, when the RS bit is set, this function resets the
       |  specified  retrieval  pointer  for  the list or plot channel.  For
       |  lists and plot modes B and C, the retrieval pointer  is  reset  to
       |  point  to  the  first  data point.  For plot mode A, the retrieval
       |  pointer is reset to point to the next  data  point  that  will  be
       |  collected.    Resetting  a  retrieval  pointer  may  be  used  for
       |  re-reading a list or a snapshot (plot mode B or C) or for throwing
       |  away unwanted data for plot mode A.
       |          +-----------------------------------------------+
       |          |R|         |  Pointer  |  List Index (1-8) or  |
       |          |S|         | ID (0-15) |  Plot Index (9-14)    |
       |          +-----------------------------------------------+

       |           15          11        8  7                     0

          9.27  F19PLT, Write Plot Sample Period

          Function codes F19A9 through  F19A14  correspond  to  plot  sample
          periods  for  plot  channels  1-6 and directly control plot sample
          rate when internal timing is specified as a trigger  source.   The
          16-bit  word written by the host is treated as an unsigned integer
          where the least significant bit represents  10  microseconds.   At
          present,  the  actual  value  must  be greater than or equal to 14
          (decimal) due to throughput  considerations.   Transmitted  values
          will  be  clamped  to  this lower limit as necessary.  The allowed
          sample periods correspond to rates from 1.5 Hz to  7.1  KHz.   The
          timer register is loaded immediately upon receipt of this function
          and  may  change  the  rate  of  a  previously  established   plot
          acquisition which is still in progress.

               Plot mode B may optionally specify fast (plot period value of
          3)  or  superfast  (plot  period value of 0) data collection using
          this function.  The limit clamp is ignored for these  two  special

          9.28  F24A0, Disable Module LAM

          This is a control function.  It inhibits the module from asserting
          LAM.  It does not reset any pending LAM status.  The module status
          may still be obtained by reading the  LAM  status  register.   (At
          module reset, LAM is enabled.)
       |  9.29  F24A1, Reset Alarm System
       |  Reset alarm system.  The good/bad bits in all alarm blocks are set
       |  to  the  good  state  (cleared),  the triesnow counts in all alarm
       |  blocks are set to zero, and the alarm  queue  is  emptied  of  all

t                                                     CAMAC 190 Module: V1.17

       |  messages.

          9.30  F26A0, Enable Module LAM

          This a control function.  It allows the module to assert LAM  when
          the  logical  AND  of  the  LAM  source  register and the LAM mask
          register is non-zero.  (At module reset, LAM is enabled.)


               Two examples of module set-up sequences are shown -- one list
          and  one  plot.   In  both  cases it is assumed that clock decoder
          source #0 has been configured to reset the time-stamp scaler  upon
          the  occurrence  of  some  clock event(s).  ACNET subsystems might
          find  it  appropriate  to  reset  the  time-stamp  scaler  at  the
          beginning  of  an  accelerator  supercycle  (event  #0).   A CAMAC
          command to effect this is shown below and need be transmitted only
          once after module reset.

                                F19A1, data = '0004'x

          In both cases the host processor may poll the LAM source  register
          (F1A0)  to determine when the data of interest has been collected.
          Alternately, the LAM mask register may be configured to generate a
          LAM  service  request  when the data collection has completed.  In
          all cases the Q-retry procedures for data  writes  to  the  module
          (detailed earlier) must be followed.

          10.1  Setting Up A List

               The following sequence of commands and data set up collection
          of  MADC  channels 0-31 (0-1F hexadecimal) at the approximate time
          of peak guide field on the next Booster  accelerator  beam  pulse.
          The digitized values and their associated time-stamps are retained
          by the module until read by the host.  After  completion  of  data
          read  the  data  collection cycle will repeat.  It is assumed that
          clock decoder source #1 is available and that time  stamps  should
          be relative to all Booster reset events.

          CAMAC 190 Module: V1.17

             F19A1, data='1002'x      !Clear all TS reset events and select
                                      !event 10 (null cycle) for TS reset.
             F19A1, data='1104'x      !TS reset on event 11 (pre-pulse).
             F19A1, data='1204'x      !TS reset on event 12 (beam pulse).
             F19A1, data='120A'x      !Clear all events for clock source #1
                                      !and enable event 12.
             F17A1, data='0000'x      !Cancel current collect for list #1.
             F16A1, data='1F00'x      !Specify channels 0-31 for list #1.
             F18A1, data='0013'x      !Specify 35 milliseconds delay from ARM.
             F17A1, data='0186'x      !Arm on clock source #1, sample trig
                                      !after internal delay and disable arms
                                      !until all data read out by host.

          10.2  Setting Up A Plot

               The following sequence of CAMAC writes will establish a  mode
          B plot on plot channel #1 which gathers 2048 data points at a rate
          of 2 KHz beginning one second after the beginning of TeV flat-top.
          The  data  is  held  until  read  by the host after which the data
          collection will be re-established for the next accelerator  cycle.
          It  is  assumed  that  clock decoder source #1 is available.  Data
          will be acquired from MADC input #3.

             F19A1, data='4C0A'x      !Clear all events for clock source #1
                                      !and enable event 4C(start flat-top).
             F17A9, data='0000'x      !Cancel any current plot #1 collect.
             F16A9, data='0003'x      !Specify MADC input #3.
             F19A9, data=50           !Specify 2 KHz internal rate for
                                      !Sample Triggers (1E5/2000=50).
             F18A9, data=1000         !Delay 1000 milliseconds (1 second)
                                      !after arm.
             F17A9, data='00C6'x      !Arm on clock decoder source #1,
                                      !internal sample triggers, disable
                                      !arms until next F17A9 function.


                                              _     _        _
u               FOP is the CAMAC  190  family  Fast  On-line  Protocol.   Its
          purpose is to provide a typecode-oriented communication scheme for
          infrequently used module functions.  This  allows  the  frequently
          used  features  to  make  full  use of dedicated function code and
          subaddress combinations.  FOP is primarily  intended  for  use  by
          diagnostic and debugging programs and is not an attempt to provide
          a general purpose communication protocol.  All  FOP  communication
          uses   four   function   codes  as  described  below.   Not  every
          transaction requires the use of all four function codes.  In fact,
          most do not.

m                                                     CAMAC 190 Module: V1.17

               The FOP typecode handler routines run at interrupt level with
          all other interrupts masked off.  The following functions are used
          to speak FOP:

                -  F19A2        write FOP command

                -  F19A3        write FOP data

                -  F6A3         read FOP status

                -  F6A4         read FOP data

          11.1  F19A2, Write FOP Command

          This function is used  to  begin  and/or  end  a  command  to  the
          module's typecode processor.

                  |S|X|                   |                       |
                  |N|E|      reserved     |   Typecode (TC)       |
                  |M|Q|                   |                       |
                   15                    8 7                     0

          SNM     Start receiving new message on F19A3.  Current contents of
                  the  received message buffer are lost (buffer read pointer
                  is reset)

          XEQ     End of message to module, execute  requested  action  with
                  data supplied on F19A3 (if any)

          TC       8-bit  command  code  (1-255).    Other   typecodes   are
                  implementation-specific  and  are  assigned  by the module
                  programmer.  The same typecode should be specified on both
                  the SNM and XEQ transmissions.

          Note that if the SNM and XEQ bits are both set then  there  is  no
          message  data  to be transmitted on F19A3, all meaning is implicit
          in the typecode itself and execution of the typecode handler  will
          begin  immediately.   In this case all data previously transmitted
          via F19A3 are lost.

          Status returns:
                  0     success
                 -1     Ambiguous command, neither start nor stop
                 -2     Undefined typecode

          CAMAC 190 Module: V1.17

          11.2  F19A3, Write FOP Data

               Up to 256 words of 16-bit  data  will  be  accepted  on  this
          function code following a FOP command to start a new message (SNM)
          on F19A2.  These data will be placed in a temporary buffer and are
          available  to the typecode handler routine when an execute command
          (XEQ) is received on F19A2.

          Status returns:
                 -1     indicates buffer overflow

          11.3  F6A3, Read FOP Status Word

                  |         STAT          |       typecode        |
                  |                       |         (TC)          |
                   15                    8 7                     0

          TC      8-bit typecode with which the status in the high  byte  is
                  associated.    0  implies  status  is  from  last  command
                  transmission on F19A2.

          STAT    is specific to the typecode indicated in the low byte.  It
                  is   treated   as   a   signed  byte  with  the  following
                            >0   partial or qualified success
                            =0   success
                            <0   error

          11.4  F6A4, Read FOP Reply Data

               Read typecode-specific data to be returned to the host.   The
          amount  of  data which is available is also typecode-specific.  It
          may be implicit for the typecode or it may have been specified  by
          the  host  in  a preceding command and data transmission sequence.
          The familiar ~Q retry procedure is required in any case.

          11.5  FOP Typecodes

          11.5.1  FOP Typecode 1 - set up return of  previously  transmitted
          command data for testing purposes.

          Status returns:
                  0    Success

                                                     CAMAC 190 Module: V1.17

          11.5.2  FOP Typecode 2 - Set up  read  of  clock  decoder  control
          table  image.   This  table is maintained as an exact duplicate of
          the decoder's table since that one  is  write-only  memory  (WOM).
          Each  returned  16-bit  word  contains  two  bytes from the table.
          Event N sensitization is  shown  in  the  most  significant  byte.
          Event N+1 sensitization is shown in the least significant byte.  A
          PDP-11 style host should byte swap each received word in order  to
          make  maximum  sense out of the table.  If a bit is clear then the
          occurrence of the event will cause a processor interrupt.  If  the
          bit  is  set then the associated clock event is ignored.  Bits are
          numbered from 0 to 7, right to left.  A bit number corresponds  to
          the DS field in the F19A1 function.

          Status returns:
                  0    Success

          11.5.3  FOP Typecode 3 - Set up read  of  diagnostic  error  event
          counters.   Up  to  17  words  will  be  available on F6A4 after a
          successful execution.  These values are stored in RAM memory which
          is  not  zeroed  as a part of processor restart.  Consequently the
          data accumulates across reset commands.  The  module  is  able  to
          tell  when a power-on reset occurs and clears these values to zero
          at that time.  The format of the array is:

       |  Word        Definition
       |  1-2     Seconds since last cold restart (low word first)
       |  3-4     Seconds since last cold restart at last warm restart 
       |          (low word first)
       |  5       Warm restart count (front panel and F9A0 resets)
       |  6       Spurious vectored interrupt count
       |  7       Extended instruction trap count
       |  8       Privileged instruction trap count
       |  9       System call trap count
       |  10      Segment trap count
       |  11      Non-maskable interrupt count
       |  12      Non-vectored interrupt count (debugger entries)
       |  13      Current stack depth in words
       |  14      # SAMEF0 interrupts/second not resulting in DMA setup
       |  15      Count of MADC convert timeout errors (not implemented)
       |  16      # of serial scheduler iterations/second

       |  17      # of serial scheduler task activations/second

          Status returns:
                  0    success

          11.5.4  FOP Typecode 4 - Set up memory dump using  first  word  in
          transmitted  data  buffer  (required) as the initial dump address.
          Up to 32K consecutive words may be read from  F6A4  (there  is  no
          wrap-around from FFFE to 0000, however).  Best practice is to read

          CAMAC 190 Module: V1.17

          only those locations  known  to  contain  memory  to  avoid  doing
          strange things to memory mapped I/O devices.

          Status returns:
                  0    Success

          11.5.5  FOP Typecode 5 - Patch module writeable memory.   An  even
          number  of  word  pairs  (address,value)  will  be  read  from the
          previously transmitted data.  Each address will be loaded with the
          subsequent  data  value until the transmitted buffer is exhausted.
          A trailing address without a corresponding data value is ignored.

          Status returns:
                  0    Success
                 -1    Insufficient data length (must have at least
                        one word pair available in buffer)

          11.5.6  FOP Typecode 6 - Transmit Alarm  Blocks  to  the  module's
          alarm  monitor.  The format of the alarm block is described in the
          alarm system section.

          Status returns:
                  0    Success

          11.5.7  FOP Typecode 7 - Set up read of an Alarm Block.  A  single
          word  is  required to specify the Alarm Block of interest and must
          have been previously transmitted on F19A3.  The format of the word

                          | | | | |       | |             |
                          |x|x|x|x| List# |x|  Channel #  |
                           15      11    8 7 6           0

          Status returns:
                  0    Success
                 -1    insufficient transmitted data
                 -2    List # out of range

          11.5.8  FOP Typecode 8 - Declare MADC resolution.  The module  has
          no reasonable method of determining the number of significant bits
          returned by the connected device (MADC).  Also, jumper wires allow
          up  to 4 bits of time stamp value to be returned in the low nibble
          of a datum -- and there is no  way  of  determining  these  jumper

                                                      CAMAC 190 Module: V1.17

          selections  from  module  firmware.   As far as data collection is
          concerned, the module simply returns whatever  it  reads,  all  16
          bits.  ACNET scaling services then have to know enough to mask off
          the  proper  number  of  bits.   In  order  to  provide   reliable
          monitoring  services, however, it becomes necessary for the module
          to  know  how  many  bits  to  mask  off  before  performing  data
          comparisons.  By default, the module assumes that a 16-bit MADC is
          connected.  If some other resolution is configured then  the  host
          may set the resolution using this function.

          Status returns:
                  0    Success
                 -1    No data in FOP buffer

          11.5.9  FOP Typecode 9 - Clear the "I've Been Reset"  bit  in  the
          extended LAM register.  This function is performed by sending C009
          (hex) to function code F19A2.

          Status returns:
                  0    Success

          11.5.10  FOP Typecode 16 - Set  up  to  read  a  data  acquisition
          task's  Environment  Block.   The  task  number,  1-14,  for which
          information is desired must have been sent via  a  previous  F19A3
          function.   After  successful execution up to 70 words may be read
          on F6A4.

          Status returns:
                  0    Success
                 -1    task number out of range
                 -2    task number not transmitted


          12.1  CPU, Board A

               The left circuit card, or "A-board", sports the following:

                -  Zilog Z8002 processor operating at 6 MHz

                -  8 KB EPROM and 8 KB RAM (no wait states)

                -  AMD 9513 5-channel programmable timer

                -  AMD 9519 8-channel interrupt controllers (x2)

          CAMAC 190 Module: V1.17

                -  8-channel accelerator clock decoder

                -  Signetics 2651 Programmable Communications Interface

                -  CAMAC function/subaddress decoder  providing  128  unique
                   interrupt vectors with a 16-bit read/write buffer

                -  Time-stamp prescaler

          12.1.1  CAMAC Function Decoder -

               All CAMAC function codes are mapped through  a  fusible  link
          PROM (U1 on the schematic drawing) to generate:

                -  A 4-bit function code for  valid  CAMAC  functions;  this
                   constitutes  the  high nibble of the interrupt vector for
                   the CPU.

                -  An X response for all valid CAMAC  functions  accompanied
                   by the assertion of the N line.

                -  Two dedicated lines for  'Test  LAM'  and  'Reset'.   The
                   latter will generate a hardware module reset.

          Function code and CAMAC sub-address  comparison  and  latching,  Q
          response and LAM generation are handled by two register type PAL's
          (U6 and U7).  Only valid function codes are latched  and  generate
          an  interrupt.   The CAMAC subaddress is used as the low nibble of
          the interrupt vector  for  the  CPU.   Arbitration  between  CAMAC
          read/write  cycles  and  CPU  access  to the CAMAC data buffers is
          controlled by a PLA (U8) and two D type flip/flops (U10).  A  WAIT
          is  generated  for  the  CPU  if  a CAMAC cycle is in progress (to
          prevent collisions).

  CAMAC Read Cycle - On  every  read  cycle  the  previous
          function  and  subaddress  is compared to the present function and
          subaddress.  A ~Q response is generated if the two are  different.
          This  prevents invalid data reads with a different CAMAC read code
          and allows for data prefetches.  If they are the  same,  the  read
          flip/flop  output  signal  (RDFF) is checked to determine if valid
          data is in the CAMAC read buffer  (U4  and  U5).   If  true,  a  Q
          response  is  returned  and the read flip/flop is cleared.  A data
          write operation by the CPU to the CAMAC read buffer will  set  the

r                                                     CAMAC 190 Module: V1.17

  CAMAC Write Cycle - The  write  flip/flop  controls  the
          loading  of  the  CAMAC  write  buffer  (U2  and U3).  Data is not
          accepted and ~Q returned if the output (WRTFF) is set.  Data reads
          by the CPU from the CAMAC write buffer will clear the flip/flop.

  CAMAC Block Transfer Reads - The  CAMAC  function  codes
          F(0)*A(n)  are  reserved  for block transfer by the I/O processor.
          Only  the  first  occurrence  after  a  change  of  function   and
          subaddress  will  generate  a  CAMAC  interrupt  to  the CPU.  All
          subsequent reads are passed on through the 'BTN' line to  the  I/O
          processor.   This  allows  the  CPU  to  setup  the  IOP for block
          transfer reads.

          12.1.2  Accelerator Clock Interface - Accepts the standard 10  MHz
          clock  signal as a input on the rear I/O connector.  The signal is
          terminated in 50 ohms and presented to the  usual  combination  of
          differential receiver and Fermilab clock decoder circuit.

               The 8-bit output of the clock decoder is used  to  address  a
          fast  256x8  RAM memory.  The eight data lines from this "decoding
          RAM" are used to provide 8  pulsed  signal  sources.   The  signal
          associated  with  the least significant bit of the decoding RAM is
          hardwired to provide a reset for the  20-bit  time  stamp  scaler.
          The  remaining  data  bits  are  hardwired  to  seven of the CPU's
          interrupt controller  inputs  to  provide  general  purpose  clock

               The described scheme requires arbitration  access  since  the
          CPU  and  the clock decoder circuitry may both address the decoder
          RAM at the same time.  In order to reduce the required chip  count
          the  CPU  is  denied  read  access  to this 256-byte memory.  Read
          access is simulated by maintaining a copy of the decoding  RAM  in
          read/write memory.

          12.1.3  External Interrupt Inputs - Four general purpose  external
          interrupt  inputs  are  made  available  and  may be user-defined.
          These interrupts may be specified whenever a general arm or Sample
          Trigger  source  is required.  These inputs are TTL compatible and
          are internally pulled up with 470 ohms (to +5  VDC).   A  negative
          going  edge  will  trigger  a CPU request.  A user of these inputs
          must exercise extreme care not to trigger requests at  a  rate  so
          high  as  to saturate the CPU!  The actual maximum rate depends on
          the total processing load  presented  to  the  CPU.   These  input
          signals  are  available  on  the I/O connector and the front panel
          (where they are cryptically labelled "IR8" to "IR11").

          CAMAC 190 Module: V1.17

          12.2  I/O Processor, Board B

               The right circuit  card,  or  "B-board",  contains  the  MADC
          interface hardware.  It sports:

                -  128 KB of dynamic RAM (32 KB dual-ported with the CPU)

                -  AMD 9513 5-channel programmable timer circuit

                -  Intel 8089 dual channel I/O processor (4 MHz)

                -  dual-ported MADC interface

                -  a general status register

                -  time-stamp counter register

          12.2.1  8089 I/O Processor - or IOP, can be thought of as a  smart
          DMA  controller which performs the usual types of DMA transfer and
          is also able to execute programmed instruction sequences  residing
          in   memory.   Alternately,  it  can  be  viewed  as  a  very  low
          performance microprocessor possessing a peculiar  and  restrictive
          instruction  set which executes one interesting instruction -- one
          that transforms it into a DMA controller  for  a  block  transfer.
          There  are  actually  two  such identical "channels" in the single
          physical package.  These two channels  can  be  assigned  priority
          relative  to  one another or they can interleave bus accesses when
          operating in either the programmed or DMA mode.   The  reason  for
          selecting  the  8089  is  that it offers two DMA channels and some
          processing power in a single 40-pin package.  This eliminates  the
          extra  glue  logic  normally  required  to  support  multiple  bus

               A more "state of  the  art"  approach  would  be  to  use  an
          integrated  computer  chip  such  as  the Intel 80186.  As of this
          writing, however, these chips are widely advertised but not nearly
          as  widely  distributed (if actually available at all).  Since the
          hardware design  was  finalized  in  1982  it  was  impossible  to
          consider these attractive devices.

          12.2.2  CPU To IOP Communication - The CPU and IOP communicate via
          the  shared  memory segment (32 KB).  The CPU has direct access to
          several IOP control lines which allow it to  start  and  stop  IOP
          programs  and  DMA transfers.  The IOP is able to generate one CPU
          interrupt.  The  CPU  must  examine  shared  memory  in  order  to
          determine  the  exact nature of the IOP's request(s).  In addition
          the CPU also has access to most B-board peripheral devices  (which
          are mapped to CPU I/O space).

h                                                     CAMAC 190 Module: V1.17

          12.2.3  Other B-board  Peripherals - The  B-board  general  status
          register  concentrates the state of the five timer output bits and
          the MADC busy and local/remote  bits.   The  time  stamp  register
          simply  counts  the  prescaled  time  stamp  clock supplied by the
          A-board.  One of the A-board's clock decoder lines is dedicated to
          resetting the time stamp counter on the logical OR of any selected
          clock events.

          12.3  Address Spaces

          An address map of the module is shown below  and  is  probably  of
          interest only to other module designers.

                Z8002 Memory           8089 Memory            Z8002 I/O
             0+---------------+     0+---------------+    0+---------------+
              |  EPROM (8KB)  |      |    unused     |     |               |
          2000|---------------|  8000|---------------|     |               |
              |   RAM (8KB)   |      | I/O Registers |     |               |
          4000|---------------|      | mapped to CPU |     |               |
              |Clk Decoder WOM|      | I/O addresses |     |    unused     |
          4200|---------------|      |  8000 - FFFF  |     |               |
              |   I/O Page    |  FFFF|---------------|     |               |
          4300|---------------|      |    unused     |     |               |
              |    unused     | E0000|---------------|     |               |
          8000|---------------|      |               | 8000|---------------|
              |               |      |               |     |               |
              |               |      |               |     |               |
              | mapped to IOP |      |  RAM (128 KB) |     | mapped to IOP |
              |   addresses   |      | program & data|     | I/O register  |
              | F8000 - FFFFF |      |               |     |   addresses   |
              |               |      |               |     |  8000 - FFFF  |
              |               | F8000|~ ~ ~ ~ ~ ~ ~ ~|     |               |
              |               |      | mapped to CPU |     |               |
              |               |      | memory addrs  |     |               |
              |               |      |  8000 - FFFF  |     |               |
          FFFF+---------------+ FFFFF+---------------+ FFFF+---------------+

          12.4  MADC Access Arbitration

               Access to the MADC interface is shared between  the  CPU  and
          the  IOP.  Since the hardware is not re-entrant it is necessary to
          arbitrate access to  the  interface.   The  IOP  never  explicitly
          reserves   the  interface.   Rather,  the  interface  is  reserved
          automatically when the IOP attempts an access  via  a  time  stamp
          read operation.  If the interface is held by the CPU port then the
          IOP channel will see a MADC busy state until the CPU  relinquishes
          the  resource.  At that time the hardware re-establishes the IOP's
          interrupted conversion request to the MADC.  The IOP's  conversion

          CAMAC 190 Module: V1.17

          then   proceeds   without  interruption.   The  IOP  releases  its
          interface reserve by reading the MADC data register.

               The CPU, in contrast, must assert an  explicit  lock  request
          via its "MO" line.  The CPU's request is acknowledged via the "MI"
          line.  The "MO" and "MI" lines  are  special  resource  management
          signals developed directly by the CPU chip.  Their state is tested
          and set by  special  instructions.   CPU  requests  for  the  MADC
          resource  have  priority  over  IOP  requests  and  are allowed to
          interleave access to the MADC between IOP accesses (even when  the
          IOP  is  in  DMA  mode  for "superfast" plot collection).  The IOP
          interface is only "interruptible" at discrete times, however (when
          it  actually  attempts  I/O  to  the ADC).  Latency for the CPU to
          acquire the interface depends on  how  many  bus  cycles  the  IOP
          executes   between   I/O   accesses  to  the  ADC  (currently  ~33
          microseconds  between  IOP's  time  stamp  read  and   data   read
          instructions  in  programmed I/O) or on the conversion time of the
          MADC if an IOP-requested conversion cycle is already  in  progress
          when the resource request is made by the CPU.

          12.5  Front Panel Features

               A photograph of the module front panel is included at the end
          of this document.

          12.5.1  RESET - The   reset   button,   when   depressed,   resets
          processors,  peripheral  chips  and  other  circuits.   The  CAMAC
          function F(9)*A(0) activates the very same sequence (no  processor
          intervention is required to do a remote reset).

          12.5.2  LEDs -

  N - indicates, when on, that the  crate  controller  has
          initiated  a dataway cycle addressed to the leftmost slot occupied
          by the 190 module.  This LED is stretched to  10  milliseconds  to
          aid viewing.

  LAM - indicates, when on, that the module  is  asserting
          the  dataway  LAM  signal  for the leftmost slot.  Since there are
          many possible reasons for this condition the host  must  read  the
          LAM  source  register,  F(1)*A(0),  and  the  extended  LAM source
          register, F(1)*A(6), in  order  to  identify  the  nature  of  the

                                                      CAMAC 190 Module: V1.17

  LAMEN - indicates, when on, that any  unmasked  bits  in
          the LAM source register may cause module LAM to be asserted.  When
o          off, module LAM will never be asserted.  LAM source bits which are
          set  by  module  firmware  will be latched and may cause LAM to be
          asserted when the LAM is enabled at some later  time.   F(24)*A(0)
          and  F(26)*A(0)  are  provided  to set the state of the LAM enable
          gate.  After power-up or reset LAM is enabled.

  L2 - is used for  various  diagnostic  purposes  by  the
          module.   It  is always set on during the initialization sequence.
          If it remains on after issuing a RESET then suspect a problem with
          the 190 or the MADC.  In addition, at this time, the monitor alarm
          scan sets this LED on for the  duration  of  its  execution.   The
          latter use may change with future firmware versions.

  BTR - indicates, when on, that the B-board (IOP  channel
          #2) is receiving F(0)*A(n) requests in the DMA mode.

  IOP - indicates, when on, that the IOP  holds  the  MADC
          interface reserve.

  BUSY - indicates, when on, that the MADC is busy with  a
          conversion.  This LED directly reflects the state of the BUSY line
          connected to the MADC.

  CPU - indicates, when on, that the CPU  holds  the  MADC
          interface reserve.

          12.5.3  RS-232  Connection - to  a  standard  asynchronous  serial
          terminal  is  provided  on the front panel.  The connector used on
          the panel  mates  to  a  4-conductor  cable  connector,  Lemo  USA
          #FO 304NYL U/4.2.  The pins are designated as:

               1.  ground

               2.  transmit data

               3.  receive data

          CAMAC 190 Module: V1.17

               4.  no connection

          The terminal interface signals are also made available at the rear
          I/O connector to accommodate more permanent installations.

          12.5.4  External Interrupt  Inputs - are  provided  as  four  Lemo
          sockets labeled IR8 through IR11.  These correspond to the general
          purpose external arm and Sample Trigger  sources  named  0  to  3,

          12.6  I/O Connector Definition

               The I/O connectors used are the 36-pin Viking  type.   The  A
          board  is  the  left  slot as viewed from the front of the module.

                                A-Board I/O Connections

                  Signal         Contact       Signal         Contact
                  ----------------------       ----------------------
                   Gnd              1L          Gnd              1R
                   nc               2L          TeV Clock        2R
                   Ext Trig 0      10L          Gnd             10R
                   Ext Trig 1      11L          Gnd             11R
                   Ext Trig 2      12L          Gnd             12R
                   Ext Trig 3      13L          Gnd             13R
                   RS-232 xmit     17L          RS-232 rcv      17R
                   nc              18L          RS-232 gnd      18R

.                                                     CAMAC 190 Module: V1.17

                                B-Board I/O Connections

                  Signal         Contact       Signal         Contact
                  ----------------------       ----------------------
                   Gnd              1L          Gnd              1R
                   Local/Remote     2L          Data Valid       2R
                   nc               3L          Busy             3R
                   Data 5           4L          Data 4           4R
                   Data 7           5L          Data 6           5R
                   Data 9           6L          Data 8           6R
                   Data 11          7L          Data 10          7R
                   Data 13          8L          Data 12          8R
                   Data 15 (msb)    9L          Data 14          9R
                   Digitize        10L          Addr 5          10R
                   Addr 6          11L          Addr 4          11R
                   Addr 7          12L          Addr 3          12R
                   Data 0  (lsb)   13L          Addr 2          13R
                   Data 1          14L          Addr 1          14R
                   Data 2          15L          Addr 0          15R
                   Data 3          16L          nc              16R

          There are 16 data lines from the MADC.  When using a  12-bit  unit
          connect to data lines D4 through D15.


               All MADC interface signals are TTL levels.   Control  signals
          that   determine   the   initiation   of  a  data  conversion  and
          synchronization of data transfer are:

                -  DIGITIZE   (active high) - C190 output

                -  BUSY       (active high) - C190 input

                -  DATA VALID (active high) - C190 input

          Digitize is asserted by the  C190  to  start  a  data  conversion.
          After  receiving  BUSY  from the MADC, digitize goes low.  Minimum
          width of DIGITIZE is 250 nsec.  If the BUSY does  not  go  active,
          then  DIGITIZE will go inactive after 500 nsec.  Address lines are
          stable at least 40 nsec before the rising edge of DIGITIZE.

               It is the responsibility  of  the  MADC  (or  other  external
          device)  to  latch the address lines of the requested data channel
          at DIGITIZE.  The MADC signals the end of conversion to  the  C190
          by  setting  BUSY  inactive (low).  Returned data from the MADC to
          the C190 is strobed into the data buffers by the  rising  edge  of
          the  DATA  VALID signal.  The remote/local line from the MADC (not
          available on all MADC units) informs the C190 of  the  MADC  mode.
          The C190 interprets this signal as low for remote, high for local.

          CAMAC 190 Module: V1.17

               If the MADC is switched to LOCAL, the C190 firmware  will  be
          unable  to  collect  any  data.   In such a case the program loops
          forever waiting for the MADC to be placed in REMOTE.  This has the
          effect   of  suspending  all  module  functions.   This  state  is
          sometimes referred to with the four-letter word "HANG".


          14.1  The Division Of Labor

               Management concerns required  that  the  firmware  effort  be
          spread  across  two programmers.  Fortunately, the module hardware
          falls naturally into two basic components which  require  firmware
          support,  the CPU and IOP.  The CPU handles all communication with
          the host, sequences the data  collection  state  machines  and  is
          responsible  for  list  data  collection and single channel reads.
          The IOP has two jobs which  require  careful  optimization  --  to
          collect  plot  data  "simultaneously"  for up to 6 channels and to
          operate as a DMA controller to allow return of collected  data  to
          the  host  at  BTR rates.  Because of the constraints imposed upon
          the IOP programmer by the available instruction set and the target
          throughput  rates,  that programmer was allowed to specify the CPU
          to IOP communication protocol.

          14.2  CPU

          14.2.1  Data  Collection  State  Sequencer - is   implemented   by
          connecting   a   given  data  collection  task/environment  to  an
          interrupt source.  As the task advances from one state to  another
          it  disconnects from the previous interrupt source and connects to
          a new interrupt source.  A shared  interrupt  system  is  provided
          which  calls  a  list  of  modules  on  the  occurrence of a given
          hardware interrupt.  This allows a number of task environments  to
          be  connected  to the same interrupt source.  To minimize overhead
          an interrupt source is enabled when the first  task  connects  and
          disabled  when the last task disconnects.  If required by the data
          acquisition mode, a  task/environment  may  be  connected  to  two
          interrupt  sources simultaneously.  Plot mode C requires this, for

          14.2.2  Low  Priority  Tasks - are  executed  by  a  simple-minded
          serial  scheduler  where  each of a number of tasks is examined in
          turn for eligibility to run.  A task is eligible if  it  has  been
          requested  to  be  run  by an interrupt service routine or another
          "background  task".   The  task  will  run  to  completion  before
          releasing  the  background  to  the next waiting task (if any).  A
          background task may disable interrupts while  accessing  the  MADC

d                                                     CAMAC 190 Module: V1.17

          interface  or updating certain data structures.  These periods are
          kept as short as possible but do add to the maximum  latency  seen
          by  any  hardware  interrupt  (including any CAMAC commands).  The
          latency in activating a requested background task depends upon the
          maximum  number  of  tasks defined and whether there are any other
          tasks which have been  requested.   If  a  single  task  has  been
          requested  and  there  are no interruptions then that task will be
          activated  in  a  maximum  of  100  microseconds.   The  poll   is
          round-robin,  therefore  it  is  possible that the first requested
           task will not actually run first; requests are not queued FIFO!

          14.2.3  Reduction Of Interrupt Service Overhead - is essential  in
          a  device  controller.   From  the  above description it should be
          clear that the CPU may be faced  with  interrupt  service  demands
          which  are  highly variable and which may impose very heavy loads.
          In order to improve the responsiveness, the  general  purpose  CPU
          registers  are  assigned  dedicated  functions.   Roughly half are
          assigned to "background" tasks for the purpose of list  collection
          while  the  other half are dedicated to transient use by interrupt
          service routines.  In addition, interrupts are serviced in  strict
          serial  sequence (one interrupt cannot interrupt another interrupt
          service routine).  This eliminates  the  overhead  of  saving  and
          restoring  registers  for  almost  all interrupt service routines.
          Such  an  approach  is   undesirable   for   a   general   purpose
          multi-tasking  system.  In a device controller, however, the great
          majority  of  all  interrupt  requests  are  for  service  from  a
          non-reentrant  hardware device or communications which modify data
          structures and require uninterrupted  serial  access  anyway.   An
          implementation  modelled  after a more general scheme would simply
          serialize these accesses at the  expense  of  increased  execution

          14.2.4  List Data Collection - is performed by the CPU.  The  list
          collection  tasks  run  as  background  tasks.   These  tasks  are
          serially scheduled as described above so only one list is actually
          being  collected  at  a time.  In the event that two or more lists
          share identical arm and Sample  Trigger  specifications  then  the
          lists will be collected one after another (with no guarantee as to
          which gets collected first).   In  reality,  there  is  a  single,
          re-entrant list collection task.

          14.2.5  Debugger Program - is a firmware option which is currently
          included  in all modules.  It provides a simple debugging facility
          for use by the developers.  All that is necessary is to plug in  a
          common  serial  terminal  (RS-232).   Commands  to  dump and patch
          memory, examine register contents and start certain test  programs
          are  supported.   Module  users  need  not  be  concerned with the

          CAMAC 190 Module: V1.17

          particulars of debugger operation though the command  formats  are
          listed in Appendix A.

          14.3  I/O Processor

          14.3.1  I/O Channel 1 - is dedicated to collecting plot data  from
          up  to  six  MADC channels.  A round-robin polling scheme is used.
          Each requesting plot is  also  assigned  a  dedicated  9513  timer
          output.   The  timer  output  bit is set to indicate a request for
          service (collect a data point).  The output bit is cleared after a
          data  point  has  been  collected  and  stored  in  the requesting
          channel's data buffer.  This allows for minimum software  overhead
          when  the  internal  asynchronous  plot  rate  generation has been
          selected (since these are hardware timer channels).   Since  there
          are  only  five  timers  directly available on the B-board a sixth
          "fake timer channel register" is simulated  by  the  CPU  (on  the
          A-board).  This takes the form of a flag in shared memory which is
          set whenever a dedicated A-board timer  interrupts  the  the  CPU.
          The  flag  is  cleared  by  the IOP after collecting a data point.
          This method of scheduling assures that  data  collection  degrades
          gracefully  as  the  aggregate  data  rate  from multiple requests
          approaches that supportable by the module.

               Two special high speed modes  of  data  collection  are  also
          supported  as  outlined  under the description of plot mode B, the
          fast and superfast modes.   In  the  fast  mode  the  normal  poll
          sequence  is  disrupted  when  the selected channel requests data.
          Instead of collecting a single  point  the  channel  program  will
          collect all 2048 data points as fast as possible in the programmed
          I/O mode.  Super-fast mode operates in a  similar  fashion  except
          that  the  data  collection  uses  the  DMA  capability of the IOP
          channel and is even faster.  See Appendix A for  approximate  data

          14.3.2  I/O Channel 2 - is  dedicated  to  supporting  high  speed
          return   of  collected  data  via  the  CAMAC  dataway.   This  is
          accomplished by setting up a DMA  transfer  from  the  appropriate
          data  buffer  in  module  memory  to the CAMAC interface register.
          Once the DMA transfer is initialized  (by  the  CPU),  CAMAC  data
          reads,  plot  data  acquisition and any CPU memory accesses to the
          B-board all contend for the B-board memory bus.

          14.4  Firmware Development Environment

               Hardware  development,  initial  code   checkout   and   PROM
          programming  use  System  #27.  System #27 is a Z80-based Multibus
          system running CDOS 1.7 or CPM 2.2.  Most importantly, the  system

d                                                     CAMAC 190 Module: V1.17

          is  equipped  with  an  Applied  Microsystems Z8000 emulator which
          provides extensive debugging  facilities  for  both  hardware  and
          software  problems.   This  includes  the  ability  to  map memory
          windows from the module  into  the  emulator.   Breakpointing  and
          traceback  facilities  (with full disassembly to assembly language
          mnemonics) simplify debugging.

               Code is assembled on the ACNET development system  VAX  under
          the  VMS  operating system using a MicroTec Z8002 cross assembler.
          The cross-assembler has  been  modified  in-house  to  more  fully
          exploit   certain   VMS   features.    Macros  defining  the  8089
          instructions and addressing modes are  also  assembled  using  the
          MicroTec  Z8002  assembler.  Output is Tektronix hex format object
          which is converted to Intel  hex  format  by  a  MicroTec  utility
          program.   Direct download of code over a VAX terminal line to the
          Applied Microsystems emulator is used for code checkout.

          15  FUSEWARE

               Together, the two circuit boards making up the module use  18
          programmable  logic  devices such as PLA's, PAL's and fusible link
          PROM's in order to reduce the total chip count.   A  comprehensive
          understanding  of  module  operation  (or  the schematic drawings)
          requires the defining parameters for  these  devices.   The  logic
          equations  for  generating  the fuse patterns are available on the
          ACNET software development system in the  Minotaur  account  under
          the  project  name  C190.  File names are of the form AAAAXYY.PLS,

                -  AAAA = module name ("C190")

                -  X    = board number ("A" or "B")

                -  YY   = I.C.  number on schematic drawing

          For example the file named C190B08.PLS contains source text  which
          defines the equations IC #8 on board B of a CAMAC 190 module.


                                      APPENDIX A


                                ADDITIONAL INFORMATION


                 ___________ ____ ___ _________ _____ ___ ____ ____ _
                 Approximate Fast and Superfast Rates For Plot Mode B

                                               Fast     Superfast
                   Fermilab MADC (11 us)       32 KHz     70 KHz
                   DSE MADC (33 us)           ~18 KHz    ~25 KHz
                   C192 (1553,14-bit,55 us)   ~13 KHz    ~16 KHz

              ___________ _______ _______________ ____________ ____ _____
              Approximate Maximum Non-interfering Simultaneous Plot Rates

                  # active       Rate          Rate         Rate
                  channels    1553_Serial    DSE_MADC     Fermi_MADC
                     1          5.8 KHz       6.9 KHz       6.9 KHz
                     2          3.4           4.2           4.2
                     3          2.4           3.0           3.0
                     4          1.8           2.3           2.3
                     5          1.5           1.9           1.9
                     6          1.2           1.6           1.6

          CAMAC 190 Module: V1.17


          F(0)*A(n)    n = 1-8: read list with time stamps
                       n = 9-14: read plot with time stamps

          F(1)*A(0)    Read LAM source register

          F(1)*A(1)    Read LAM mask register

          F(1)*A(2)    Read single channel (selected by F16A0)

          F(1)*A(3)    Read time stamp at last F1A2

          F(1)*A(6)    Read extended LAM source register

          F(1)*A(7)    Read extended LAM mask register

          F(6)*A(0)    Read module number (190 decimal)

          F(6)*A(1)    Read software version (major version # / rev level #)

          F(6)*A(2)    Read module configuration/status word

          F(6)*A(3)    Read diagnostic protocol status

          F(6)*A(4)    Read diagnostic protocol data

          F(6)*A(5)    Read alarm message FIFO

       |  F(6)*A(6)    Read plot channel status word

       |  F(6)*A(7)    Hardware diagnostics read

          F(8)*A(0)    Test LAM (this is a "all hardware" function)

          F(9)*A(0)    Reset module (this is a "all hardware" function)

          F(16)*A(0)   Write MADC channel number for single read

          F(16)*A(n)   n = 1-8 (lists): write first and last MADC channels
                       n = 9-14 (time plots): write selected MADC channel

       |  F(16)*A(15)  Initialize hardware diagnostics read

          F(17)*A(n)   n = 1-8: write list trigger selection
                       n = 9-14: write plot trigger selection

          F(18)*A(n)   n = 1-8: write list arm delay
                       n = 9-14: write plot arm delay

          F(19)*A(0)   Write LAM mask register

          F(19)*A(1)   Write clock decoder configuration

                                                      CAMAC 190 Module: V1.17

          F(19)*A(2)   Write FOP command

          F(19)A*(3)   Write FOP data

          F(19)A*(4)   Write extended LAM mask register

          F(19)A(5)   Flush data return for list or plot

          F(19)*A(n)   n = 9-14: Write plot sample period

          F(24)*A(0)   Disable LAM

       |  F(24)*A(1)   Alarm system reset (big clear)

          F(26)*A(0)   Enable LAM


              Typecode         Meaning
                 1         Return previously transmitted data
                 2         Read clock decoder control table
                 3         Read diagnostic event counters
                 4         Set memory dump address
                 5         Patch module memory
                 6         Transmit alarm specification block(s)
                 7         Specify alarm block for later read
                 8         Declare MADC resolution
                 9         Clear extended LAM "I've Been Reset" bit
                16         Set Environment Block read address


       |     Command   Parameters                   Description
       |       DR      none                         Display Registers
       |       DW             Display memory (Word)
       |       EP                    Examine input Port
       |       GO                     Go to user program
       |       OP        Output word to Port
       |       SW      (terminate w/CR)        Substitute memory Word
       |       XD       none                        eXit Debug mode

          All debugger parameters are entered in hexadecimal and must be  in
          upper  case.  Parameters and the command name must be separated by
          a blank.  A full-duplex terminal running at 9600 baud is  assumed.
          Debugger mode is entered whenever a character is received from the
          terminal.  While in the debugger mode all other  module  functions
          are  suspended  (including  any CAMAC I/O).  When finished, always

          CAMAC 190 Module: V1.17

          issue a XD command or reset the module.

u                                                     CAMAC 190 Module: V1.17

          A.5  BIBLIOGRAPHY


           ACNET Design Note 27.8
            CAMAC MADC Controller Specification
           R.J. Ducar, W.R. Knopf and A.D. Thomas

           May 22, 1982


            Z8000 CPU User's Reference Manual
           Zilog, Inc.
           Prentice-Hall, Inc. 1982
           ISBN 0-13-983890-2

e           Z8000 Assembly Language Programming
           Levinthal, Osborne, Collins
           Osborne/McGraw-Hill 1980
           ISBN 0-931988-36-5

           iAPX 86,88 User's Manual
           Intel Corporation 1981

            8089 I/O Processor Handbook
           Adam Osborne
           ISBN 0-931988-39-X

i           Data Communications Handbook 1981
           A. Weissberger
           Signetics Corporation 1981

           Am9500 Peripheral Products Interface Guide
           Advanced Micro Devices, Inc. 1980

           Z8002 Relocatable Macro Assembler Manual
           MicroTec, Inc. 1979
           Sunnyvale, CA

          CAMAC 190 Module: V1.17



           B. Brown        MS344
           M. Johnson      MS308
           F. Nagy         MS220
           D. Ritchie      MS120
           A. Thomas       MS220
           J. Tinsley      MS306


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