State Algorithm Table SATn defines the timing process for the testing of a process channel. It is defined by writing a small table of up to eight 16 bit words. The C204 will allow up to eight sequential writes to each sub-address for the specification of a particular state algorithm. When the last state of the table is satisfied, a trigger is issued to test the process channel as configured. States are generally satisfied by recognition of either a TCLK or Beam Sync clock event with or without a programmed delay.

The first state table entry uniquely defines the state reset (or escape) clock event, indication if this event is a TCLK or Beam Sync event, and the number of states that are thereafter programmed. There is no allowed delay from the detected event in this first entry. Occurrence of this event will serve to initialize the SAT by a stop/disable of any and all timing channels associated with the state algorithm table and vectoring to the second entry of the SAT. The first entry has the following format:

W16-W9: State Reset Clock Event ($00 to $FE)

W8: 0 = TCLK Event, 1 = Beam Sync Event

W7-W5: 7 (Implies No Delay). 0 thru 6 are Illegal

W4: 0 = Proceed to Next Entry When Satisfied, 1 is Illegal

W3-W1: Number of Subsequent Entries in Algorithm Table (1-7)

Subsequent table entries are of similar format but allow specification of an associated time delay. The C204 has capability for four time delays and they are uniquely associated with the clock event as reference in the table entry. These entries have the following format:

W16-W9: Clock Event ($00 to $FE)

W8: 0 = TCLK Event, 1 = Beam Sync Event

W7-W5: Associated Time Delay - 0 = TD0, 1 = TD1, 2 = TD2, 3= TD3,

7 = No Time Delay, 4 thru 6 are Illegal.

W4: 0 = Proceed to Next Entry When Satisfied

1 = Generate Trigger to Test Process Channel

W3-W1: Number of Subsequent Entries in Algorithm Table (0-6)

Writing of a SAT table is a string operation and should be preceded by a different F or A code. The C204 module will No Q on the 9^th received F(21) operation to a single sub-address given the maximum size of eight entries per state algorithm table.

SAT0 is reserved for a steady state examination of process channel inputs. This is similar to how the C200 module treats permit inputs.

F(5) A(1-7) Read State Algorithm Table SATn

Reading of a SAT table is a string operation and should be preceded by a different F or A code. No Q Expected on First Try. Sequential reads increment through the table. No Q is to be expected after the 8^th successful read. 

F(21) A(8) Write High/Low Beam Intensity Threshold

Data written is consistent with transmitted MDAT (TC=$60) data for Main Injector Intensity.

F(5) A(8) Read of F(21) A(8) data register. No Q Expected on First Try.

F(20) A(0-3) Write Time Delay TDn for Timing Channel TCn

LSB = 100 microseconds, FS = 6.5535 Seconds

Four timing channels, TC0 thru TC3, are available for individual association with programmed state algorithms. The singular reference event for the particular timing channel is uniquely specified in the state algorithm. When used in a state algorithm, the timing out of the timing channel may advance the state algorithm to the next table entry or trigger the test of a process channel.

F(4) A(0-3) Read Time Delay TDn for Timing Channel TCn. No Q expected on First Try.

F(19) A(0) Write Total Number of Active Process Channels

Given a maximum of 64 analog channels and 32 digital channels, the write data ranges from 1 to 96 decimal or $xx01 to $xx60 hex. If there is more than a single testing instance for a channel, the number of additional instances shall be added to the total number of active process channels.

F(3) A(0) Read of F(19) A(0) data register. No Q Expected on First Try.

F(18) A(0) Write Process Channel Pointer

PCn ranges from PC0 to PC95 or $xx00 to $xx5F.

PC0 to PC63 ($xx00 to $xx3F) are analog channels and correlate directly to associated MADC channels.

PC64 to PC95 ($xx40 to $xx5F) are digital channels and correlate directly to C204 digital input lines.

PCn values are not necessarily contiguous This pointer applies to F(16) and F(0) operations.

If a particular analog or digital channel is to be tested in more than one way (i.e. with different State Algorithm Tables), the channel is said to have more than one "instance". The $xx high byte of the Process Channel Pointer is used to distinguish these different instances. Normally this high byte would be written as $00 for a single instance. Additional instances would be accommodated by writing the high byte as $01, $02, $03 in that order. Allowing for a maximum of three additional instances per channel is thought to be a reasonable limit.

F(2) A(0) Read current content of F(18) A(0) register. No Q Expected on First Try.

W16: 1 = Channel is ACTIVE and Capable of Trip,

0 = Channel is MASKED and Incapable of Trip.

W15-13: Desired State Algorithm Table for this PCn - SAT0 thru SAT7

W12: 1 = Allow PC Trip Only if NuMI Beam Permit is Asserted

W11: 1 = Allow PC Trip Only if MI Beam Permit is Asserted

W10: 1 = Allow PC Trip Only if NuMI Beam is Present

W9: 0 or 1 = Desired State of Digital Process Channel

W8: 1 = Analog Low Limit Value Applies

W7: 1 = Analog High Limit Value Applies

W6: 1 = Both Analog Low and High Limit Values Apply

W5: 1 = Analog Low Limit Value is a High Limit for Low Intensity Beam

W4: 1 = Analog High Limit Value is a High Limit for High Intensity Beam

W3: 1 = Archive Process Channel Data if Tripped

W2: 1 = Scale Back Delivered Intensity if Tripped

W1: Unassigned

F(0) A(0) Read Process Channel Configuration for the Process Channel PCn Indicated by the Previous F(18) A(0) Operation

No Q Expected on First Try.

F(16) A(1) Write Low Analog Limit for the Process Channel PCn Indicated by the Previous F(18) A(0) Operation

This value may selectively be considered as a High Analog Limit for low intensity beam. Not required for digital channels.

F(0) A(1) Read Low Analog Limit for the Process Channel PCn Indicated by the Previous F(18) A(0) Operation

No Q Expected on First Try.

F(16) A(2) Write High Analog Limit for the Process Channel PCn Indicated by the Previous F(18) A(0) Operation

This value may selectively be considered as a High Analog Limit for high intensity beam. Not required for digital channels.

F(0) A(2) Read High Analog Limit for the Process Channel PCn Indicated by the Previous F(18) A(0) Operation

No Q Expected on First Try.

F(0) A(3) Read Last Acquired Nominal Value for the Process Channel PCn Indicated by the Previous F(18) A(0) Operation

Applies to both analog and digital channels. No Q Expected on First Try. Module may No Q subsequent to first try if value has not been sampled in accord with the completion of the State Algorithm Table.

F(0) A(4) Read Average of Eight (8) Last Acquired Nominal Values for the Process Channel PCn Indicated by the Previous F(18) A(0) Operation

Applies only to analog channels. No Q Expected on First Try. Module may No Q subsequent to first try if less than eight values have been sampled in accord with the completion of the State Algorithm Table. When provided, these average values should serve as reference for the low and high analog limits.

F(1) A(0) Read Module Status

R16: 1 = Process Channel Trip has Occurred Since Last Reset

R15: 1 = TCLK Present

R14: 1 = Beam Sync Clock Present

R13: 1 = MDAT Present

R12 1 = Beam Present

R11: 1 = All Process Channels Configured

R10: 1 = Configuration Enabled

R9: Module Heartbeat - Expect to See this Bit Toggling

R8: 1 = State Algorithm Table #7 Active

R7: 1 = State Algorithm Table #6 Active

R6: 1 = State Algorithm Table #5 Active

R5: 1 = State Algorithm Table #4 Active

R4: 1 = State Algorithm Table #3 Active

R3: 1 = State Algorithm Table #2 Active

R2: 1 = State Algorithm Table #1 Active

R1: 1 = State Algorithm Table #0 Active

No Q Expected on First Try. Ordering of bits subject to change. Definition of State Algorithm Table Active needs clarification. A possible definition is start of active when the SAT is at the second entry and end of active upon issuance of trigger.

F(1) A(1) Read Tripped Process Channels

No Q Expected on First Try. If a process channel has tripped since last reset, read data indicates the process channel number PCn ranging from $0000 to $005F that has tripped. The first read returns the first PCn that tripped after module reset thereby following a first in - first out protocol. PCn is not repeated for multiple trips. No Q after list of tripped channels is read completely.

F(6) A(0) Read Module Number 204

No Q Expected on First Try. Data returned are $CC hex.

F(7) A(0) Dummy Read - No Data are Returned.

A good way to check for hung read lines. No Q Expected on First Try.

F(9) A(0) Module Reset or Z+S2

Resets module micro-controller and internal processes. State Algorithm Tables are reset to first entry. Timing channels are stopped and disabled. Record of tripped process channels is cleared. Records of nominal values are cleared. Sets module to "Disable Configuration" mode. "Active/Mask" state of individual PCn remains as programmed.

The occurrence of the TCLK $A8 event (NuMI Beam Permit System Reset) is more limited than the F(9) A(0) or Z+S2 operation. For the $A8 event: State Algorithm Tables are reset to first entry; timing channels are stopped and disabled; and the record of tripped process channels is cleared.

F24) A(0) Disable Configuration

Expect for the F(18) operation that is always enabled, write codes F(16), F(19), F(20) and F(21) are disabled.

F(26) A(0) Enable Configuration

Write codes F(16), F(19), F(20) and F(21) are enabled.