CONTROLS HARDWARE RELEASE NO. 66.2CONTROLS
CAMAC 269
MI PS LINK
ED-218527
CONTROLS HARDWARE RELEASE NO. 66.2
CAMAC 269 Module
Main Injector Power Supply Link Receiver
Robert J. Ducar
February 16, 1990
1 DESCRIPTION
4 CAMAC 269 MODULE - I/O ASSIGNMENTS
5 CAMAC 269 MODULE - INTERFACE CONNECTOR ASSIGNMENTS
6 CAMAC 269 MODULE - FRONT PANEL
7 SPARES
8 DOCUMENTATION
9 PALS DOCUMENTATION
1 DESCRIPTION
The one-wide CAMAC 269 module is a serial to parallel
converter designed to receive serial data from the new Main
Ring Power Supply Link (MRPSL) as described in CHR No. 65.2.
The module is designed to receive both aggregate and addressed
serial frames. Up to three addressed frames per location are
recognized by comparison to a hard-wired house number at the
module I/O connector. Recognized data are multiplexed in
parallel format to the associated SCR Controller Unit (SCU).
These data effect control of local Lower, Upper, and Quad Bus
Power Supplies. There is also capability to effect control of
certain Special Power Supplies.
Received serial frames are 36 bits in length and are self
clocking at a 10 MBit/sec data rate. Types of frames include
Power Supply Data (PSD), Stay Alive (SA), Link Clear (LC), and
Link Integrity (LI). LI and SA frames are normally
transmitted at a 720 Hz rate and bracket the transmission of
PSD frames when generated by the link sourcing computer. The
LC frame is transmitted upon power up of the Link Transmitter
or by programmed instruction of the sourcing computer.
The nature of the Main Injector Power Supply System demands a
high level of communication link integrity. To this end,
transmitted frames include 8 bits of additional data for
transmission verification in addition to explicitly defined
frame protocol. All received frames are fully examined for
adherence to the defined protocol. Though some amount of
transmission error will be tolerated, as set by data
associated with the LI frame, excessive detected errors will
result in a fast trip condition. This condition is effected
by a change of state of the "PS Link Permit" signal that is
hard-wired from the 269 module to the SCU.
The 269 module also accommodates the monitor of certain
status from the SCR Controller Unit. This status is
multiplexed to the 269 as four 6 bit words, all being
refreshed at a 1 KHz rate. All connections between the CAMAC
269 module and the SCU are opto-isolated.
Some of the information provided by the module reflects
status that has been counted or detected over a two and
one-half second interval. This information includes a count
of frame faults, a count of missing LI frames, and receipt of
the LC frame. This information is latched at the end of each
2.5 second interval and updated at the end of each subsequent
interval.
2 MODULE OPERATION
2.1 Receipt Of Serial Frames
Serial frames, nominally 3.55 microseconds in length, are
separated by a minimum of 4 microseconds dead time. Every
frame broadcast on the link is examined for adherence to
protocol. Detected frame errors are counted and compared to
the programmed trip level. LI frames are expected at a 720 Hz
rate. Absence of these frames is also counted and compared to
the programmed trip level. If either trip level is reached,
the PS Link Permit line is brought to the logical "0" state.
Resetting of the Permit line is achieved only by receipt of
the LC frame or by a reset of the module.
Individual status flags are set upon receipt of
recognized PSD frames for the Lower, Upper, Quad, and Special
power supplies. The state of these flags will cleared at a
2.5 second interval. These flags control the CAMAC "Q"
response for the read operations of received data of
recognized frames.
2.2 Write Operations To The SCU
Receipt of PSD frames that contain an address that
matches the hard-wired house number are multiplexed to the
SCU. The transfer of the associated 16 bits of data is
accompanied by assertion of a two line write address (WA2 and
WA1) and a write strobe (WSTRB). Receipt of the SA frame is
also transmitted to the SCU with a write address and strobe,
but without data. The write strobe is nominally one
microsecond wide, with data and write address lines stable one
microsecond before and after WSTRB. Transmittal of SA to the
SCU results in reclocking previously received PS reference and
control information to the individual SCR controllers.
Assignment of the write address is as follows:
WA2 WA1 Assignment
---------------------------
0 0 Lower Bus PS *
0 1 Upper Bus PS
1 0 Quad Bus PS
1 1 Stay Alive
* Also used for Special PS
2.3 Read Operations From The SCU
Independent of MRPSL activity, four 6 bit words of status
are read from the SCR Controller Unit at a 1 KHz rate. The
SCU receives a two line read address (RA2 and RA1) from the
269 module and gates status data as per the following
assignment:
RA2 RA1 Assignment
---------------------------------------
0 0 Lower Bus PS Status
0 1 Upper Bus PS Status
1 0 Quad Bus PS Status
1 1 SCR Controller Unit Status
3 CAMAC 269 OP CODES
All codes return module Q and X immediately, except
as noted. This module asserts LAM only if the PS
Link Permit line is false.
F(0) A(0) Read Lower Bus PS Received Data (Conditional Q)
---------
R16 - R5 | R4 | R3 | R2 | R1
-----------------------------------------
PS Reference | SPARE | REGL | BYPS | RECT
F(0) A(1) Read Upper Bus PS Received Data (Conditional Q)
---------
R16 - R5 | R4 | R3 | R2 | R1
-----------------------------------------
PS Reference | SPARE | REGL | BYPS | RECT
F(0) A(2) Read Quad Bus PS Received Data (Conditional Q)
---------
R16 - R5 | R4 | R3 | R2 | R1
-----------------------------------------
PS Reference | SPARE | REGL | BYPS | RECT
F(0) A(3) Read Special PS Received Data (Conditional Q)
---------
R16 - R1
-----------------------------------------
PS Reference
PS Reference: Scaling is a bipolar signed 2's comple-
ment integer for the Lower, Upper, and
Quad power supplies. Scaling for Special
power supplies may be scaled similarly
or may be a unipolar unsigned integer.
SPARE: This is a spare control bit. It is
normally transmitted as a "0".
REGL: Regulators - Commanded OFF by a "1".
BYPS: Bypass - Commanded ON by a "1".
RECT: Rectifiers - Commanded ON by a "1".
When RECT is OFF, BYPS must be ON.
F(1) A(0) Read Lower Bus PS Status
---------
R16 - R7 | R6 - R1
-------------------------------
0 | Power Supply Status
F(1) A(1) Read Upper Bus PS Status
---------
R16 - R7 | R6 - R1
-------------------------------
0 | Power Supply Status
F(1) A(2) Read Quad Bus PS Status
---------
R16 - R7 | R6 - R1
-------------------------------
0 | Power Supply Status
For the Lower, Upper, and Quad supplies, status
bit assignments are as follows:
R6: Equals "1" if PS Reference Set to Zero
R5: Equals "1" if 60 Hz Sync OK
R4: Equals "1" if Rectifier SCRs ON
R3: Equals "1" if Bypass SCRs OFF
R2: Equals "1" if Timing Generator in Lock
R1: Equals "1" if Power Supply Within Limits
F(1) A(3) Read SCR Controller Unit Status
---------
R16 - R7 | R6 - R1
-------------------------------
0 | SCU Status
R6: Equals "1" if All PS References Set to Zero
R5: Equals "1" if Link Trip
R4: Equals "1" if Stay Alive Trip
R3: Equals "1" if EDF Asserted
R2: Equals "1" if MASS Trip
R1: Equals "1" if Plug Trip
F(2) A(0) Read Module Status
---------
R16 - R9 | R8 - R1
-------------------------------
House/SPS Number | Status
House Number: Ranges from $00 to $18 (Hex)
SPS Number: Ranges from $19 to $1F (Hex)
R8: Equals "1" if PS Link Permit Asserted
R7: Equals "1" if Link Integrity Frames Active
R6: Equals "1" if Stay Alive Frames Active
R5: Equals "1" if Link Clear Frame Received
R4: Equals "1" if Special PS PSD Received
R3: Equals "1" if Quad Bus PS PSD Received
R2: Equals "1" if Upper Bus PS PSD Received
R1: Equals "1" if Lower Bus PS PSD Received
F(2) A(1) Read Frame Fault Trip Levels Set by LI
---------
R16 (MSB) - R9 | R8 - R5 | R4 - R1
----------------------------------------
FRAME FAULT TL | 0 | LI FF TL
F(2) A(2) Read Accumulated Frame Faults (Latched Data)
---------
R16 (MSB) - R9 | R8 - R5 | R4 - R1
----------------------------------------
FRAME FAULTS | 0 | LI FF
F(6) A(0) Read Module Number
---------
R16 - R9 | R8 - R1
------------------------------
| 0 | 10D Hex, 269 Dec |
F(7) A(0) Dummy Read - No Data are Returned
---------
F(9) A(0) Reset Module
---------
This command is part of the logical or of
Z*S2, power-up clear, and receipt of the
LC frame. This clear resets PS Link Permit,
clears fault counters, and resets module
process flags. This command will also cause
bit R5 of module status to be asserted
momentarily.
4 CAMAC 269 MODULE - I/O ASSIGNMENTS
Rear I/O: 36 Position Edge Connector A = R B = L
POS SIGNAL POS SIGNAL
--- --------------- --- ----------------
1L MRPSL In (Coax) 1R Write Common
2L WSTRB 2R HA16 (MSB)
3L WA2 (MSB) 3R HA8
4L WA1 4R HA4
5L RA2 (MSB) 5R HA2
6L RA1 6R HA1
7L WD11 (MSB) 7R WD10
8L WD9 8R WD8
9L WD7 9R WD6
10L WD5 10R WD4
11L WD3 11R WD2
12L WD1 12R WD0 (LSB)
13L C3/SPARE 13R C2/REGL
14L C1/BYPS 14R C0/RECT
15L PSLP 15R Read Common
16L RD5 (MSB) 16R RD4
17L RD3 17R RD2
18L RD1 18R RD0 (LSB)
5 CAMAC 269 MODULE - INTERFACE CONNECTOR ASSIGNMENTS
Rear I/O: 36 Position Edge Connector A = R B = L
Interface Connector: Cable End - G6F22-38SNE
Chassis Bulkhead - GOB22-38PNE
Cable Type: Belden #9769 17 Individually Shielded
Twisted Pairs, 22AWG, Beldfoil Shield,
22AWG Tinned Stranded Drain Wires,
.585 inch OD.
Color Coding: Optional
Shielding: Individual drain wires may connect to
Write Common (1A) at the CAMAC I/O.
In that the interface is fully opto-
isolated, drain wires should be cut off
at the SCU connector and foil shields
protected from coming into contact with
the SCU connector shell.
G6F Pos 269 I/O Description (Positive Logic) Color
------- ------- ------------------------------ -----
A 15B PSLP - PS Link Permit Yellow
B 1A Write Common Black
Drain to 1A
C 2B WSTRB - Write Strobe Orange
D 1A Write Common Red
Drain to 1A
E 3B WA2 - Write Address 2 (MSB) White
F 4B WA1 - Write Address 1 Black
Drain to 1A
G 5B RA2 - Read Address 2 (MSB) Green
H 6B RA1 - Read Address 1 Blue
Drain to 1A
J 7B WD11 - PS Reference (MSB) Red
K 7A WD10 - | Brown
L 8B WD9 - | Green
M 8A WD8 - | Black
N 9B WD7 - | Yellow
P 9A WD6 - 2's Green
Complement
R 1OB WD5 - Format Black
S 10A WD4 - | Red
T 11B WD3 - | Blue
U 11A WD2 - | Black
V 12B WD1 - | Red
W 12A WD0 - PS Reference (LSB) Yellow
X 13B C3 - SPARE = Spare Control Bit Brown
Y 13A C2 - REGL = Regulators OFF Green
Drain to 1A
Z 14B C1 - BYPS = Bypass ON Black
a 14A C0 - RECT = Rectifiers ON Brown
Drain to 1A
b 1A Write Common White
c 1A Write Common Green
d 16B RD5 - Read Data (MSB) Red
e 16A RD4 - | White
f 17B RD3 - | Green
g 17A RD2 - | Red
h 18B RD1 - | Red
j 18A RD0 - Read Data (LSB) Blue
k 15A Read Common Orange
m 15A Read Common Black
n-s - Not Wired
6 CAMAC 269 MODULE - FRONT PANEL
The CAMAC 269 module has the following front
panel features:
N led: Red (stretched)
LAM led: Red
LI led: Green (stretched)
SA led: Green (stretched)
Special PS Data Flag led: Yellow
Quad PS Data Flag led: Green
Upper PS Data Flag led: Green
Lower PS Data Flag led: Green
PS Link Permit: Green led (not stretched)
Lemo (74F3037 Driver)
MRPSL Out: Green led (stretched)
Lemo (74F3037 Driver)
7 SPARES
A supply of CAMAC 269 operational spares is maintained on
the second floor of the Linac Annex.
8 DOCUMENTATION
0812-ED-218527 Schematic
0812-BD-218528 Artwork (RF-132)
0812-BD-218529 Master Drawing
0812-MD-34863 Outline Drawing
0812-MC-218530 Front Panel Mechanical
0812-MD-218531 Front Panel Silkscreen
9 PALS DOCUMENTATION
Directory: DEVL::USR$DISK3:[DUCAR.PALS]
Filenames: 26902A.DAT 1st Level NAF Decoder 82S173
26906A.DAT 2nd Level NAF Decoder 82S173
26935C.DAT Address Recognition 82S173
26940A.DAT SCU Write Control 82S153
26941B.DAT Frame Verification 82S153
26944C.DAT Frame Fault Processor 82S173
rjd: DEVL::USR$DISK3:[DUCAR.DOC]CMC269.RNO
PALS DOCUMENTATION
module 26902a title ' CAMAC 269 R. DUCAR 7-20-89 ' 26902a device 'f173';
F16, F8, F4, F2, F1, A8 pin 1,2,3,4,5,6; A4, A2, N, A1, ZS2 pin 7,8,9,10,11; S1, CLR, DF20, DF22, DF60, DF21 pin 13,14,15,16,17,18; R, QX, DF1, DF0, PUC pin 19,20,21,22,23;
H,L,X,Z = 1,0,.X.,.Z.; "Use standard PALASM operators @ALTERNATE equations ;
DF0 = N*F16*F8*F4*F2*F1*A8*A4*PUC ;" F(0)A(0-3)
DF1 = N*F16*F8*F4*F2*/F1*A8*A4*PUC ;" F(1)A(0-3)
/DF20 = N*F16*F8*F4*/F2*F1*A8*A4*A2*A1*PUC ;" F(2)A(0)
/DF21 = N*F16*F8*F4*/F2*F1*A8*A4*A2*/A1*PUC ;" F(2)A(1)
/DF22 = N*F16*F8*F4*/F2*F1*A8*A4*/A2*A1*PUC ;" F(2)A(2)
/DF60 = N*F16*F8*/F4*/F2*F1*A8*A4*A2*A1*PUC ;" F(6)A(0)
/CLR = N*F16*/F8*F4*F2*/F1*A8*A4*A2*A1*/S1*PUC + "F(9)A(0)S1
/PUC + ZS2*PUC
R = N*DF0 + N*DF1 + N*/DF20 + " Read
N*/DF21 + N*/DF22 + N*/DF60
QX = N*F16*F8*/F4*/F2*/F1*A8*A4*A2*A1*PUC + " F(7)A(0)
N*F16*/F8*F4*F2*/F1*A8*A4*A2*A1*PUC + " F(9)A(0)
N*R ;
"DESCRIPTION: This PAL provides the first level of NAF
decoding for the CAMAC 269 module.
end 26902a
module 26906a title ' CAMAC 269 R. DUCAR 8-19-89 ' 26906a device 'f173';
NC1, CQS, CUS, CSS, DF0, DF1 pin 1,2,3,4,5,6; QX, R, A2, CLS, A1 pin 7,8,9,10,11; NC13, DF01, Q, READ, DF13, DF02 pin 13,14,15,16,17,18; X, DF003, DF10, DF11, DF12 pin 19,20,21,22,23;
H,L,X,Z = 1,0,.X.,.Z.; "Use standard PALASM operators @ALTERNATE equations ;
/DF10 = DF1*A2*A1*QX*R ;" F(1)A(0)
/DF11 = DF1*A2*/A1*QX*R ;" F(1)A(1)
/DF12 = DF1*/A2*A1*QX*R ;" F(1)A(2)
/DF13 = DF1*/A2*/A1*QX*R ;" F(1)A(3)
/DF003 = DF0*A2*A1*QX*R*CLS + " F(0)A(0)
DF0*/A2*/A1*QX*R*CSS ;" F(0)A(3)
/DF01 = DF0*A2*/A1*QX*R*CUS ;" F(0)A(1)
/DF02 = DF0*/A2*A1*QX*R*CQS ;" F(0)A(2)
/READ = R*QX*/DF0 + R*QX*/DF003 + " Read
R*QX*/DF01 + R*QX*/DF02
/X = QX ;" X
/Q = QX*/DF0 + QX*/DF003 + QX*/DF01 + QX*/DF02 " Q
"DESCRIPTION: This PAL provides the second level of NAF
decoding for the CAMAC 269 module.
end 26906a
module 26935c title ' CAMAC 269 R. DUCAR 2-9-90 ' 26935c device 'f173';
HA16, A6, A7, A5, A4, A3 pin 1,2,3,4,5,6; A2, A0, A1, T2, VFY pin 7,8,9,10,11; NC13, DG, RPAR, PBAD, VHN, PASSD pin 13,14,15,16,17,18; LIA, LCA, SAA, VLUQS, HAPEQ pin 19,20,21,22,23;
H,L,X,Z = 1,0,.X.,.Z.; "Use standard PALASM operators @ALTERNATE equations ;
VHN = /VFY*/A5*/A4*/PBAD*T2 + " $00-0F
/VFY*/A5*A4*/A3*/PBAD*T2 + " $10-17
/VFY*/A5*A4*A3*/A2*/A1*/A0*/PBAD*T2 ;" $18
PBAD = /RPAR*DG + PBAD*DG " Parity Bad Flag
VLUQS = /A7*/A6*VHN*DG + " Valid Lower
/A7*A6*VHN*DG + " Valid Upper
A7*/A6*VHN*DG + " Valid Quad
/VFY*A7*A6*/A5*A4*A3*/A2*/A1*A0*/PBAD*T2*DG + " $D9
/VFY*A7*A6*/A5*A4*A3*/A2*A1*/PBAD*T2*DG + " $DA-DB
/VFY*A7*A6*/A5*A4*A3*A2*/PBAD*T2*DG ;" $DC-DF
/PASSD = HAPEQ*HA16*A4*VLUQS*DG + " Pass Data
HAPEQ*/HA16*/A4*VLUQS*DG;
SAA = /VFY*A7*A6*A5*A4*A3*/A2*A1*/A0*/PBAD*T2*DG ;" Stay Alive Adr
LCA = /VFY*A7*A6*A5*A4*A3*A2*/A1*/A0*/PBAD*T2*DG + " Link Clear Adr
LCA*DG;
LIA = /VFY*A7*A6*A5*A4*A3*A2*A1*/A0*/PBAD*T2*DG ;" Link Integ Adr
"DESCRIPTION: This PAL processes received addresses for both
aggregate and addressed operations. Note that
LCA is latched and stays active until DG times
out because /LCC will clear the receiver shift
registers.
B VERSION changed to add $00 as a valid house
number for special supplies at TG6 in the
Transfer Hall.
C VERSION changed to correct improper handling
of bad parity status. PBAD pin used to be
called RPAS.
end 26935c
module 26940a title ' CAMAC 269 R. DUCAR 7-20-89 ' 26940a device 'f153';
NC1, _25C, DIP, PASSD, A6 pin 1,2,3,4,5; A7, LCC, SA, CSL pin 6,7,8,9; CLS, CUS, CQS, CSS, WA1 pin 11,12,13,14,15; CQ, CU, WSTRB, WA2 pin 16,17,18,19;
H,L,X,Z = 1,0,.X.,.Z.; "Use standard PALASM operators @ALTERNATE equations ;
/WSTRB = /PASSD*DIP*LCC*/SA + " Write Strobe
SA*DIP*PASSD*LCC ;
/WA2 = A7*/A6*/PASSD*LCC*/SA + " Write Adr 2
SA*PASSD*LCC;
/WA1 = /A7*A6*/PASSD*LCC*/SA + " Write Adr 1
SA*PASSD*LCC;
CSS = A7*A6*/PASSD*DIP*LCC*/SA + " Clk Spec Flag
CSS*LCC*/_25C;
CQS = A7*/A6*/PASSD*DIP*LCC*/SA + " Clk Quad Flag
CQS*LCC*/_25C;
CUS = /A7*A6*/PASSD*DIP*LCC*/SA + " Clk Upper Flag
CUS*LCC*/_25C;
CLS = /A7*/A6*/PASSD*DIP*LCC*/SA + " Clk Lower Flag
CLS*LCC*/_25C;
CSL = A7*A6*/PASSD*DIP*LCC*/SA + " Clk Special or
/A7*/A6*/PASSD*DIP*LCC*/SA + " Lower Rgstr
/LCC;
CU = /A7*A6*/PASSD*DIP*LCC*/SA + " Clk Upper Rgstr
/LCC;
CQ = A7*/A6*/PASSD*DIP*LCC*/SA + " Clk Quad Rgstr
/LCC;
"DESCRIPTION: This PAL controls external write operations,
clocks power supply data into on-board reg-
isters, and generates process flags indicating
which supplies have been strobed.
end 26940a
module 26941b title ' CAMAC 269 R. DUCAR 2-9-90 ' 26941b device 'f153';
VLUQS, SAA, LCA, LIA, C2 pin 1,2,3,4,5; C3, C1, C0, NC9 pin 6,7,8,9; CLR, BF, LI, LC, SAC pin 11,12,13,14,15; DIP, LIX, SA, LCC pin 16,17,18,19;
H,L,X,Z = 1,0,.X.,.Z.; "Use standard PALASM operators @ALTERNATE equations ;
LC = LCA*C3*C2*/C1*/C0*CLR + LC*LCA " Link Clear Flag
/LCC = LC*CLR*DIP + /CLR " LCFlag*DIP + CLR
SA = SAA*C3*/C2*C1*/C0*CLR ;" Stay Alive
/SAC = SA + /LCC " Stay Alive + CLR
LI = LIA*C3*C2*C1*/C0*CLR*DIP ;" Link Integrity
LIX = LIA*C3*C2*C1*/C0*CLR ;" LI less DIP
BF = /VLUQS*/SA*/LC*/LIX*CLR*DIP ;" Bad Frame
"DESCRIPTION: This PAL provides the final processing of
received frame protocol as either valid or
invalid.
Version B fixes false BF upon LC by making
LC a flag. Also made /LCC active at DIP.
end 26941b
module 26944c title ' CAMAC 269 R. DUCAR 1-25-90 ' 26944c device 'f173';
CY2, SAF, _25S, _25C, LI, RD2 pin 1,2,3,4,5,6; BF, CISR, LCC, EQ2, CY1 pin 7,8,9,10,11; EQ1, NC14, PSLP, LSC, R5S, CC pin 13,14,15,16,17,18; LIR, LCCF, PSLPB, BFC, LIF pin 19,20,21,22,23;
H,L,X,Z = 1,0,.X.,.Z.; "Use standard PALASM operators @ALTERNATE equations ;
CC = _25C + /LCC " Clear Counters
LSC = LIF*CY1*/CC*LIR ;" Clk LI Fault
BFC = BF*CY2*/CC*LIR ;" Clk Bad Frame Fault
LIR = LI + LIR*LCC " LI Receive Flag
LCCF = /LCC + LCCF*/_25C " 1st LCC Flag
R5S = LCCF + LCCF*_25S + " R5 Status Bit Flag
R5S*/_25S + R5S*LCCF
PSLPB = EQ1*/LSC*LIR + " /Power Supply Link Permit
/EQ2*/BFC*LIR + " OK = 0, Fault = 1
PSLPB*LCC*LIR;
PSLP = /PSLPB ;" Power Supply Link Permit
"DESCRIPTION: This PAL controls the counters for LI and
frame faults and generates the Power Supply
Link Permit signal. It also generates the
Fast Trip Flag for status monitoring.
Version B: SA fault capability removed.
Version C: RD2 input obsolete. New output
R5S created to show F(9)A(0) or LC.
end 26944c
module 26944x title ' CAMAC 269 R. DUCAR 3-15-90 ' 26944x device 'f173';
CY2, SAF, _25S, _25C, LI, RD2 pin 1,2,3,4,5,6; BF, CISR, LCC, EQ2, CY1 pin 7,8,9,10,11; EQ1, NC14, PSLP, LSC, R5S, CC pin 13,14,15,16,17,18; LIR, LCCF, PSLPB, BFC, LIF pin 19,20,21,22,23;
H,L,X,Z = 1,0,.X.,.Z.; "Use standard PALASM operators @ALTERNATE equations ;
CC = _25C + /LCC " Clear Counters
LSC = LIF*CY1*/CC*LIR ;" Clk LI Fault
BFC = BF*CY2*/CC*LIR ;" Clk Bad Frame Fault
LIR = LI + LIR*LCC " LI Receive Flag
LCCF = /LCC + LCCF*/_25C " 1st LCC Flag
R5S = LCCF + LCCF*_25S + " R5 Status Bit Flag
R5S*/_25S + R5S*LCCF
/PSLPB = BF ;" X Fix to make PSLP = Bad Frame
PSLP = BF + PSLP*/_25C " Giving FP LED a BF Memory
"DESCRIPTION: This PAL controls the counters for LI and
frame faults and generates the Power Supply
Link Permit signal. It also generates the
Fast Trip Flag for status monitoring.
Version B: SA fault capability removed.
Version C: RD2 input obsolete. New output
R5S created to show F(9)A(0) or LC.
Version X: For Diagnostics, giving FP PSLP new meaning. end 26944x
module 26944y title ' CAMAC 269 R. DUCAR 3-22-90 ' 26944y device 'f173';
CY2, SAF, _25S, _25C, LI, RD2 pin 1,2,3,4,5,6; BF, CISR, LCC, EQ2, CY1 pin 7,8,9,10,11; EQ1, NC14, PSLP, LSC, R5S, CC pin 13,14,15,16,17,18; LIR, LCCF, PSLPB, BFC, LIF pin 19,20,21,22,23;
H,L,X,Z = 1,0,.X.,.Z.; "Use standard PALASM operators @ALTERNATE equations ;
CC = _25C*PSLP + /LCC " Clear Counters
LSC = LIF*CY1*/CC*LIR*PSLP ;" Clk LI Fault
BFC = BF*CY2*/CC*LIR*PSLP ;" Clk Bad Frame Fault
LIR = LI + LIR*LCC " LI Receive Flag
LCCF = /LCC + LCCF*/_25C " 1st LCC Flag
R5S = LCCF + LCCF*_25S + " R5 Status Bit Flag
R5S*/_25S + R5S*LCCF
PSLPB = EQ1*/LSC*LIR + " /Power Supply Link Permit
/EQ2*/BFC*LIR + " OK = 0, Fault = 1
PSLPB*LCC*LIR;
PSLP = /PSLPB ;" Power Supply Link Permit
"DESCRIPTION: This PAL controls the counters for LI and
frame faults and generates the Power Supply
Link Permit signal. It also generates the
Fast Trip Flag for status monitoring.
Version B: SA fault capability removed.
Version C: RD2 input obsolete. New output
R5S created to show F(9)A(0) or LC.
Version Y: Fault counters stop when PSLP trips
and don't reset in 2.5 sec.
end 26944y