General

The C479 module generates timing signals, synchronous with the accelerator RF for the equipment and instruments operating with accelerator beams in real time. Its four timing channels use one 53 Mbit/s encoded BSCLK for timing and may use TCLK and external trigger signals for arming. Once armed, the channel decodes a coming reference BSCLK event and generates the output signal with delay up to 2 seconds and resolution of either 1 ns or 1 bucket (about 19 ns). Optionally, the 7.5 MHz BSCLK may be used that provides the resolution of 7 buckets (about 132 ns) only, as a C279 two-channel decoder/timer does.

The four channel outputs may be combined using an internal OR logic (no external wire-OR allowed). While in timing state, each channel provides a signal on its status output. For test purposes and synchronization of external devices, three more decoding channels generate output signals: a BSCLK revolution AA event, combination of BSCLK events, and combination of TCLK events.
 

Versions

Each module has its unique set of BSCLK and TCLK events to be decoded, its combination of the external triggers, its timing channel outputs OR-logic, and the resolution of its timers. All these determine a C479 module version. Version parameters are programmed individually for each version and kept in one EPROM in the module. This version EPROM, a configuration EPROM for an ALTERA FLEX8K device, can easily be replaced when the module version should be changed *. The version number, decimal X.XX.X is readable.
A list of C479 versions in use is in a spreadsheet, C479_Versions.xls.
 

Timing

Each timing channel has three timers in series:

Timer Resolution Delay Data Delay Range

Conventional 7 bucket Dc: 24 bit about 2 s

High-resolution 1 bucket Dh: 3 bit about 132 ns

Fine-resolution 1.0 ns Df: 5 bit 31 ns

The delay time data: Dc, Dh, and Df are stored in one 32-bit register of the channel. To load these data in the register it is required two addressed write CAMAC operations. A bit map of the register, where the 16 bit CAMAC data, Word 0 and Word 1 correspond to the lower register bits and to the higher bits respectively, is shown below.
 

Word 0 [15..0], Register [15..0]

                                      Dc
<--------------------------------------------------------------------LSB
 

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Word 1 [15..0], Register [31..16]

           Df                Dh                       Dc
MSB----------------LSB  MSB-------LSB  MSB------------------------------<
 

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

A total delay time of one channel including all three timers is:

        Delay Time = (7·Dc + 1·Dh) bucket + (1·Df) nanosecond

Where: 1 bucket = 1 RF cycle = about 19 ns.
 

Arming

In accordance to the version, each timing channel may be:

- Armed always

- Armed or disarmed by TCLK event(s)

- Armed or disarmed by BSCLK event(s)

- Armed or disarmed by external trigger signal(s)
 

Enabling

Each timing channel may separately be enabled or disabled by an addressed CAMAC operation F26 or F24 respectively.
 

Inhibit, LAM

When failure of BSCLK occurs, the module stops the timing process and inhibits channel outputs for a time to avoid possible errors after restoration of BSCLK.

The module sets LAM when BSCLK or TCLK failure. The signals from the LAM sources are latched, may be read, and may be cleared.
 

Inputs

BSCLK *             - rear Viking and front Lemo inputs

TCLK                   - rear Viking input

Trig 1 - Trig 4     - four rear Viking inputs

OR IN                  - two inputs for signals coming from another C479 to be
                                OR’ed with CH 0, rear Viking and front Lemo inputs

Each of four timing channels has two output drivers: one for the rear Viking connector and the other for the front Lemo connector.

        NOTE:    No external Wire-OR of any outputs is allowed at C479 module!

Instead, each timing channel may internally be OR’ed with the previous channel in the order:

        - CH0 with External OR Input

        - CH1 with CH0

        - CH2 with CH1

        - CH3 with CH2

This allows any number of channels, including the channels of the other C479 module(s), be properly OR’ed in accordance to the version(s) assignments.
 

Other Outputs

BDE           - combination of BSCLK decoded events, assigned by the version, rear and front

TDE           - combination of TCLK decoded events, assigned by the version, rear and front

$AA           - revolution or BSCLK $AA decoded event, 588 or 1113 bucket period, front

7.5 MHz     - clock extracted from BSCLK, 7 bucket period, front output, attenuated

53 MHz      - clock extracted from BSCLK, 1 bucket period, front output, attenuated

BSCLK       - rear and front outputs, for use by other C479’s only!

TCLK         - rear output, for use by other C479’s only!

Timing 0     - ON when CH 0 in timing process, rear output

Timing 1     - ON when CH 1 in timing process, rear output

Timing 2     - ON when CH 2 in timing process, rear output

Timing 3     - ON when CH 3 in timing process, rear output
 

CAMAC Functions

Read Functions

F0A0 - return CH0 delay data word 0

F0A1 - return CH0 delay data word 1

F0A2 - return CH1 delay data word 0

F0A3 - return CH1 delay data word 1

F0A4 - return CH2 delay data word 0

F0A5 - return CH2 delay data word 1

F0A6 - return CH3 delay data word 0

F0A7 - return CH3 delay data word 1

F1A0 - read module status

    bit 0 = BSCLK Present

    bit 1 = TCLK Present

    bit 2 = PLL not locked

    bit 3 = Inhibit

    bit 4 = CH0 Timing

    bit 5 = CH1 Timing

    bit 6 = CH2 Timing

    bit 7 = CH3 Timing

    bit 8 = CH0 Armed

    bit 9 = CH1 Armed

    bit 10 = CH2 Armed

    bit 11 = CH3 Armed

    bit 12 = CH0 Enabled

    bit 13 = CH1 Enabled

    bit 14 = CH2 Enabled

    bit 15 = CH3 Enabled

F1A1 - read LAM

    bit 0 = BSCLK missing, latched

    bit 1 = TCLK missing, latched

    bit 2 = PLL not locked, latched

    bit 3 = Inhibit

    bit 4 = LAM, latched

    bit 14 = TCLK assigned

    bit 15 = 53 Mbit/s BSCLK assigned

F6A0 - read module ID number, hex: 1DF

F6A1 - read version number, dec.: XXXX

F6A2 - read module configuration

    bit 0 = CH0 Df timer (1 ns) ON

    bit 1 = CH1 Df timer (1 ns) ON

    bit 2 = CH2 Df timer (1 ns) ON

    bit 3 = CH3 Df timer (1 ns) ON

    bit 4 = CH0 OR’ed to Ext. OR IN

    bit 5 = CH1 OR’ed to CH0

    bit 6 = CH2 OR’ed to CH1

    bit 7 = CH3 OR’ed to CH2

    bit 14 = TCLK assigned

    bit 15 = 53 Mbit/s BSCLK assigned
 

Write Functions

F16A0 - write CH0 delay data word 0

F16A1 - write CH0 delay data word 1

F16A2 - write CH1 delay data word 0

F16A3 - write CH1 delay data word 1

F16A4 - write CH2 delay data word 0

F16A5 - write CH2 delay data word 1

F16A6 - write CH3 delay data word 0

F16A7 - write CH3 delay data word 1
 

Control Functions

F9A0 - reset module

F10A0 - clear LAM registers
 

F24A0 - disable CH0

F24A1 - disable CH1

F24A2 - disable CH2

F24A3 - disable CH3
 

F26A0 - enable CH0

F26A1 - enable CH1

F26A2 - enable CH2

F26A3 - enable CH3
 

I/O Connectors

All I/O signals are TTL @ 50 ohm (unless otherwise noted).
 

Viking Connector (Rear)

1L - /BSCLK OUT, a.c. ECL, 53 Mbit/s *

2L - ground

3L - /BSCLK IN, a.c. ECL, 53 Mbit/s *

4L - ground

5L - ground

6L - CH2 OUT, width = 8·7 bucket (» 1.06 m s)**

7L - CH3 OUT, width = 8·7 bucket (» 1.06 m s)**

8L - ground

9L - Ext. OR input

10L - ground

11L - ground

12L - Trig.3 input

13L - Trig.4 input

14L - Timing 3 output

15L - Timing 4 output

16L - ground

17L - ground

18L - ground
 
 

1R - BSCLK OUT, a.c. ECL, 53 Mbit/s *

2R - ground

3R - BSCLK IN, a.c. ECL, 53 Mbit/s *

4R - ground

5R - ground

6R - CH0 OUT, width = 8·7 bucket (» 1.06 m s)**

7R - CH1 OUT, width = 8·7 bucket (» 1.06 m s)**

8R - ground

9R - BDE output, width = 7 bucket (» 132 ns)

10R - TDE output, width = 7 bucket (» 132 ns)

11R - ground

12R - Trig.1 input

13R - Trig.2 input

14R - Timing 1 output

15R - Timing 2 output

16R - ground

17R - TCLK output

18R - TCLK input
 

LEMO Connectors (Front)

1 - BSCLK IN, a.c. ECL, 53 Mbit/s *

2 - /BSCLK IN, a.c. ECL, 53 Mbit/s *

3 - BSCLK OUT, a.c. ECL, 53 Mbit/s *

4 - /BSCLK OUT, a.c. ECL, 53 Mbit/s *

5 - CH0 OUT, width* = 8·7 bucket (» 1.06 m s) **

6 - CH1 OUT, width* = 8·7 bucket (» 1.06 m s) **

7 - CH2 OUT, width* = 8·7 bucket (» 1.06 m s) **

8 - CH3 OUT, width* = 8·7 bucket (» 1.06 m s) **

9 - Ext. OR input

10 - BDE output, width = 7 bucket (» 132 ns)

11 - TDE output, width = 7 bucket (» 132 ns)

12 - $AA output, width = 7 bucket (» 132 ns)

13 - 53 MHz clock output, period = 1 bucket, attenuated TTL

14 - 7.5 MHz clock output, period = 7 bucket, attenuated TTL

    * Optionally, TTL, 7.5 MHz BSCLK might be used. Resolution of 7 bucket would be supported only.

    ** Width of the OR’ed signal coming from Ext. OR input to CH 0 output (and other channel outputs if assigned) remains unchanged and may generally not be equal to (8·7) bucket.
 

LEDs

There are 13 LED’s that indicate unstretched, stretched, or latched signals:

N - CAMAC N-address received, stretched (Red)

L - CAMAC LAM request set, latched (Red)

T - TCLK presents (Green)

H - High-resolution (53 Mbit/s) BSCLK option (Amber)

P - PLL not locked, stretched (Red)

B - BSCLK presents (Green)

CH 0 - CH 0 signal generated (not OR’ed signal ), stretched (Green)

CH 1 - CH 1 signal generated (not OR’ed signal ), stretched (Green)

CH 2 - CH 2 signal generated (not OR’ed signal ), stretched (Green)

CH 3 - CH 3 signal generated (not OR’ed signal ), stretched (Green)

BDE - BDE generated, stretched (Amber)

TDE - TDE generated, stretched (Amber)

$AA - $AA generated, stretched (Amber)
 

Replacement of C479 Module

Generally, every used C479 module has its unique version (X.XX.X). Before the replacement of a failed module its version must be installed in a spare C479 module. For this installation the version EPROM, DIP-8 ALTERA chip, programmed for the proper version should be inserted in the socket, position U22 at the board. To get the proper EPROM you may:

• Remove the EPROM chip (assumed in good condition) from the failed module. The chip has the version number on its label: cdV XXXX month / year. Or
• Program a new EPROM chip, ALTERA EPC1213PC8, using ALTERA programming tools and the POF programming file generated for this version and stored. The file name is cdvXXXX.pof

Group of Versions with Direct Output Pulse

A group of versions of C479 modules has been designed for timing of kickers that use power supplies with a long self-discharging time. Such power supply having been charged may failure in the following cycle if its trigger signal is missed in the current cycle. It happens when generation of a BSCLK event, serving as a reference for the trigger, is denied for any reason at a transmission part of the BSCLK system.

In this case, the C479 with this new version generates an additional pulse using the "end of cycle" TCLK event and delivers it directly to the output of the channel assigned for the trigger. Width of the direct pulse is 100 ns (one TCLK tick) and differs from the width of a normal output pulse that is about 1 µs. Three mutual conditions for generation of the direct pulse should meet: first, the cannel is enabled, second, the channel is armed, and third, absence of the reference BSCLK event. It should be noted that the direct pulse also disarms the channel, as a normal output pulse would do.

Modules of this version group with direct output pulse use the new timer EPROM, Timer 42 (or TM42) while modules of all other versions use the non-modified timer EPROM, Timer 4 (or TM4, or TM). Attention on installation of the adequate timer EPROM should be taken when replacing the C479 module.