Card Type | A | R | SA | Data Description | Digital Bit Flags | Description | |||||||
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7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | ||||||
Pirani | 0 | 1 | 0x0 | fault status | f | e | d | c | b | a | Fault status for each guage. A fault is generated if the cable is disconnected. | ||
0 | 1 | 0x1 | permit status | f | e | d | c | b | a | Permits for each of 6 gauges | |||
1 | 1 | 0x0 | gauge A | analog | Channels 0-5 from each of 6 Pirani guages. The gauges measure from atmospheric to 0.1 milliTorr. The corresponding voltage range is 9 volts (full scale) to 0.3 volts. A permit is generated when the pressure falls to 3 milliTorr. | ||||||||
1 | 1 | 0x1 | gauge B | analog | |||||||||
1 | 1 | 0x2 | gauge C | analog | |||||||||
1 | 1 | 0x3 | gauge D | analog | |||||||||
1 | 1 | 0x4 | gauge E | analog | |||||||||
1 | 1 | 0x5 | gauge F | analog | |||||||||
1 | 1 | 0x6 | ground | analog | Calibration voltages. | ||||||||
1 | 1 | 0x7 | +10V | analog | |||||||||
Cold Cathode | 0 | 0 | 0x0 | turn all gauges on | Turns all guages on. Digital data is not used. | ||||||||
0 | 1 | 0x0 | on/off status, channels 0-7 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | Status for channels 0-7. | |
0 | 1 | 0x1 | on/off status, channels 8-11 | 11 | 10 | 9 | 8 | Status for channels 8-11. | |||||
1 | 1 | 0x0 | gauge 0 | analog | Channels 0 - 11 correspond to one of 12 cold cathode gauges. The guages measure from 0.3 milliTorr to 0.1 microTorr. The corresponding voltage range is 1.2 volts (full scale) to 7.2 volts. When the power is off, it should read 9.0 volts. Each gauge is turned on by a Pirani permit. | ||||||||
1 | 1 | 0x1 | gauge 1 | analog | |||||||||
1 | 1 | 0x2 | gauge 2 | analog | |||||||||
1 | 1 | 0x3 | gauge 3 | analog | |||||||||
1 | 1 | 0x4 | gauge 4 | analog | |||||||||
1 | 1 | 0x5 | gauge 5 | analog | |||||||||
1 | 1 | 0x6 | gauge 6 | analog | |||||||||
1 | 1 | 0x7 | gauge 7 | analog | |||||||||
1 | 1 | 0x8 | gauge 8 | analog | |||||||||
1 | 1 | 0x9 | gauge 9 | analog | |||||||||
1 | 1 | 0xA | gauge 10 | analog | |||||||||
1 | 1 | 0xB | gauge 11 | analog | |||||||||
1 | 1 | 0xC | calibration | analog | Calibration voltages | ||||||||
1 | 1 | 0xD | calibration | analog | |||||||||
1 | 1 | 0xE | calibration | analog | |||||||||
1 | 1 | 0xF | calibration | analog | |||||||||
Ion Pump | 0 | 0 | 0x0 | on/off control, pumps 0,1,2,3 | off | on | off | on | off | on | off | on | Bit 0 and 1 controls pump 0
Bit 2 and 3 controls pump 1 Bit 4 and 5 controls pump 2 Bit 6 and 7 controls pump 3 |
0 | 0 | 0x1 | on/off control, pumps 4,5 | off | on | off | on | Bit 0 and 1 controls pump 4
Bit 2 and 3 controls pump 5 |
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0 | 0 | 0x2 | reset selected pumps | 5 | 4 | 3 | 2 | 1 | 0 | Resets for pumps 0 - 5. | |||
0 | 1 | 0x0 | status, pumps 1 and 0 | p | g | o | p | g | o | Three bits of status each for pumps 0 and 1: permit, good, and on. Bits 0-2 are returned from pump 0, bits 3-5 from pump 1. | |||
0 | 1 | 0x1 | status, pumps 3 and 2 | p | g | o | p | g | o | Three bits of status each for pumps 2 and 3: permit, good, and on. Bits 0-2 are returned from pump 2, bits 3-5 from pump 3. | |||
0 | 1 | 0x2 | status, pumps 5 and 4 | en | g | o | g | o | Two bits of status each for pumps 4 and 5: good and on. Bits 0-2 are returned from pump 4, bits 3-5 from pump 5. An enable, bit 8, is generated onboard if two or more permits from pumps 0 - 3 are active. There are no permits associated with these pumps. | ||||
1 | 1 | 0x0 | pump 0 | analog | Channels 0 - 5 correspond to one of 6 ion pumps or guages. Voltage range is from 0.1 volts (full scale) to 9.0 volts. | ||||||||
1 | 1 | 0x1 | pump 1 | analog | |||||||||
1 | 1 | 0x2 | pump 2 | analog | |||||||||
1 | 1 | 0x3 | pump 3 | analog | |||||||||
1 | 1 | 0x4 | pump 4 | analog | |||||||||
1 | 1 | 0x5 | pump 5 | analog | |||||||||
1 | 1 | 0x6 | +10V | analog | Calibration voltages | ||||||||
1 | 1 | 0x7 | Gnd | analog | |||||||||
Sector Valve | 0 | 0 | 0x0 | open/close command, up, down, BVs | res | c | o | c | o | Bit 0 and 1 control the upstream valve
Bit 2 and 3 control the downstream valve Bit 7 resets the air bit |
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0 | 1 | 0x0 | status, up, downstream beam valves | en | rq | c | o | en | rq | c | o | Returned from upstream and downstream beam valves, enable, request to open, open and closed status. Bit 0-3 from the upstream valve, bits 4-7 from the downstream valve. | |
0 | 1 | 0x1 | status, upstream warm sector valves | air | c | o | he | uve | c | o | From upstream sector valves. House enable and upstream valve enable bits are generated on board. The air bit is an auxilary i/o connection to an air pressure switch. | ||
0 | 1 | 0x2 | status, downstream sector valves | c | o | c | o | Close/open status from downstream sector valves. | |||||
Manifold Valve | 0 | 0 | 0x0 | open/close command, up, down MVs | res | c | o | c | o | Bit 0 and 1 control the upstream valve Bit 2 and 3 control the downstream valve Bit 7 resets the air bit | |||
0 | 1 | 0x0 | status, up, downstream valves | dp | rq | c | o | dp | rq | c | o | Upstream, downstream valves. Differential pressure across the valve, request to open, close and open. Bits 0-3 are returned from the upstream valve, bits 4-7 from the downstream valve. | |
0 | 1 | 0x1 | status, air pressure | air | Air bit from an air pressure switch. | ||||||||
Roughing Station | 0 | 0 | 0x0 | open/close RV, on/off RP | res | off | on | c | o | c | o | Bits 0 and 1 control the upstream valve
Bits 2 and 3 control the downstream valve Bit 7 resets the air bit |
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0 | 1 | 0x0 | status, up,
downstream rough valve |
dp | rq | c | o | dp | rq | c | o | Upstream, downstream roughing valve. Differential pressure across the valve, request to open, close, and open. Bits 0-3 are returned from the upstream valve, bits 4-7 from the downstream valve. | |
0 | 1 | 0x1 | status, RP, TP | air | g | o | drp | <1 | o | Roughing pump status. Bits are as follows: 7 - air bit; 5 pump is good; 4 - pump is on. 2 - change in pressure across the pump exceeds a predetermined amount. The pump will shut itself off when this bit is set. 0 - pump on; 1 - pressure across the pump is less than 1 torr. | |||
Status and Analog Monitor | 0 | 0 | 0x0 | on/off control for all sublimation pumps |
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Only bit 0 is used to control pumps. Setting bit 0 will start
all pumps
previously enabled. Enabling is the pumps is done manually. |
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0 | 1 | 0x0 | status pumps 0 and 1 |
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Three bits of status for each pump(true=1)
f=filament on/off e=emission enabled/fault d=degas/sublimate |
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0 | 1 | 0x1 | status pumps 2 and 3 |
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0 | 1 | 0x2 | status pumps 4 and 5 |
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0 | 1 | 0x3 | status pumps 6 and 7 |
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0 | 1 | 0x4 | status pump 8 and roughing station |
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Three bits, def, fro pump 8
Three bits for roughing station(true=1) roughing valve closed roughing valve open roughing pump on |
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1 | 1 | 0x0 | pump 0 |
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channels 0-8 correspond to one of 9 sublimation pumps
1 volt = 10 amps |
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1 | 1 | 0x1 | pump 1 |
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1 | 1 | 0x2 | pump 2 |
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1 | 1 | 0x3 | pump 3 |
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1 | 1 | 0x4 | pump 4 |
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1 | 1 | 0x5 | pump 5 |
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1 | 1 | 0x6 | pump 6 |
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1 | 1 | 0x7 | pump 7 |
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1 | 1 | 0x8 | pump 8 |
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1 | 1 | 0x9 | turbo speed (obsolete) |
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1 | 1 | 0xC | +6 Volts |
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calibration channels | ||||||||
1 | 1 | 0xD | +7.5 Volts |
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1 | 1 | 0xE | +9 Volts |
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1 | 1 | 0xF | Gnd |
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Thermocouples | 0 | 0 | 0x0 | set low ptr for mux |
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Thermocouple (TC) readings are muxed.
A 0 is 1st written to the low mux ptr. Successive reads then cause this ptr to cycles thru 12 stat/ temperature pairs per TC, for a given sep. The full table here actually has 24 reads for each of 8 seps. What you see here just tries to represent that in abbreviated form. An example of a database device channel # is: a chan 12 reading is digital read of TC 0 for sep 1. Database property determines whether get temperature, or status. |
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0 | 0 | 0x7 | reset TC processor |
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0 | 0 | 0xf | set high addr ptr |
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0 | 1 | 0x0 | TC 0, separator 0
status |
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0 | 1 | 0x0 | TC 0, separator 0
temperature |
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0 | 1 | 0x0 | TC 1, sep 0
status |
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0 | 1 | 0x0 | TC 1, sep 0
temperature |
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0 | 1 | 0x0 | TC 2, sep 0
status |
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0 | 1 | 0x0 | TC 2, sep 0
temperature |
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0 | 1 | 0x0 | TC 3, sep 0
status |
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0 | 1 | 0x0 | TC 3, sep 0
temperature |
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0 | 1 | 0x0 | TC 4, sep 0
status |
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0 | 1 | 0x0 | TC 4, sep 0
temperature |
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0 | 1 | 0x0 | TC 5, sep 0
status |
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0 | 1 | 0x0 | TC 5, sep 0
temperature |
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0 | 1 | 0x0 | TC 6,sep 0
status |
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0 | 1 | 0x0 | TC 6, sep 0
temperature |
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0 | 1 | 0x0 | TC 7, sep 0
status |
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0 | 1 | 0x0 | TC 7, sep 0
temperature |
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0 | 1 | 0x0 | TC 8, sep 0
status |
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0 | 1 | 0x0 | TC 8, sep 0
temperature |
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0 | 1 | 0x0 | TC 9, sep 0
status |
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0 | 1 | 0x0 | TC 9, sep 0
temperature |
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0 | 1 | 0x0 | TC 10, sep 0
status |
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0 | 1 | 0x0 | TC 10, sep 0
temperature |
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0 | 1 | 0x0 | TC 11, sep 0
status |
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0 | 1 | 0x0 | TC 11, sep 0
temperature |
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0 | 1 | 0x1 | TC 0, sep 1
status |
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0 | 1 | 0x1 | TC 0, sep 1
temperature |
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0 | 1 | 0x1 | TC 1, sep 1
status |
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0 | 1 | 0x1 | TC 1, sep 1
temperature |
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~ | ~ | ~~~ | ~~~~~~~~~~~ |
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0 | 1 | 0x1 | TC 11, sep 1
status |
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0 | 1 | 0x1 | TC 11, sep 1
temperature |
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~ | ~ | ~~~ | ~~~~~~~~~~~ |
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0 | 1 | 0x7 | TC 0, sep 7
status |
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0 | 1 | 0x7 | TC 0, sep 7
temperature |
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~ | ~ | ~~~ | ~~~~~~~~~~~ |
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0 | 1 | 0x7 | TC 11, sep 7
status |
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0 | 1 | 0x7 | TC 11, sep 7
temperature |
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Heaters | 0 | 0 | 0x0 | Relay 0 on_count |
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0 | 0 | 0x1 | relay 1 on_count |
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0 | 0 | 0x2 | relay 2 on_count |
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0 | 0 | 0x3 | relay 3 on_count |
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0 | 0 | 0x4 | relay 4 on_count |
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0 | 0 | 0x5 | relay 5 on_count |
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0 | 0 | 0x6 | relay 6 on_count |
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0 | 0 | 0x7 | relay 7 on_count |
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0 | 1 | 0x0 | Relay 0 on_count |
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0 | 1 | 0x1 | relay 1 on_count |
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0 | 1 | 0x2 | relay 2 on_count |
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0 | 1 | 0x3 | relay 3 on_count |
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0 | 1 | 0x4 | relay 4 on_count |
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0 | 1 | 0x5 | relay 5 on_count |
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0 | 1 | 0x6 | relay 6 on_count |
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0 | 1 | 0x7 | relay 7 on_count |
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0 | 1 | 0x8 | clock present status | c | digital read | ||||||||
0 | 1 | 0x9 | relay on/off status | h7 | h6 | h5 | h4 | h3 | h2 | h1 | h0 | Status of heater for heaters 7 to 0 |
Chip Select | /UCS | Used to select program memory. Here we are using flash memory -- 1 Mbyte. |
/LCS | RAM select -- 128K words of RAM supplied -- 0 - 1FFFFH. | |
/GCS0 | Data Way Interface EPLD | |
/GCS1 | Not used | |
/GCS2 | Arcnet controller - COM20020, byte wide port (D0-D7).
Details in COM20020 data sheet. |
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/GCS3 | Not used. | |
/GCS4 | Not used. | |
/GCS5 | Display and switch port, at address 0, 1 word.
Write word -- writes LEDs (No longer controlable by software) Read word -- reads DIP switches (16 switches) |
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/GCS6 | Not used | |
/GCS7 | ARCNET Reset on either a read or write to this area | |
Interrupts | NMI | Not used, tied to ground |
INT0 | DWC_DONE -- Data Way Controller cycle done | |
INT1 | ARCINT -- Arcnet Controller interrupt. | |
INT2 | Not used | |
INT3 | Not used | |
INT4 | Not used |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
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A | R | MS[3..0] | AS[3..0] |
MS[3..0] | Module select, 0-15 |
AS[3..0] | Module sub-address, 0-15 |
A | Analog |
R | Reading |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
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ERR | D[11..0] |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
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DRDY | DWO | NACK | ATO |
DRDY | Dataway ready. Set upon completion of a dataway cycle. Reset by writing to the address register. For digital and analog read cycles, DRDY indicates that the data and status registers are valid. For digital write cycles, DRDY indicates that the write cycle completed and the status register is valid. |
DWO | Dataway overlap. Set when the processor attempts to initiate a new dataway cycle while a cycle is in progress. Reset by writing to the status register. |
NACK | Module negative acknowledge. Set if the selected module fails to respond to a dataway cycle. Reset by writing to the status register. |
ATO | ADC tieout. Set if an analog read dataway cycle is aborted. Reset by writing to the status register. |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
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AIE | DIE | SMR |
AIE | Analog Interrupt Enable. If set, the processor will be interrupted when DRDY goes active after an analog read cycle. |
DIE | Digital Interrupt Enable. If set, the processor will be interrupted when DRDY goes active after a digital read or write cycle. |
SMR | State Machine Reset. If set, the dataway cycle controller is reset to the idle state. Reset is held until SMR is reset. |
Digital Write Cycle:
1. Write data to the low byte of the data register.
2. Write module select, address, and cycle type to address register.
3. Poll the status register for DRDY or wait for DRDY interrupt.
4. Check status register for errors.
Digital Read Cycle:
1. Write module select, address, and cycle type to address register.
2. Poll the status register for DRDY or wait for DRDY interrupt.
3. Read the data register.
4. Check status register if error flag is set.
Analog Read Cycle:
1. Write module select, address, and cycle type to address register.
2. Poll the status register for DRDY or wait for DRDY interrupt.
3. Read the data register.
4. Check status register if error flag is set.
The datway controller holds its interrupt line active until the status register is read. The address and dataway write-data registers are locked while a dataway cycle is in progress.
The VIOB needs to be configured based on the configuration of the crates the front end is communicating with. The configuration information need by the VIOB is the card type in each slot of each crate. This configuration information is stored in the static variable crateConfig, which is defined in the front end source code file viob_create.c. Therefore reconfiguring the VIOB requires a edit-compile-reboot cycle. The VIOB for each crate controller is configured dynamically using the static configuration information from the front end. When a crate controller boots it requests that the front end send it an expectation table which contains it its crate configuration. The VIOB uses unique integers to indentify board types in the expectation table. The controllers and the front end must agree on the correspondence between integers and board types. This correspondence is defined by the BOARD_TYPE enumeration in the boards.h header file. Both the front end and controller source code have a boards.h file, the definition of the BOARD_TYPE enumeration must be the same in both files. However, the boards.h files contain other differences which prevent using a single file for both the front end and crate controller software. Note that the enumeration constant ENDM is the number of board types; it does not correspond to a board type. The boards.h files and viob_create.c would needed to be edited if a new board type was to placed in a crate, otherwise reconfiguration only requires modifications to viob_create.c.
Due to the need to convert ion pump readings to engineering units the front-end must be configured with what conversions are to be applied to each ion pump channel. This configuration information is in mivdev.c which must be updated when the ion pump configuration is changed.
Each controller and the front end has a special section of memory, which holds values received over the VIOB and values to be transmitted over the VIOB. The format of this memory depends on the configuration but is otherwise static. That is, for a particular configuration the value at a particular offset in this memory will always be the value of a particular data item. On the front end one does not directly read or write this special memory, but instead uses the routines vset_data and vread_data, which sets or reads data items from this memory based on the calling arguments which specify crate, slot, channel, etc. On the crate controllers one directly accesses this special section of memory. The data items from each card occupy a contiguous section of this special memory both on the front end and on the crate controller for that card. The amount of memory depends on the card type. In order for the front end VIOB to know how much space a card uses it must know the total number of analog and digital readings, the number of digital settings, and the total number of status readings. This information is made available to the front end VIOB software via the static variable boards defined in boards.h. The controller software also needs to know how much memory each card type requires. The controller software file dwc.c has arrays which provide the software with the list of data items for each card type. From these arrays the number of data items can be computed. The global variable boards is then initialized with the computed values. Therefore, since the controllers and the front end come up with the number of data items for each card type independently, one must insure that the front end's boards array in boards.h is consistent with the arrays in the controller's dwc.c file.
The order of data items in dwc.c's data item arrays determines the association of each data item to a VIOB channel. The sequence of readings and settings is the same as in the arrays. The sequence of status values is the same as in the arrays with the digital setting statuses first and the reading statuses next. There is some special logic involved with the setting data items. So that a controller does not try to set a setting with an unintialized value from the the VIOB memory, a setting value must have its most-significant bit, the valid bit, set to indicate it has been initialized from the front end. In addition the controller will only set a setting if the value has changed or a reset bit of the setting is set. Which bits the controller considers to be reset bits is defined in dwc.c's data item arrays.