Epicure Design Note 120.0

Paul A. Kasley

22 December 1992

Specification for an 8-by-4 Serial Link Multiplexer

I. Objective

This is a hardware design specification for a serial link multiplexer to replace the 4-by-4 link mux currently in use. The link multiplexer is a device that routes serial data between up to eight beamline front end processors and the four serial CAMAC links on a demand basis. It is comprised of three major blocks: an arbiter to assign links to front ends, a crosspoint switch to perform the actual routing and a diagnostic block to accumulate loading statistics. The proposed device shall support up to eight front ends and up to four serial links.

II. Specifications

A. General

1. The link mux shall assign available links using a priority scheme. Front ends shall be granted access to links with front end "A" having the highest priority and front end "H" having the lowest priority.

2. The crosspoint switch shall allow all four serial links to be routed to four different front ends simultaneously.

3. The card shall use a 2-phase, 10 Mhz clocking scheme such that channel requests are latched by a first clock phase and requests are arbitrated by a second clock phase.

4. All connectors and card dimensions shall be compatible with the 4-by-4 link mux. The 8-by-4 link multiplexer shall occupy a double wide CAMAC slot.

5. Signal pinouts, signal functions, and signal levels shall be fully compatible with the 4-by-4 device. Additional signals needed to support the additional front ends will be placed on connector pins that are presently unused on both the 4-by-4 device and the card slot into which it plugs. This will maintain backward compatibility with, and allow the use of the 4-by-4 mux in the event that the 8-by-4 device should fail.

6. The 8-by-4 requires a number of extra LEDs to maintain the same set of diagnostic indicators as is provided on the 4-by-4 for all channels. Status LEDs shall be grouped for ease of use.

7. The module ID number will be C1300. The module serial number will be a sequence number starting with 1 for unit number 1.

8. The link mux shall be implemented using EPLDs for the bulk of the logic.

B. Link Utilization Monitoring

1. Eight 24 bit binary counters shall be provided to monitor channel and link requests and grants for the purpose of accumulating channel and link loading information.

2. The counter gate period shall be software settable to either one second or one minute. When the one second gate is selected the counters will accumlate link activity in one microsecond increments. With the one minute gate selected the granularity of the counters will be 4 microseconds.

3.The counters will monitor one of four conditions: link grant (Summation of CNL_GRANTn*LINK_ADRS), channel grant (CNL_GRANT), channel request (CNL_REQ), and test count (VCC). Two software control bits will select the variable that all eight counters will monitor for their respective channels. When "link grant" is selected the counters for channels A through D will monitor the link activity while the counters for channels E through H will perform "test count".

4. Each counter will be double buffered. At the end of every count period the contents of a counter will be transferred to a holding register. At the same time the counter will be reset and a new accumulation will begin. A status bit will be provided via the CAMAC "Q" signal to indicate to software if the current content of the holding register for a particular counter was previously read. All counter status bits will be set at the end of a gate period. A read of a holding register will reset the status bit after the read operation has completed.

C. CAMAC Interface

1. The module will not support block transfer.

2. The module will not generate a LAM signal.

3. The Z signal and the C signal will reset all counters and clear the control register.

4. The I signal will disable all register decoding for as long as the signal is asserted.

5. The X signal will be driven only if the addressed function code and register exist.

6. The Q bit will return count status as defined in item II.B.4. above. The flag will be reset at S2 time. Writing to the control register will clear all count status bits and all counters at S2 during the dataway write cycle.

7. CAMAC register and bit assignments:

See Figure 1.

D. Mechanical

1. The module will be a double wide CAMAC module.

2. The following LED indicators shall be provided on the front panel:

(1) Module Addressed

(1) Counters Reset

(1)Gate Select

(4) Function Select

(1) One second Gate

(3) Power

(16) Branch Address

(8) Channel Request

(8) Channel Grant

(16) Serial Transmit and Receive

3. Connectors

Serial Links (8) Lemo-type, mounted on the front panel

Channels A-D Viking connector #1

Channels E-F Viking connector #2

The selection of Viking connector locations and pinouts shall be such that the 4-by-4

and 8-by-4 multiplexers can be swapped.

Figure 1.