Research Division EED/Controls Software<P> Special Project Note #8.0<P> D0 Note #1318<P> OTC Auto Test Program<P> User Manual

Research Division EED/Controls Software

Special Project Note #8.0

D0 Note #1318

OTC Auto Test Program

User Manual

David M. Kline

Contents

Introduction

The purpose of the OTC Auto Test Program is to provide a menu driven program that requires minimal user interaction to test the D0 Muon OTC module hardware by exercising both memory components and hardware sections with simple keystrokes. The program is implemented using Turbo Pascal 6.0 under MS-DOS. Tests are divided in two sections OTC Memory Tests and OTC Trigger Tests which are logically arranged to produce the most efficient testing. The OTC Memory Tests are further divided into tests for each of the OTC memory types . The OTC Trigger Tests are further divided into subtests that may be individually selected by the user. Later sections will describe these menus in detail. The user should be familar with the OTC or had read document D0 Note # 1315, ``Octant Trigger Card (OTC) Hardware Description''.

Control Options

There are control options available which the user may select before executing any of the tests. The options may not be selected during a test and remains in effect until disabled. The state of the option is identified by color: yellow means disabled while green means enabled. By depressing the identified function key the option toggles between yellow and green. The function of each control option is listed below:

Looping
- This option is available for both memory and OTC trigger tests. By selecting this option, the user enables looping on the current test or all tests continuously until the ESC key is depressed. This option is not available with OTC trigger subtests.
Sublooping
- This option is available for OTC trigger subtests only and overrides the looping option when enabled. If this option is enabled and an OTC trigger test is selected, a list of the subtests appears on the screen and prompts the user for a test name. The user then enters the test name and depresses the carriage return key. The subtest executes continuously until the ESC key is depressed.
Logging
- By selecting this option, test error messages which appear on the screen are written to a log file. After the session, the user may view or print the log file for analysis.
Pause
- By enabling this option, the program will pause for every error encountered. The user must depress any key in order to continue with the test. If the user wants to stop outputting error messages but the option is disabled, the pause key may be depressed. To continue depress the carriage return key.

Main Menu

The main menu appears when the program is executed and displays options. The control options as described in the previous section are always displayed towards the bottom of the page. Therefore the user will know at all times which ones are enabled. Status messages are displayed in the status message region located at the bottom of the screen. Below is a list of the options available from the main menu:

Select Board Version
- The user is required to enter the board version of the OTC under test. OTCs may be configured differently by programming the crosspoint PLDs. The board version is a data file containing the crosspoint mappings. The test program reads the information and maintains a table of these mappings in order to generate the expected data returned by the OTC. A description of the data files is provided in later a section.
Switch Board Mode
- This option provides for testing of both the normal and test mode of the baord. One of these modes are selected on the OTC by a dip switch. The program uses the OTC Test Module to read the specific status register and determine the current setting of the dip switch. If there is a difference between the read status and the dip switch setting, an error message is displayed in the status message region of the screen. The user should then place the dip switch at the correct setting.
Select Defaults Menu
- When this option is selected another menu is displayed which lists the defaults that the program uses to test an OTC. A later section describes these options.
OTC Memory Tests Menu
- This option displays a list of available memory tests for an OTC. A later section describes these tests.
OTC Trigger Tests Menu
- This option displays another menu that lists the tests which exercise the hardware sections. A later section describes these tests.
Execute Both Memory and OTC Trigger Tests
- By selecting this test, the user executes all tests listed in the ``OTC Memory Tests'' and ``OTC Trigger Tests'' menus. If the looping control option is enabled, all tests are executed continuously until the ESC key is depressed.

Select Defaults Menu

The Select Defaults Menu contains options that maintain the OTC and OTC test module addresses and bit masks used by both OTC memory and trigger tests. Modifications made are placed into a binary file so consistent defaults may be used between sessions. The user selects the option by depressing the letter to the left of the option description and is queried for a value. The menu may be exited at any time by depressing the ESC key. These options are:

Kinematic Address Mask
- The kinematic address mask is used by the address memory test to determine what addresses are written ones. The address mask is limited to 14 bits . A later section describes the kinematic address test in more depth.
M1 & M2 Address Mask
- Similar to the kinematic address test, this mask is used by the M1 & M2 memory address test. The address mask is limited to 18 bits . A later section describes the M1 & M2 address mask test.
OTC Module Select
- This value identifies the OTC VME address. The value should reflect the OTC dip switch settings.
OTC Test Module Select
- This value identifies the OTCs on the OTC/MGR bus. The value should reflect the OTC dip switch settings.
Error Log Size
- The value limits the number of error messages written to the log file. A value of zero indicates that an unlimited number of messages may be written.

OTC Memory Tests Menu

This menu provides a list of OTC memory tests available to the user. The memory tests are divided into OTC memory types: M1, M2, K1 & K2, and K3. The user selects an option by depressing the letter to the left of the option description. The menu may be exited any time by depressing the ESC key. Below lists the options:

M1 Memory Tests
- Selecting this option displays the memory tests which are available for the M1 memory. Depressing the ESC while in this menu returns the user to the OTC Memory Tests Menu.
M2 Memory Tests
- Selecting this option displays the memory tests which are available for the M2 memory. Depressing the ESC while in this menu returns the user to the OTC Memory Tests Menu.
K1 & K2 Memory Tests
- Selecting this option displays the memory tests which are available for the K1 & K2 memories. Depressing the ESC while in this menu returns the user to the OTC Memory Tests Menu.
K3 Memory Tests
- Selecting this option displays the memory tests which are available for the K3 memory. Depressing the ESC while in this menu returns the user to the OTC Memory Tests Menu.
Execute All Memory Tests
- By selecting this option, all OTC memory tests for each memory are executed in the order listed on this menu.

For each memory option selected, a menu is displayed requiring the user to select the type of memory test to execute. The available memory tests are:

Zeros Test
- This test writes zeros (0) to all memory locations for the OTC memory type. Then each location is read and compared to what is expected. If the values do not match an error message is output to the error message area of the screen.
Ones Test
- This test is similar to the zeros test except that ones (1) are written and compared.
Random Test
- The random test generates a random value in the range of the memory type then writes to and reads from the same memory location. If the values do not match an error message is output to the error message area of the screen.
Address Test
- The address test is a walking ones test. The memory is cleared by writing zeros to all locations to assure a known state. The address masks , defined by the Select Defaults Menu, are used to determine the addresses to which ones (1) are written to. A one (1) is shifted to the left by one and compared with the address mask. If the comparison is successful, a one is written to that address. The address is then placed into a lookup table for later use. Next all memory locations are read for their expected values. The address is searched for in the lookup table and if found, a one (1) is expected and compared, otherwise a zero (0) is expected and compared. If the values do not match, a message is output to the error message area of the screen.
Execute All Tests
- Selecting this test executes all memory tests for the selected memory type.

After the user has selected a memory test, the screen is divided into four parts. At the top a header is displayed with the test name and the column headers: Test Name, Subtest Name, VME address, Expected Data, Read Data, and Error count. If looping is enabled another column is displayed as Loop Count. In addition the current loop count is displayed in the upper left hand corner of the screen. The header background color is blue with yellow print. The next section is the test error message area where the errors are output. The background color is white with black print. Just below the error message area is the query region, identified by a green background with black print. This area is used to prompt the user for input required by the test. For example, if the Pause control option was enabled and the test encountered an error, the user is prompted to continue from this area. If the Pause control option is not enabled and the user wants to stop the error messages, the pause key on the keyboard may be depressed. To continue output, the carriage return key must be depressed. The next two areas are the control option and status message area which are described in previous sections.

OTC Trigger Tests Menu

The OTC Trigger Tests Menu contains the tests which exercise individual hardware sections of the OTC. The OTC Test Module is used in conjunction with the tests to simulate MAC layer input and output.

Each test has its own data file which contains the test vectors that are downloaded to the OTC test module or the OTC directly. The program uses these vectors to determine the expected return data. The data is read from the OTC Test Module data output FIFOs or the OTC directly and compared with the data expected. If the values do not compare, an error is output to the error message area. Below are the available tests:

VME Input Layer Test
- Both the OTC and OTC Test Module are used to test the layer input bit data path through VME and the XPT A1, B1, & C1 crosspoints. The test data file VMEINBIT.ASC provides the test vectors which are downloaded to the OTC through VME and read back through the OTC Test Module data output FIFOs. Any data error encountered is output on the error message area located on the screen.
MAC Input Layer Test
- The OTC Test Module is used to test the MAC layer input bit data paths and crosspoints. The test data file MACINBIT.ASC vectors are downloaded to the OTC Test Module, tone bursted to the OTC, and read back from its data output FIFOs. Any data error encountered is output on the error message area located on the screen.
Asynchronous Test
- The OTC Test Module is used to test the asynchronous trigger logic. The test vectors from the data file ASYNC.ASC are downloaded to the OTC Test Module, tone bursted to the OTC, and read back from its data output FIFOs. Any data error encountered in output on the error message area located on the screen.
Input SRAM & FIFO Test
- The purpose is to test the input SRAMs, input FIFO, and overflow error monitor. The test vectors supplied by the data file FIFORAM.ASC are used to produce the desired status from each of the MAC layer inputs A, B, & C. Any data error encountered iS output on the error message area located on the screen.
SAM1 Synchronous Test
- This test exercises the SAM1 microsequencer and the processing logic of the input sequencers. The test vectors from the data file SYNCPROC.ASC is loaded into the OTC Test Module MAC layer data input FIFOs and read back from its data output FIFOs. Any data error encountered is output on the error message area located on the screen.
Manager Output FIFO Test
- The purpose of this test is to download the OTC Test Module with test vectors, using the MANOUT.ASC datafile, that will fill all 256 OTC output FIFO locations. Any data error encountered iS output on the error message area located on the screen.
VME Output/RTOF FIFO Test
- The OTC Test Module is downloaded similarly to the Manager Output FIFO Test but read back from the OTC directly. After the test has completed, a command is sent to reset the data output FIFO read pointers and read and verify them again. Any data error encountered in output on the error message area located on the screen.
Pair Find Output Test
- The purpose of this test is to exercise the pair find output data bits. Any data error encountered is output on the error message area located on the screen.
Execute All Tests
- When this option is depressed, all OTC Trigger Tests are executed. If the looping option is enabled, the test executes continuously until the user depresses the ESC key.

After the user has selected an OTC trigger test, the screen is formatted similarly to the OTC memory tests. The test header is displayed with the test name and the column headers which are: Test Name, Subtest Name, First Word (Read/Expected), Second Word (Read/Expected), Pair Find (Read/ Expected), and Error count. If looping is enabled another column is displayed as Loop Count. In addition the current loop count is displayed in the upper left hand corner of the screen. The only difference with the memory test screen is the column headers.

Data files

The program uses data files to provide the test vectors that are downloaded to the OTC Test Module or the OTC directly. This section provides a description of the data files required by the program.

The program uses a binary file that contains the defaults selected and modified from the Select Defaults Menu. Each of the options are written to the file as the user selects and modifies them. When the program is executed, it reads the defaults and places them into global variants that are used by all tests. Presently the file is named OTCDEFS.DAT.

Each OTC under test may have its PLDs configured differently and are described by the bit mapping defined within the board version data file. The file is divided into two main areas: Header and crosspoints. The header area defines the crosspoint serial numbers and is used for documentation purposes. The crosspoint area defines the PLD bit mappings for each memory type. When the need arises to define another OTC board version, the data file may be copied and edited using any text editor. Furthermore, the data within must adhere to the predefined format in order to operate correctly.

Each test located on the OTC Trigger Test Menu requires a data file. The data file contains test vectors that are either downloaded to the OTC Test Module or OTC directly, depending on the test. The file is divided into subtests which may be executed individually if the sublooping control option is enabled. A subtest is defined by name; MAC layer test vectors; expected triggers; scanned status bit mask; and expected status bit mask. Regardless of the control option settings, the program scans the data file for the name identifier and places it into a global variant . Next the test vectors are read and loaded into the OTC Test Module or the OTC directly. Following are the triggers that are used to generate the data that is expected to be read from the OTC Test Module or OTC data output FIFOs. The expected data is placed into a lookup table and scanned after the data FIFOs are read. Since the returned data arrangement is not guaranteed, the program scans the lookup table linearly for each trigger.

After the expected trigger data are masks which are used to compare with the OTC specific status data. The scanned status mask is used to indicate which status bits to test and the expected status mask indicates the value that should be read from the specific status register.

Following the mask words is the end subtest indicator. At this point the program produces the appropriate signal to execute the test. After the test is completed, the program reads the specific status register and the data output FIFOs. It compares the status with both the scanned and expected bit masks and outputs any errors to the error message area. If the status masks are successful, the program searches through the lookup table and attempts to match the read data with the expected data. If the read values are not matched with any of the entries in the table, an error message is output to the error message area.

Names

This section provides a list of the data file names used by the program and what test uses them:

ASYNC.ASC
- Used by the Asynchronous Processing Test
MACINBIT.ASC
- Used by the MAC Input Bit Layer Test.
FIFORAM.ASC
- Used by the Input SAM & FIFO Test.
SYNPROC.ASC
- Used by the SAM1 Synchronous Processing Test.
OUTFIFO.ASC
- Used by the Output FIFO Test.
VMEINBIT.ASC
- Used by the VME Input Bit Layer Test.
PFOUT.ASC
- Used by the PF Output Test.
BRDVERxx.ASC
- Used to describe the bit mapping of the crosspoints.
TRIGDATA.ASC
- Used to download the trigger memories M1 & M2.
OTCDEFS.DAT
- Used to preserve defaults between testing sessions.

Operation

This section describes the procedures necessary to execute the OTC Auto Test program. Initially, the user is required to verify that the OTC Test Module and the OTC under test are in the VME crate and set up correctly. Next the computer may be booted unless already running. The user must change to directory `` OTCAUTO'' to execute the test. At the DOS prompt enter OTC to execute the program; the main menu is displayed. The user should then select the `` Select Board Version'' option and enter the board version data file name of the OTC under test. The program will automatically setup the internal tables and variables. The defaults should be checked before any of the tests are executed. Enter the `` Select Defaults Menu'' and verify that the ones listed are valid. At this point the user is ready to execute memory or OTC trigger tests by depressing the option identifier to the left of the description. Depressing the ESC key returns the user to either the next higher or main menu. To exit the program, depress the ESC key at the main menu and the DOS prompt will appear.

Appendix: Data File Examples

This appendix contains the data files used by the program describing their format and contents:

! FILENAME: ASYPROC.ASC ! DESCRIPTION: ASYNCRONOUS PROCESSING TEST ! DATE: 3/16/92 ! ! FORMAT: N=Ci,j ! A=n1 n2 n(m) ! B=n1 n2 n(n) ! C=n1 n2 n(p) ! ! ! A B C ! T=A B C ! : ! : ! : N=C1,1 A=0021 B=0001 0002 0003 0004 C=0001 0002 0003 0004

! A B C T=0021 0001 0001 M=01FF S=013C E

N=C1,2 A=0022 B=0001 0002 0003 0004 C=0001 0002 0003 0004

! A B C T=0022 0001 0002 M=01FF S=013C E

N=C1,3 A=0023 B=0001 0002 0003 0004 C=0001 0002 0003 0004

! A B C T=0023 0001 0003 M=01FF S=013C E

N=C1,4 A=0024 B=0001 0002 0003 0004 C=0001 0002 0003 0004

! A B C T=0024 0001 0004 M=01FF S=013C E

N=C2,1 A=0025 B=0001 0002 0003 0004 C=0001 0002 0003 0004

! A B C T=0025 0002 0001 M=01FF S=013C E

N=C2,2 A=0026 B=0001 0002 0003 0004 C=0001 0002 0003 0004

! A B C T=0026 0002 0002 M=01FF S=013C E

N=C2,3 A=0027 B=0001 0002 0003 0004 C=0001 0002 0003 0004

! A B C T=0027 0002 0003 M=01FF S=013C E

N=C2,4 A=0028 B=0001 0002 0003 0004 C=0001 0002 0003 0004

! A B C T=0028 0002 0004 M=01FF S=013C E

N=C3,1 A=0029 B=0001 0002 0003 0004 C=0001 0002 0003 0004

! A B C T=0029 0003 0001 M=01FF S=013C E

N=C3,2 A=002A B=0001 0002 0003 0004 C=0001 0002 0003 0004

! A B C T=002A 0003 0002 M=01FF S=013C E

N=C3,3 A=002B B=0001 0002 0003 0004 C=0001 0002 0003 0004

! A B C T=002B 0003 0003 M=01FF S=013C E

N=C3,4 A=002C B=0001 0002 0003 0004 C=0001 0002 0003 0004

! A B C T=002C 0003 0004 M=01FF S=013C E

N=C4,1 A=002D B=0001 0002 0003 0004 C=0001 0002 0003 0004

! A B C T=002D 0004 0001 M=01FF S=013C E

N=C4,2 A=002E B=0001 0002 0003 0004 C=0001 0002 0003 0004

! A B C T=002E 0004 0002 M=01FF S=013C E

N=C4,3 A=002F B=0001 0002 0003 0004 C=0001 0002 0003 0004

! A B C T=002F 0004 0003 M=01FF S=013C E

N=C4,4 A=0031 B=0001 0002 0003 0004 C=0001 0002 0003 0004

! A B C T=0031 0004 0003 M=01FF S=013C E

N=CALL A=0011 B=0001 0002 0003 0004 C=0001 0002 0003 0004

! A B C T=0011 0001 0001 T=0011 0001 0002 T=0011 0001 0003 T=0011 0001 0004 T=0011 0002 0001 T=0011 0002 0002 T=0011 0002 0003 T=0011 0002 0004 T=0011 0003 0001 T=0011 0003 0002 T=0011 0003 0003 T=0011 0003 0004 T=0011 0004 0001 T=0011 0004 0002 T=0011 0004 0003 T=0011 0004 0004 M=01FF S=013C E ! ! End of test data

! FILENAME: FIFORAM.ASC ! DATE: 3/19/92 ! DESCRIPTION: INPUT SRAM AND FIFO TEST ! ! FORMAT: N=TSTNAME ! A=n1 n2 n(m) ! B=n1 n2 n(n) ! C=n1 n2 n(p) ! ! ! A B C ! T=TA1 TB1 TC1 ! : : : ! : : : ! : : :

N=AFIFO-A A=282A 282A 282A 282A 282A 282A 282A 282A 282A 282A A=282A 282A 282A 282A 282A 282A 282A 282A 282A 282A A=282A 282A 282A 282A 282A 282A 282A 282A 282A 282A 282A B=0000 C=0000

! A B C T=282A 0000 0000 T=282A 0000 0000 T=282A 0000 0000 T=282A 0000 0000 T=282A 0000 0000 T=282A 0000 0000 T=282A 0000 0000 T=282A 0000 0000 T=282A 0000 0000 T=282A 0000 0000 T=282A 0000 0000 T=282A 0000 0000 T=282A 0000 0000 T=282A 0000 0000 T=282A 0000 0000 T=282A 0000 0000 T=282A 0000 0000 T=282A 0000 0000 T=282A 0000 0000 T=282A 0000 0000 T=282A 0000 0000 T=282A 0000 0000 T=282A 0000 0000 T=282A 0000 0000 T=282A 0000 0000 T=282A 0000 0000 T=282A 0000 0000 T=282A 0000 0000 T=282A 0000 0000 T=282A 0000 0000 T=282A 0000 0000 M=013F S=0138 E

N=AFIFO-5 A=1015 1015 1015 1015 1015 1015 1015 1015 1015 1015 A=1015 1015 1015 1015 1015 1015 1015 1015 1015 1015 A=1015 1015 1015 1015 1015 1015 1015 1015 1015 1015 1015 B=0000 C=0000

! A B C T=1015 0000 0000 T=1015 0000 0000 T=1015 0000 0000 T=1015 0000 0000 T=1015 0000 0000 T=1015 0000 0000 T=1015 0000 0000 T=1015 0000 0000 T=1015 0000 0000 T=1015 0000 0000 T=1015 0000 0000 T=1015 0000 0000 T=1015 0000 0000 T=1015 0000 0000 T=1015 0000 0000 T=1015 0000 0000 T=1015 0000 0000 T=1015 0000 0000 T=1015 0000 0000 T=1015 0000 0000 T=1015 0000 0000 T=1015 0000 0000 T=1015 0000 0000 T=1015 0000 0000 T=1015 0000 0000 T=1015 0000 0000 T=1015 0000 0000 T=1015 0000 0000 T=1015 0000 0000 T=1015 0000 0000 T=1015 0000 0000 M=013F S=0138 E

N=AINPOVFL A=0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 A=0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 A=0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 C=0001

M=013F S=013B E

N=ASRAM-A A=282A 282A 282A 282A 282A 282A 282A 282A 282A 282A A=282A 282A 282A 282A 282A 282A 282A 282A 282A 282A A=282A 282A 282A 282A 282A 282A 282A 282A 282A 282A 282A B=0001 0001 0001 0001 0000 C=0001 0001 0001 0000

! A B C T=282A 0000 0000 T=282A 0000 0000 T=282A 0000 0000 T=282A 0000 0000 T=282A 0000 0000 T=282A 0000 0000 T=282A 0000 0000 T=282A 0000 0000 T=282A 0000 0000 T=282A 0000 0000 T=282A 0000 0000 T=282A 0000 0000 T=282A 0000 0000 T=282A 0000 0000 T=282A 0000 0000 T=282A 0000 0000 T=282A 0000 0000 T=282A 0000 0000 T=282A 0000 0000 T=282A 0000 0000 T=282A 0000 0000 T=282A 0000 0000 T=282A 0000 0000 T=282A 0000 0000 T=282A 0000 0000 T=282A 0000 0000 T=282A 0000 0000 T=282A 0000 0000 T=282A 0000 0000 T=282A 0000 0000 T=282A 0000 0000 M=013F S=0130 E

N=ASRAM-5 A=1015 1015 1015 1015 1015 1015 1015 1015 1015 1015 A=1015 1015 1015 1015 1015 1015 1015 1015 1015 1015 A=1015 1015 1015 1015 1015 1015 1015 1015 1015 1015 1015 B=0001 0001 0001 0001 0000 C=0001 0001 0001 0000

! A B C T=1015 0000 0000 T=1015 0000 0000 T=1015 0000 0000 T=1015 0000 0000 T=1015 0000 0000 T=1015 0000 0000 T=1015 0000 0000 T=1015 0000 0000 T=1015 0000 0000 T=1015 0000 0000 T=1015 0000 0000 T=1015 0000 0000 T=1015 0000 0000 T=1015 0000 0000 T=1015 0000 0000 T=1015 0000 0000 T=1015 0000 0000 T=1015 0000 0000 T=1015 0000 0000 T=1015 0000 0000 T=1015 0000 0000 T=1015 0000 0000 T=1015 0000 0000 T=1015 0000 0000 T=1015 0000 0000 T=1015 0000 0000 T=1015 0000 0000 T=1015 0000 0000 T=1015 0000 0000 T=1015 0000 0000 T=1015 0000 0000 M=013F S=0130 E

N=BSRAM-A A=0000 B=282A 282A 282A 282A 282A 282A 282A 282A 282A 282A B=282A 282A 282A 282A 282A 282A 282A 282A 282A 282A B=282A 282A 282A 282A 282A 282A 282A 282A 282A 282A 282A C=0000

! A B C T=0000 282A 0000 T=0000 282A 0000 T=0000 282A 0000 T=0000 282A 0000 T=0000 282A 0000 T=0000 282A 0000 T=0000 282A 0000 T=0000 282A 0000 T=0000 282A 0000 T=0000 282A 0000 T=0000 282A 0000 T=0000 282A 0000 T=0000 282A 0000 T=0000 282A 0000 T=0000 282A 0000 T=0000 282A 0000 T=0000 282A 0000 T=0000 282A 0000 T=0000 282A 0000 T=0000 282A 0000 T=0000 282A 0000 T=0000 282A 0000 T=0000 282A 0000 T=0000 282A 0000 T=0000 282A 0000 T=0000 282A 0000 T=0000 282A 0000 T=0000 282A 0000 T=0000 282A 0000 T=0000 282A 0000 T=0000 282A 0000 M=013F S=0130 E

N=BSRAM-5 A=0000 B=1015 1015 1015 1015 1015 1015 1015 1015 1015 1015 B=1015 1015 1015 1015 1015 1015 1015 1015 1015 1015 B=1015 1015 1015 1015 1015 1015 1015 1015 1015 1015 1015 C=0000

! A B C T=0000 1015 0000 T=0000 1015 0000 T=0000 1015 0000 T=0000 1015 0000 T=0000 1015 0000 T=0000 1015 0000 T=0000 1015 0000 T=0000 1015 0000 T=0000 1015 0000 T=0000 1015 0000 T=0000 1015 0000 T=0000 1015 0000 T=0000 1015 0000 T=0000 1015 0000 T=0000 1015 0000 T=0000 1015 0000 T=0000 1015 0000 T=0000 1015 0000 T=0000 1015 0000 T=0000 1015 0000 T=0000 1015 0000 T=0000 1015 0000 T=0000 1015 0000 T=0000 1015 0000 T=0000 1015 0000 T=0000 1015 0000 T=0000 1015 0000 T=0000 1015 0000 T=0000 1015 0000 T=0000 1015 0000 T=0000 1015 0000 M=013F S=0130 E

N=BINPOVFL A=0000 B=0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 B=0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 B=0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000

M=013F S=0133 E

N=CSRAM-A A=0000 B=0000 C=282A 282A 282A 282A 282A 282A 282A 282A 282A 282A C=282A 282A 282A 282A 282A 282A 282A 282A 282A 282A C=282A 282A 282A 282A 282A 282A 282A 282A 282A 282A 282A

! A B C T=0000 0000 282A T=0000 0000 282A T=0000 0000 282A T=0000 0000 282A T=0000 0000 282A T=0000 0000 282A T=0000 0000 282A T=0000 0000 282A T=0000 0000 282A T=0000 0000 282A T=0000 0000 282A T=0000 0000 282A T=0000 0000 282A T=0000 0000 282A T=0000 0000 282A T=0000 0000 282A T=0000 0000 282A T=0000 0000 282A T=0000 0000 282A T=0000 0000 282A T=0000 0000 282A T=0000 0000 282A T=0000 0000 282A T=0000 0000 282A T=0000 0000 282A T=0000 0000 282A T=0000 0000 282A T=0000 0000 282A T=0000 0000 282A T=0000 0000 282A T=0000 0000 282A M=013F S=0130 E

N=CSRAM-5 A=0000 B=0000 C=1015 1015 1015 1015 1015 1015 1015 1015 1015 1015 C=1015 1015 1015 1015 1015 1015 1015 1015 1015 1015 C=1015 1015 1015 1015 1015 1015 1015 1015 1015 1015 1015

! A B C T=0000 0000 1015 T=0000 0000 1015 T=0000 0000 1015 T=0000 0000 1015 T=0000 0000 1015 T=0000 0000 1015 T=0000 0000 1015 T=0000 0000 1015 T=0000 0000 1015 T=0000 0000 1015 T=0000 0000 1015 T=0000 0000 1015 T=0000 0000 1015 T=0000 0000 1015 T=0000 0000 1015 T=0000 0000 1015 T=0000 0000 1015 T=0000 0000 1015 T=0000 0000 1015 T=0000 0000 1015 T=0000 0000 1015 T=0000 0000 1015 T=0000 0000 1015 T=0000 0000 1015 T=0000 0000 1015 T=0000 0000 1015 T=0000 0000 1015 T=0000 0000 1015 T=0000 0000 1015 T=0000 0000 1015 T=0000 0000 1015 M=013F S=0130 E

N=CINPOVFL B=0000 C=0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 C=0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 C=0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000

M=013F S=0133 E ! ! End of test data

! FILENAME: MACINBIT.ASC ! DESCRIPTION: MAC INPUT BIT LAYER TEST ! DATE: 3/16/92 ! ! FORMAT: N=MACBITxx ! A=n1 n2 n3 n(m) ! B=n1 n2 n3 n(p) ! C=n1 n2 n3 n(q) ! ! !A B C ! T=A B C ! : ! : ! : ! N=MACBIT00 A=0001 B=0001 C=0001

! A B C T=0001 0001 0001 M=01FF S=013C E

N=MACBIT01 A=0002 B=0002 C=0002

!A B C T=0002 0002 0002 M=01FF S=013C E

N=MACBIT02 A=0004 B=0004 C=0004

!A B C T=0004 0004 0004 M=01FF S=013C E

N=MACBIT03 A=0008 B=0008 C=0008

!A B C T=0008 0008 0008 M=01FF S=013C E

N=MACBIT04 A=0010 B=0010 C=0010

!A B C T=0010 0010 0010 M=01FF S=013C E

N=MACBIT05 A=0020 B=0020 C=0020

!A B C T=0020 0020 0020 M=01FF S=013C E

N=MACBIT06 A=0040 B=0040 C=0040

!A B C T=0040 0040 0040 M=01FF S=013C ! MAPS TO 0000 0000 0000 FOR BRDVER01.ASC E

N=MACBIT07 A=0080 B=0080 C=0080

!A B C T=0080 0080 0080 M=01FF S=013C ! MAPS TO 0000 0000 0000 FOR BRDVER01.ASC E

N=MACBIT08 A=0100 B=0100 C=0100

!A B C T=0100 0100 0100 M=01FF S=013C ! MAPS TO 0000 0000 0000 FOR BRDVER01.ASC E

N=MACBIT09 A=0200 B=0200 C=0200

!A B C T=0200 0200 0200 M=01FF S=013C ! MAPS TO 0000 0000 0000 FOR BRDVER01.ASC E

N=MACBIT10 A=0400 B=0400 C=0400

!A B C T=0400 0400 0400 M=01FF S=013C ! MAPS TO 0000 0000 0000 FOR BRDVER01.ASC E

N=MACBIT11 A=0800 B=0800 C=0800

!A B C T=0800 0800 0800 M=01FF S=013C E

N=MACBIT12 A=1000 B=1000 C=1000

!A B C T=1000 1000 1000 M=01FF S=013C E

N=MACBIT13 A=2000 B=2000 C=2000

!A B C T=2000 2000 2000 M=01FF S=013C E

N=MACBITAA A=2AAA B=2AAA C=2AAA

!A B C T=2AAA 2AAA 2AAA M=01FF S=013C ! MAPS TO 282A 282A 282A FOR BRDVER01.ASC E

N=MACBIT55 A=1555 B=1555 C=1555

!A B C T=1555 1555 1555 M=01FF S=013C ! MAPS TO 1015 1015 1015 FOR BRDVER01.ASC E ! ! End of test data

! FILENAME: OUTFIFO.ASC ! DESCRIPTION: OUTPUT FIFO ! DATE: 3/23/92 ! ! FORMAT: N=OUTFIFO ! A=n1 n2 n(m) ! B=n1 n2 n(n) ! C=n1 n2 n(p) ! ! ! A B C ! T=A B C ! : : : ! : : : ! : : : ! E

N=OUTFIFO A=0021 0022 0023 0024 0025 0026 0027 0028 A=0029 002A 002B 002C 002D 002E 002F 0031 B=0001 0002 0003 0004 0001 0002 0003 0004 B=0001 0002 0003 0004 0001 0002 0003 0004 C=0001 0002 0003 0004 0001 0002 0003 0004

! A B C T=0021 0001 0001 T=0022 0001 0002 T=0023 0001 0003 T=0024 0001 0004 T=0025 0002 0001 T=0026 0002 0002 T=0027 0002 0003 T=0028 0002 0004 T=0029 0003 0001 T=002A 0003 0002 T=002B 0003 0003 T=002C 0003 0004 T=002D 0004 0001 T=002E 0004 0002 T=002F 0004 0003 T=0031 0004 0004 T=0021 0001 0001 T=0022 0001 0002 T=0023 0001 0003 T=0024 0001 0004 T=0025 0002 0001 T=0026 0002 0002 T=0027 0002 0003 T=0028 0002 0004 T=0029 0003 0001 T=002A 0003 0002 T=002B 0003 0003 T=002C 0003 0004 T=002D 0004 0001 T=002E 0004 0002 T=002F 0004 0003 T=0031 0004 0004 T=0021 0001 0001 T=0022 0001 0002 T=0023 0001 0003 T=0024 0001 0004 T=0025 0002 0001 T=0026 0002 0002 T=0027 0002 0003 T=0028 0002 0004 T=0029 0003 0001 T=002A 0003 0002 T=002B 0003 0003 T=002C 0003 0004 T=002D 0004 0001 T=002E 0004 0002 T=002F 0004 0003 T=0031 0004 0004 T=0021 0001 0001 T=0022 0001 0002 T=0023 0001 0003 T=0024 0001 0004 T=0025 0002 0001 T=0026 0002 0002 T=0027 0002 0003 T=0028 0002 0004 T=0029 0003 0001 T=002A 0003 0002 T=002B 0003 0003 T=002C 0003 0004 T=002D 0004 0001 T=002E 0004 0002 T=002F 0004 0003 T=0031 0004 0004 T=0021 0001 0001 T=0022 0001 0002 T=0023 0001 0003 T=0024 0001 0004 T=0025 0002 0001 T=0026 0002 0002 T=0027 0002 0003 T=0028 0002 0004 T=0029 0003 0001 T=002A 0003 0002 T=002B 0003 0003 T=002C 0003 0004 T=002D 0004 0001 T=002E 0004 0002 T=002F 0004 0003 T=0031 0004 0004 T=0021 0001 0001 T=0022 0001 0002 T=0023 0001 0003 T=0024 0001 0004 T=0025 0002 0001 T=0026 0002 0002 T=0027 0002 0003 T=0028 0002 0004 T=0029 0003 0001 T=002A 0003 0002 T=002B 0003 0003 T=002C 0003 0004 T=002D 0004 0001 T=002E 0004 0002 T=002F 0004 0003 T=0031 0004 0004 T=0021 0001 0001 T=0022 0001 0002 T=0023 0001 0003 T=0024 0001 0004 T=0025 0002 0001 T=0026 0002 0002 T=0027 0002 0003 T=0028 0002 0004 T=0029 0003 0001 T=002A 0003 0002 T=002B 0003 0003 T=002C 0003 0004 T=002D 0004 0001 T=002E 0004 0002 T=002F 0004 0003 T=0031 0004 0004 T=0021 0001 0001 T=0022 0001 0002 T=0023 0001 0003 T=0024 0001 0004 T=0025 0002 0001 T=0026 0002 0002 T=0027 0002 0003 T=0028 0002 0004 T=0029 0003 0001 T=002A 0003 0002 T=002B 0003 0003 T=002C 0003 0004 T=002D 0004 0001 T=002E 0004 0002 T=002F 0004 0003 T=0031 0004 0004 M=013F S=0124 E

! FILENAME: PFOUT.ASC ! DESCRIPTION: PF OUTPUT ! DATE: 3/30/92 ! ! FORMAT: N=PFOUT ! A=n1 n2 n(m) ! B=n1 n2 n(n) ! C=n1 n2 n(p) ! ! ! A B C ! T=A B C ! : : : ! : : : ! : : : ! E

N=PFOUT A=0001 0002 0004 0008 0010 0020 0040 !A=0100 0200 0400 0800 1000 2000 282A 1015 B=0001 0002 0004 0008 0010 0020 0040 !B=0100 0200 0400 0800 1000 2000 282A 1015 C=0001 0002 0004 0008 0010 0020 0040 !C=0100 0200 0400 0800 1000 2000 282A 1015

! A B C T=0001 0001 0001 T=0002 0002 0002 T=0004 0004 0004 T=0008 0008 0008 T=0010 0010 0010 T=0020 0020 0020 T=0040 0040 0040 !T=0080 0080 0080 !T=0100 0100 0100 !T=0200 0200 0200 !T=0400 0400 0400 !T=0800 0800 0800 !T=1000 1000 1000 !T=2000 2000 2000 !T=282A 282A 282A !T=1015 1015 1015

M=013F S=0024 E ! ! End of test data

! FILENAME: SYNCPROC.ASC ! DESCRIPTION: SAM1 SYNCRONOUS PROCESSING ! DATE: 3/23/92 ! ! FORMAT: N=SYNCPROC ! A=n1 n2 n(m) ! B=n1 n2 n(n) ! C=n1 n2 n(p) ! ! ! A B C ! T=A B C ! : : : ! : : : ! : : : ! E N=SYNCPROC A=0001 383F 383F 383F 383F 383F 383F 383F 383F 383F A=383F 383F 383F 383F 383F 383F 383F 383F 383F 383F A=383F 383F 383F 383F 383F 383F 383F 383F 383F 383F 001F B=0001 383F 383F 383F 383F 383F 383F 383F 383F 383F B=383F 383F 383F 383F 383F 383F 383F 383F 383F 383F B=383F 383F 383F 383F 383F 383F 383F 383F 383F 383F 001F C=0001 383F 383F 383F 383F 383F 383F 383F 383F 383F C=383F 383F 383F 383F 383F 383F 383F 383F 383F 383F C=383F 383F 383F 383F 383F 383F 383F 383F 383F 383F 001F

! A B C T=0001 0001 0001 T=001F 001F 001F M=013F S=0120 E ! ! End of test data

! FILENAME: VMEINBIT.ASC ! DESCRIPTION: VME INPUT BIT LAYER TEST ! DATE: 3/16/92 ! ! FORMAT: N=VMEBITxx ! A=n1 n2 n3 n(m) ! B=n1 n2 n3 n(p) ! C=n1 n2 n3 n(q) ! ! !A B C ! T=A B C ! : ! : ! : ! N=VMEBIT00 A=0001 B=0001 C=0001

! A B C T=0001 0001 0001 M=01FF S=013C E

N=VMEBIT01 A=0002 B=0002 C=0002

!A B C T=0002 0002 0002 M=01FF S=013C E

N=VMEBIT02 A=0004 B=0004 C=0004

!A B C T=0004 0004 0004 M=01FF S=013C E

N=VMEBIT03 A=0008 B=0008 C=0008

!A B C T=0008 0008 0008 M=01FF S=013C E

N=VMEBIT04 A=0010 B=0010 C=0010

!A B C T=0010 0010 0010 M=01FF S=013C E

N=VMEBIT05 A=0020 B=0020 C=0020

!A B C T=0020 0020 0020 M=01FF S=013C E

N=VMEBIT06 A=0040 B=0040 C=0040

!A B C T=0040 0040 0040 M=01FF S=013C ! MAPS TO 0000 0000 0000 FOR BRDVER01.ASC E

N=VMEBIT07 A=0080 B=0080 C=0080

!A B C T=0080 0080 0080 M=01FF S=013C ! MAPS TO 0000 0000 0000 FOR BRDVER01.ASC E

N=VMEBIT08 A=0100 B=0100 C=0100

!A B C T=0100 0100 0100 M=01FF S=013C ! MAPS TO 0000 0000 0000 FOR BRDVER01.ASC E

N=VMEBIT09 A=0200 B=0200 C=0200

!A B C T=0200 0200 0200 M=01FF S=013C ! MAPS TO 0000 0000 0000 FOR BRDVER01.ASC E

N=VMEBIT10 A=0400 B=0400 C=0400

!A B C T=0400 0400 0400 M=01FF S=013C ! MAPS TO 0000 0000 0000 FOR BRDVER01.ASC E

N=VMEBIT11 A=0800 B=0800 C=0800

!A B C T=0800 0800 0800 M=01FF S=013C E

N=VMEBIT12 A=1000 B=1000 C=1000

!A B C T=1000 1000 1000 M=01FF S=013C E

N=VMEBIT13 A=2000 B=2000 C=2000

!A B C T=2000 2000 2000 M=01FF S=013C E

N=VMEBITAA A=2AAA B=2AAA C=2AAA

!A B C T=2AAA 2AAA 2AAA M=01FF S=013C ! MAPS TO 282A 282A 282A FOR BRDVER01.ASC E

N=VMEBIT55 A=1555 B=1555 C=1555

!A B C T=1555 1555 1555 M=01FF S=013C ! MAPS TO 1015 1015 1015 FOR BRDVER01.ASC E ! ! End of test data

! FILENAME: BRDVER01.ASC ! DESCRIPTION: OTC TEST BOARD VERSION CROSSPOINT MAPPING ! FROM LAYER INPUTS AND VME TO M1,M2,AND ! KINEMATIC MEMORIES ! ! Edit history: 23-Oct-91 ! ======================================================================== ! 21-Nov-91 DMK Modified format for 12 character field widths. ! ======================================================================== ! ! NOTE: M1 MAPPING ASSUMES M1 JUMPER SELECT (M1JSXX) INDICATED ! BOARD CROSSPOINT VERSIONS: XPTA1_02 XPTB1_02 XPTC1_02 XPTA2_02 XPTB2_02 XPTC2_02 XPTK_02 MIJS_01

! M1 CONFIGURATION M1: ! LAYER VME 0 C3 VMEA2 1 C4 VMEA3 2 C5 VMEA4 3 C11 VMEA5 4 B3 VMEA6 5 B4 VMEA7 6 B5 VMEA8 7 B11 VMEA9 8 A3 VMEA10 9 A4 VMEA11 10 A5 VMEA12 11 A11 VMEA13 12 C12 VMEA14 13 C13 VMEA15 14 B12 VMEA16 15 B13 VMEA17 16 A12 VMEA18 17 A13 VMEA19

!M2 CONFIGURATION M2: ! LAYER VME 0 C0 VMEA2 1 C1 VMEA3 2 C2 VMEA4 3 C3 VMEA5 4 C4 VMEA6 5 C5 VMEA7 6 B0 VMEA8 7 B1 VMEA9 8 B2 VMEA10 9 B3 VMEA11 10 B4 VMEA12 11 B5 VMEA13 12 A0 VMEA14 13 A1 VMEA15 14 A2 VMEA16 15 A3 VMEA17 16 A4 VMEA18 17 A5 VMEA19

!K CONFIGURATION K2: ! VME 1STWORD 1STWORD 2NDWORD 2NDWORD !OUTPUTS K R/W KIN(M=0) PF(M=0) KIN(M=1) PF(M=1) 0 CKIN0 * * CKIN1 CKIN0 1 CKIN1 * * CKIN2 CKIN1 2 CKIN2 * * CKIN3 CKIN2 3 CKIN3 * * CKIN4 CKIN3 4 CKIN4 * * CKIN5 CKIN4 5 CKIN5 * * CKIN11 CKIN5 6 CKIN6 * * CKIN12 CKIN6 7 CKIN7 * * BKIN1 BKIN0 8 CKIN8 * * BKIN2 BKIN1 9 CKIN9 * * BKIN3 BKIN2 10 CKIN10 * * BKIN4 BKIN3 11 CKIN11 BKIN11 BKIN11 BKIN5 BKIN4 12 CKIN12 BKIN12 BKIN12 BKIN11 BKIN5 13 CKIN13 BKIN13 BKIN13 BKIN12 BKIN11

K3: ! VME 1STWORD 1STWORD 2NDWORD 2NDWORD !OUTPUTS K R/W KIN(M=0) PF(M=0) KIN(M=1) PF(M=1) 0 CKIN0 * * * * 1 CKIN1 * * * * 2 CKIN2 * * * * 3 CKIN3 * * * * 4 CKIN4 * * * * 5 CKIN5 * * * * 6 CKIN6 * * * * 7 CKIN7 * * * * 8 CKIN8 * * * * 9 CKIN9 * * * * 10 CKIN10 * * * * 11 CKIN11 CKIN11 CKIN11 * * 12 CKIN12 CKIN12 CKIN12 * * 13 CKIN13 CKIN13 CKIN13 * *

! M1 JUMPER SELECT M1JS_01: !OUTPUTS INPUTS M1A12 CnX0 M1A13 CnX1 M1A14 BnX0 M1A15 BnX1 M1A16 AX0 M1A17 AX1

! FILENAME: TRIGDATA.AS ! DATE: 3/23/92 ! DESCRIPTION: OTC TEST TRIGGER DATA

!A B C 0001 0001 0001 0002 0002 0002 0004 0004 0004 0008 0008 0008 0010 0010 0010 0020 0020 0020 0040 0040 0040 0080 0080 0080 0100 0100 0100 0200 0200 0200 0400 0400 0400 0800 0800 0800 1000 1000 1000 2000 2000 2000 1015 1015 1015 282A 282A 282A 0021 0001 0001 0022 0001 0002 0023 0001 0003 0024 0001 0004 0025 0002 0001 0026 0002 0002 0027 0002 0003 0028 0002 0004 0029 0003 0001 002A 0003 0002 002B 0003 0003 002C 0003 0004 002D 0004 0001 002E 0004 0002 002F 0004 0003 0031 0004 0004 0011 0001 0001 0011 0001 0002 0011 0001 0003 0011 0001 0004 0011 0002 0001 0011 0002 0002 0011 0002 0003 0011 0002 0004 0011 0003 0001 0011 0003 0002 0011 0003 0003 0011 0003 0004 0011 0004 0001 0011 0004 0002 0011 0004 0003 0011 0004 0004 282A 0000 0000 0000 282A 0000 0000 0000 282A 1015 0000 0000 0000 1015 0000 0000 0000 1015 001F 001F 001F ! ! End of triggers

Keywords: D0, OTC, OTCTM

Distribution:

Paul Czarapata MS-220

Tom Fitzpatrick MS-222

Carmen Rotolo MS-222

Bob Trendler MS-208

Therese Watts MS-220

Security, Privacy, Legal

rwest@fsus04.fnal.gov