RD Controls Special Project Note 11.5
Precision Automatic Flux Measurement System (PAFMS)
Coil Configuration Module (CCM)
November 2, 1993
Table of Contents
1. General Description 2
2. Technical Characteristics 3
3. Module Description 3
3.1 Module Structure 3
3.2 Coil Configuration Module Interconnections 5
3.3 Relay Specification 11
3.4 Programmable Bucking Source 12
3.5 VXI Interface 18
3.5.1 Register Description 18
3.5.2 ID Register (READ ONLY) 19
3.5.3 Manufacturer ID: 19
3.5.4 Logical Address Register (WRITE ONLY) 20
3.5.5 Device Type Register (READ ONLY) 20
3.5.6 Status Register (READ ONLY) 20
3.5.7 Control Register (WRITE ONLY) 21
3.5.8 Offset Register (READ/WRITE) 21
3.5.9 ID/Device Type Register Configuration 22
3.5.10 A16 Device Dependent Register Implementation 23
3.5.11 VXI Connections 25
3.6 CCM Power supply 27
4. Front Panel 31
5. Combining CCMs 33
6. Application Note 34
7. Appendix A...Register-Based Programming 40
1. General Description
The Coil Configuration Module (CCM) takes inputs from up to 10 probe coils and combines them into two output signals. It is a standard VXI ' C ' size single wide module. The CCM can be controlled by either an embedded P.C., or by a host computer through a Slot-0 VXI controller via a GPIB interface, .
The CCM is a part of the Precision Automatic Flux Measurement System (PAFMS) shown in Figure 1a.
Fig. 1a. Precision Automatic Flux Measurement System
The Coil Configuration Module consists of 10 coil configuration channels, (CCC) which have the capability of performing the following tasks:
l they can change the polarity of an incoming signal;
l they can configure coils which produce incoming signals either as source coils or as bucking coils;
2. Technical Characteristics
* Number of input coils: up to 10
* Number of output signals: 2
* Coil Configuration Channel types: 3
* Summing Resistor Values: 4 selectable
* Bucking Voltage: 0 - 300 mv programmable, 12-Bit resolution
* Power Supply: VXI 5 Volts @ 1.5 amps,
* 24 Volts @ 250 ma
* Interface: VXI Register Based
* Relay types: Clare SPDT precision,
American Zettler DPDT
* Input\Output signals: via Front Panel LEMO connectors,
Coil input signals: via AMP connector
3. Module Description
3.1 Module Structure
The structure of the CCM module is shown in Figure 3.1a. It consists of the following components:
* VXI Interface: Register Based I/O; processes instructions from the embedded processor, decodes Module ID., Module Number, and Device Type.
* PLC Controller: Built on the Altera 7128 PLC chip; processes instructions from the VXI interface and sends control signals via local bus to the appropriate CCC.
* Coil Configuration Channels: Each CCC consists of relays, and depending on the CCC type, either contains a Programmable Bucking Source or does not use one.
Fig. 3.1a. CCM Structure
The PLC Controller allows the host computer to all PLC; registers used to control relays inside the Coil Configuration Channel. It also allows logic to perform "warm" resets on the module. The block diagram for the PLC controller in shown in Figure 3.1b. It includes:
* address registers;
* load and read decoders;
* write / read logic;
* handshake logic;
* reset logic.
The PLC Controller's registers are set up as A24 Device Dependent Registers whose base address space is determined by the value placed on the LA(7 : 0) pins, or is programmed by the system Resource Manager if FFh is placed on the LA(7 : 0) pins. To operate a particular I/O register, its address must be written into the lower 16 bits of the Control and Address Channel of the VXI Interface. Buffered VXI data is provided on VXI data bus (BVD15 - BVD0) providing a data path between the VXI data bus and the A24 Device Dependent registers. The PLC decodes addressing from the I/O registers and enables the appropriate CCC relay drivers. Addressing of the two Dual Bucking current sources is also accomplished via the PLCs.
Fig 3.1b PLC Controller
3.2 Coil Configuration Module Interconnections
All CCCs are chained as shown in Figure 3.2a and connected to three output groups OC1, OC2 and Buck. Some output terminals are duplicated but have different names. It is done to ease combining several CCMs in one coil configuration unit. To transform current induced into the source coil to voltage as required by the Front End preamplifier, a summing resistor with a value derived by the summing relays is placed in series with the source signal. This also allows the user to place another coil in parallel with the summing resistor to buck the source signal. This combination, and others will be explained at a later time.
Each of the outputs OC1 and OC2 has two summing resistors associated with its outputs. These summing resistors are arranged so that four combinations of summing resistor values can be derived (Figure 3.2a). These derivations are provided by summing relays controlled by control signals SumH1, SumH2, for the summing resistor connected to the OC1 output group; and SumF1, SumF2 for the summing resistor connected to the OC2 output group. Table 3.2a shows the different values that can be derived by using the control signals SumH1 and SumH2.
Fig. 3.2a. CCC Interconnections
SR1 OFF OFF
SR2 ON OFF
SR1+SR2 OFF ON
BYPASS ON ON
The 10 CCCs are divided into three groups : 1) PDBS (channels 1 through 4) with Polarity, Disconnect Bucking and Selection capabilities, 2) PDS (channels 5 through 8) with Polarity, Disconnect and Selection capabilities, 3) DS (channels 9 and 10) with Disconnect and Selection capabilities only.
A CCC from the PDBS group is shown in Figure 3.2d. All relays shown in this or other examples are in a non-energized state unless stated otherwise. It has the capability of performing all coil configuration functions. These functions include Polarity, Disconnect, Bucking, and Selection. The Polarity function allows the user to control the input signal polarity. The Disconnect function is used when the user does not want to use a particular coil signal in the his/her configuration of the module. When the Disconnect function is selected, resistor R1 is placed across the coil and becomes a shunt for the coil current (Figure 3.2b). This helps reduce parasitic signals introduced into the load. At the same time both OC1 and OC2 outputs are shorted to provide bypass routes for output signals.
Figure 3.2b Shunting disconnected coil
When the coil is configured as a bucking coil, it is connected to the input of a Programmable Bucking Source. The output from the latter is then connected in parallel with the summing resistor (Figure 3.2c). This allows the user to vary the amount of current used to buck the current flowing through the summing resistor from the source coils. More than one bucking coil can be placed in parallel with a summing resistor. When bucking is not selected, resistor R2 is placed across the output of the Programmable Bucking Source. This prevents the programmable bucking source from switching between the unloaded state and the fully loaded state.
Fig. 3.2c. Source and Bucking coil configuration
Through the use of the Selection function the user can direct configured coil signals to either of two outputs, OC1, or OC2.
The table in Figure 3.2d explains the different coil configurations derived by varying combinations of control signals.
Fig. 3.2d PDBS Coil Configuration Channel.
The second CCC group, PDS, is shown in Figure 3.2e and performs three functions: Polarity, Disconnect, and Selection. The functions are controlled in the same way as they were in the previously described CCC PDBS group.
Fig. 3.2e. PDS Coil Configuration Channel.
The third CCC group, DS is shown in Figure 3.2f. and performs only two functions: Disconnect and Selection. The functions are controlled in the same manner that was previously described in PDBS section.
Fig. 3.2f. DS Coil Configuration Channel
CCCs are daisy chained by connecting the OC1_OUT, OC2_OUT signals of each preceding channel to the corresponding OC1_IN, OC2_IN signal of the successive channel. The OC1_IN, OC2_IN signals of the first channel constitute one leg of CCM OC1 and OC2 outputs. The OC1_OUT, OC2_OUT signals of the last channel is the other leg of the CCM OC1 and OC2 outputs. The Buck_In and Buck_Out signals of each preceding channel are placed in parallel with corresponding Buck_In and Buck_Out signals of the successive channels (Fig. 3.2a).
Because more than one CCM can be used in the system, each of the three outputs (OC1, OC2, and Bucking) have multiple connections to the front panel of the module, assuring easy module interconnection (Fig. 3.2a).
3.3 Relay Specification
The configuration relays are Clare HGWM52112n00 mercury-wetted relays. Specification for this relay is as follows:
* form - bistable;
* transfer open time - 25 microseconds;
* life expectancy - 2 x operations;
* contact circuit resistance - 12 to 25 milliohms stable within 2.0 milliohms over life;
* capacitance - across open contacts of 5 pf;
* physical - upright within of vertical position before operating;
* timing - operating: 1.25 ms, max., at normal coil voltage
release: 1.25 ms, max., at normal voltage
Pin layout is shown in Fig 3.3a
Fig 3.3a Clare Relay pin layout.
The bucking relays used in the PDBS group are American Zettler DPDT relay. Specification for this relay is as follows:
* form - bistable;
* transfer open time - 3 microseconds;
* transfer open to close time - 3.5 microseconds;
* life expectancy - 100 million operations;
* contact circuit resistance - 50 milliohms stable within 2.0 milliohms over life;
* capacitance - across open contacts of 1 pf;
Pin layout is shown in Fig 3.3b
Fig 3.3b. American Zettler pin layout
The Clare and American Zettler relays are latching relays and are activated and deactivated using two coils. Activation from open to closed relay state is accomplished by placing a pulse on one of the relays coils. To go back from closed to open relay state a pulse must be applied to the other coil.
3.4 Programmable Bucking Source
The Programmable Bucking Source employs an Analog Device AD7537 dual 12-bit current output DAC and two AD797 Ultra low Distortion Ultra low Noise Op-amps. Each DAC consists of a highly stable R-2R ladder and 12 N-channel steering switches. Figure 3.4a shows a simplified D/A circuit for the DAC. The R-2R ladder, binary weighted currents are steered between Iout and AGND. The current flowing in each ladder is constant, irrespective of switch state. The AD797 amplifiers are used as a current boosters to provide the necessary current across the bucking resistor.
Fig 3.4a . Programmable Bucking Source
Specifications for AD7537;
* Accuracy: 12-bit
* Relative Accuracy: *1/2 LSB max.
* Gain Error: *3% LSB max.
* Gain Temp. Coefficient: *5 ppm/*C max.
* Output leakage current: 10 na max. with register loaded
150 na max. with registers at 0s
* Output Noise Voltage Density 25 nV/ typ
* Absolute Max:
Vdd to DGND -0.3V, +17V
VrefA, VrefB AGND *25V
Dig. input Volts to DGND -0.3V, Vdd +0.3V
IoutA, IoutB to DGND -0.3V, Vdd +0.3V
AGND to DGND -0.3V, Vdd +0.3V
Specifications for AD797;
0.9 nV/ typ(1.2 nV/ max.)input Voltage
50nV p-p Input Voltage Noise 0.1 Hz to 10 Hz
-110 dB Total Harmonic Distortion (@ 20 KHZ)
* AC Characteristics:
110 MHz Gain Bandwidth (G = 1000)
6 MHz Bandwidth (G + 10)
280 KHZ Full Power Bandwidth
10 V/micro second Slew Rate
* Output Current Drive 30 ma min.
A PSpice analysis of the Bucking current source Figure 3.4b has been done on the following circuit representation of the DAC AD7537. The analysis was to check the functionality of the device.
Fig. 3.4b Programmable Bucking Source
Figure 3.4c depicts the voltage across the summing resistor when digital inputs are changed from 000h to FFFh. The spikes visible in the picture are not real. They are caused by a lack of resolution of the PSpice software and the CRT displaying the Waveform. Figure 3.4d is showing a smaller part of the same signal 50ms. of simulation.
Fig. 3.4c Voltage across Summing resistor
Fig 3.4 d Voltage across Summing resistor, Enhanced resolution.
Figure 3.4e shows the voltage across the summing resistor caused by the leakage current when the DAC addressing is set to 000h.
Fig. 3.4e. Voltage caused by the leakage current with DAC set to 000h.
Fig. 3.4f. The blown up picture for the voltage caused by the leakage current with DAC set to 000h.
Fig. 3.4g Input for DAC set to 7FFh.
Fig 3.4h The blown up picture of the output voltage for DAC set to 7FFh.
Fig 3.4i output voltage with DAC set to FFFh.
3.5 VXI Interface
The CCM employs a DT-9110 VXI adapter card from Interface Technology. This card provides a complete VXI bus interface capable of performing all register based data transfers. It has a 4 row by 43 pin connector. (See Table below for pinout information.)
Pin # Row A Row B Row D Row E Pin# Row A Row B Row D Row E
1 ---- ---- VD0 VD8 23 BVD4 BVD5 AM4 A15
2 ---- ---- VD1 VD9 24 BVD6 BVD7 A7 A14
3 ---- ---- VD2 VD10 25 BVD8 BVD9 A6 A13
4 ---- ---- VD3 VD11 26 BVD10 BVD11 A5 A12
5 ---- ---- VD4 VD12 27 BVD12 BVD13 A4 A11
6 ---- ---- VD5 VD13 28 BVD14 BVD15 A3 A10
7 ---- ---- VD6 VD14 29 INTRPT* ---- A2 A9
8 ---- ---- VD7 VD15 30 ---- ---- A1 A8
9 ---- INTL3 ---- ---- 31 ---- ---- IRQ1* IRQ2*
10 ---- INTL2 CLK SYSFAIL* 32 ---- ---- IRQ3* IRQ4*
11 ---- INTL1 AM0 ---- 33 ---- ---- IRQ5* IRQ6*
12 ---- ---- DS1* SYSRST* 34 ---- ---- IRQ7* ----
13 ---- MRST DS0* ---- 35 ---- ---- ---- ----
14 ---- ---- WRT* AM5 36 ---- RST REGRD* MODID
15 ---- ---- AM1 A23 37 ---- UASEL* A24 A25
16 ---- ---- DTACK* A22 38 ---- REGWR* A26 A27
17 ---- ---- AM2 A21 39 DDSEL* ---- A28 A29
18 ---- ---- AS* A20 40 LA0 LA1 A30 A31
19 ---- ---- AM3 A19 41 LA2 LA3 VCC VCC
20 ---- ---- IACK* A18 42 LA4 LA5 GND GND
21 BVD0 BVD1 IACKIN* A17 43 LA6 LA7 GND GND
22 BVD2 BVD3 IACKOUT* A16 ---- ---- ---- ---- ----
3.5.1 Register Description
The DT9110 incorporates all of the configuration registers required by the VXIbus specification, and decodes the address lines to provide a select signal (DDSEL*) for all A16 Device Dependent registers. All registers conform to the definitions and rules given in the VXIbus specification. The VXIbus register map is shown below.
DT9110 VXIbus DEVICE REGISTER MAP
Base Addr Register Name
3E DEVICE DEPENDENT
08 DEVICE DEPENDENT
02 DEVICE TYPE
00 ID/LOGICAL ADDRESS
The base address for the DT9110's device registers is determined by the device's unique logical address. The logical address is determined by the value placed on the LA(7:0) pins, or is programmed by the system's Resource Manager if a value of FFH is placed on the LA(7:0) pins. The logical address corresponds to bits 6 -13 of the device register base address. Bits 14 and 15 of the base address are both 1. VXIbus accesses to the DT9110's registers are automatically detected and controlled by the DT9110. In order to achieve the greatest flexibility, the DT9110 implements only the configuration registers. If A16 Device Dependent registers are needed, (address 08 thru 3E ) they must be implemented external to the DT9110.
3.5.2 ID Register (READ ONLY)
BIT# 15<-14 13<-12 11<-0
CONTENTS DEVICE CLASS ADDRESS SPACE MANUFACTURER ID
DEVICE CLASS: This field indicates the classification of the DT9110 according to the following table. The default value is 11
10 Message Based
11 Register Based
ADDRESS SPACE: This field indicates the addressing mode(s) of the DT9110's operational registers according to the following table. The default value is 00.
00 A16 / A24
01 A16 / A32
11 A16 Only
3.5.3 Manufacturer ID:
This number uniquely identifies the manufacturer of the device. The list of ID numbers is maintained by the VXIbus consortium. Each VXIbus device manufacturer has exactly one Manufacturer ID number. Numbers are assigned to manufacturers in decreasing order beginning with number 4095. See the VXIbus specifications for information on obtaining a manufacturer ID number. The default value is 0.
3.5.4 Logical Address Register (WRITE ONLY)
The Logical Address register is used to determine the DT9110's register base address. Each device in a system must have a unique Logical Address. The value of the DT9110's Logical Address is set by placing a value on the LA(7:0) pins. These pins contain internal pull-up resistors, allowing the use of a dip switch without the need for external resistors. If the value of FFhex is placed on the LA(7:0) pins, the DT9110 will become a dynamically configured (DC) device, meaning the value of its Logical Address register will be programmed automatically during initialization by the Resource Manager.
3.5.5 Device Type Register (READ ONLY)
The Device Type register is programmed by selectively cutting the jumper traces at locations RN1 and RN2 (See Fig. 4.9a, ID/DEVICE TYPE REGISTER CONFIGURATION). The Device Type register Fields are Defined by the VXIbus specification as follows.
BIT# 15 <- 12 11 <- 0
CONTENTS REQUIRED MEMORY MODEL CODE
REQUIRED MEMORY (Only required for A16/A24 and A16/A32 devices): These 4 bits contain a number m, which is between 0 and 15. The required memory usage is defined as
where a is the value address space field in the ID register. This equation gives the amount of A24 VMEbus memory space (in bytes) resident on the device. The DT9110 will automatically decode the address bits to the corresponding resolution. The default value of this field is 0x0008, which corresponds to 32768 bytes (32 Kbytes) if the DT9110 is configured as an A16/A24 device, or 8388608 bytes ( 8 Mbytes) if the DT9110 is configured as an A16/A32 device. If the DT9110 is configured as an A16 only device, these four bits are the upper bits of the model code.
NOTE: If the DT9110 is configured as an A16/A24 device, the minimum size of the A24 memory is 256 bytes. The maximum size is 1/2 of the complete A24 VMEbus address space. If the DT9110 is configured as an A16/A32 device, the minimum size of the A32 memory is 65536 bytes (64 Kbytes). The maximum size is 1/2 of the complete A32 VMEbus address space. It is a good idea to limit the memory space of any one device to 1/4 of the available address space.
MODEL CODE: This field contains a unique card identifier which is defined by the manufacturer. In the case of an A16 only device, this field occupies all 16 bits of the Device Type register. Model codes 0-255 (0-FFHEX) are reserved for Slot 0 devices. The default value for this field is 0. Therefore, if the Device Type register value is not modified by the user, the system's Resource Manager may give a warning during initialization indicating "redundant Slot 0 capability", or other similar warning. Programming a model code value greater than 255 will eliminate this warning.
3.5.6 Status Register (READ ONLY)
BIT# 15 14 13<-4 3 2 1 0
CONTENTS A24/A23ACTIVE MODID* NOTUSED READY PASSED SYSFAILINHIBIT RESET
A read of this register provides information about the DT9110's status according to the following bit definitions.
A24/A32 ACTIVE: This bit is only valid for A16/A24 and A16/A32 devices. A one (1) in this field indicates that the DT9110's A24 or A32 registers can be accessed. This bit reflects the state of the Control registers A24/A32 ENABLE bit.
MODID*: This bit reflects the inverted state of the MODID pin.
READY: This bit is used to indicate to the system controller that the DT9110 is ready to begin normal operation. This bit is cleared to 0 during reset conditions and automatically set to 1 when the device is ready for operation.
PASSED: The PASSED bit is normally used to indicate the success or failure of a device's self test. Because the DT9110 does not execute a self test, this bit is automatically set to 1 when the READY bit is set to 1.
SYSFAIL INHIBIT: This bit reflects the state of the SYSFAIL INHIBIT bit of the control register.
RESET: This bit reflects the state of the RESET bit of the control register.
3.5.7 Control Register (WRITE ONLY)
BIT# 15 14 13<-4 3 2 1 0
CONTENTS A24/A23ACTIVE MODID* NOTUSED READY PASSED SYSFAILINHIBIT RESET
A write to this register causes specific actions to be executed by the DT9110. These actions are described below.
A24/A32 ENABLE: A one (1) in the field enables access to the device's A24 or A32 VMEbus registers. A zero (0) disables such access.
SYSFAIL INHIBIT: A one (1) in this field disables the device from driving the SYSFAIL* line.
RESET: A one (1) in this field forces the device into a soft reset state.
3.5.8 Offset Register (READ/WRITE)
This register is used only for A16/A24 and A16/A32 devices. This 16-bit register defines the base address of the device's A24 or A32 VMEbus register. The m+1 most significant bits of the Offset register are the values of m+1 most significant bits of the device's A24 or A32 register addresses, where m is the value of the Required Memory field of the DT9110's Device Type Register. The 15-m least significant bits of the Offset register are meaningless. The DT9110 automatically maps the Offset register bits 15 -> 15-m to the address lines A23 -> A23-m for A24 registers, or to lines A31 ->A31-m for A32 registers. When a VXIbus access to the device's A24 or A32 registers is detected, the DT9110 asserts the UASEL* (upper address select) signal, which can be used as a device select. The Offset register is always reset to 0 by
a reset or power up condition.
3.5.9 ID/Device Type Register Configuration
The ID register and Device Type register can be custom configured by selectively cutting configuration traces provided for this purpose, or adding jumpers to override traces that have already been cut. The locations of the configuration traces are shown below.
Figure 4.9a ID/DEVICE TYPE REGISTER CONFIGURATION.
The default values for the ID register and Device Type register are as follows.
BIT# 15 <- 14 13 <- 12 11 <- 0
BINARY VALUE 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DEFINITION DEVICE CLASS (register base) ADD. SPACE = A16/A24 MANUF. ID = 0
Device Type Register
BIT# 15 <- 12 11 <- 0
BINARY VALUE 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DEFINITION REQUIRED MEMORY32768 bytes (A24 register)or 8388608 bytes (A32 registers) MODEL CODE = 0
To change a bit from a '0' to a '1', the configuration trace corresponding to the bit must be cut. To change a bit from a '1' to a '0' (which implies that the configuration trace has already been cut), a jumper wire must be installed between the two pin holes normally connected by the trace. To configure the registers with dip switches, simply cut all configuration traces and install a 8-position DIP switches in locations SW1, SW2, SW3, and SW4.
(See Figure 4.9a on previous page.)
3.5.10 A16 Device Dependent Register Implementation
The VXI Device Dependent registers, which are located at address 08-3F relative to the DT9110's VXIbus base address, are intended to be implemented external to the DT9110. The buffered VXI data bus pins (BVD15-BVD0) are provided as the data path between the VXI data bus and the A16 Device dependent registers. Enable and direction control for the "on board" VXI data buffers is provided automatically by the DT9110.
The DT9110 provides special signals to control access to the external register locations. These external register control signals consist of a device select signal, DDSEL*, and independent read/write control lines, REGRD*, REGWR*. The control signal DDSEL* is asserted whenever the VXIbus accesses an A16 Device Dependent register location. The VXIbus address lines from the back plane, A5-A1, can then be used to decode the individual registers. A block diagram showing the implementation of the A16 Device Dependent registers is shown in figure 4.10a.
3.5.11 VXI Connections
The CCM complies with all VXI specifications for bus and power pin usage. The CCM uses, two 96-pin card edge connectors defined by VXI as P1 and P2. Tables 4.11a and 4.11b list the assigned pins.
Pin ROWa ROWb ROWc PIN
NUMBER SIGNAL SIGNAL SIGNAL NUMBER
MNEMONIC MNEMONIC MNEMONIC
1 D00 BBSY* D08 1
2 D01 BCLR* D09 2
3 D02 ACFL* D10 3
4 D03 BG9IN* D11 4
5 D04 BG0OUT* D12 5
6 D05 BG1IN* D13 6
7 D06 BG1OUT* D14 7
8 D07 BG2IN* D15 8
9 GND BG2OUT* GND 9
10 SYSCLK BG3IN* SYSFAIL* 10
11 GND BG3OUT* BERR* 11
12 DS1* BR0* SYSRESET* 12
13 DS0* BR1* LWORD* 13
14 WRITE BR2* AM5 14
15 GND BR3* A23 15
16 DTACK* AM0 A22 16
17 GND AM1 A21 17
18 AS* AM2 A20 18
19 GND AM3 A19 19
20 IACK* GND A18 20
21 IACKIN* - A17 21
22 ICAKOUT* - A16 22
23 AM4 GND A15 23
24 A07 IRQ7* A14 24
25 A06 IRQ6* A13 25
26 A05 IRQ5* A12 26
27 A04 IRQ4* A11 27
28 A03 IRQ3* A10 28
29 A02 IRQ2* A09 29
30 A01 IRQ1* A08 30
31 -12V - +12V 31
32 +5V +5V +5V 32
Table 4.11a. P1 Pin Definitions; Slots 1 - 12
PIN ROWa ROWb ROWc PIN
NUMBER SIGNAL SIGNAL SIGNAL NUMBER
MNEMONIC MNEMONIC MNEMONIC
1 ECLTRG0 +5V CLK10+ 1
2 -2V GND CLK10- 2
3 ECLTRG1 RSV1 GND 3
4 GND A24 -5.2V 4
5 LBUSA00 A25 LBUSC00 5
6 LBUSA01 A26 LBUSC01 6
7 -5.2V A27 GND 7
8 LBUSA02 A28 LBUSC02 8
9 LBUSA03 A29 LBUSC03 9
10 GND A30 GND 10
11 LBUSA04 A31 LBUSC04 11
12 LBUSA05 GND LBUSC05 12
13 -5.2 +5V -2V 13
14 LBUSA06 D16 LBUSC06 14
15 LBUSA07 D17 LBUSC07 15
16 GND D18 GND 16
17 LBUSA08 D19 LBUSC08 17
18 LBUSA09 D20 LBUSC09 18
19 -5.2V D21 -5.2V 19
20 LBUSA10 D22 LBUSC10 20
21 LBUSA11 D23 LBUSC11 21
22 GND GND GND 22
23 TTLTRG0* D24 TTLTRG1* 23
24 TTLTRG2* D25 TTLTRG3* 24
25 +5V D26 GND 25
26 TTLTRG4* D27 TTLTRG5* 26
27 TTLTRG6* D28 TTLTRG7* 27
28 GND D29 GND 28
29 RSV2 D30 RSV3 29
30 MODID D31 GND 30
31 GND GND +24V 31
32 SUMBUS +5V -24V 32
Table 4.11b. P2 Pin Definitions: Slots 1-12
3.6 CCM Power Supply
The *15 volt power supply is derived in the CCM from the VXI *24 volt supply. It is used primarily for the AD7537 DACs and OP-797 amplifiers. Figure 3.6a depicts the power supply layout.
Fig. 3.6a *15 Volt Power Supply
A PSpice analysis of the Power Supply was conducted in the following manner. A number of noise sources were introduced onto the base *24 volt power supply. A means of checking minimum and maximum current draws was also used. Switches S2 and S3 are provided for the short circuit test. Switches S1 and S4 are used to change the load conditions from 100 to 350 ma.. Below is a list of parameters used in this test:
* V1, 5 *24 volts from VXI;
* V2, 6 Ripple Source - 150 mv, 60 HZ;
* V3, 7 Noise Source - 20 mv, 10 KHZ;
* V4, 8 Spike Source - *10 Volts, 250 pulse width, 20 ms pulses;
* V5 Total V1 + V2 + V3 + V4;
* V9 Total V5 + V6 + V7 + V8;
Results of the simulation show the output voltage are *15 Volts @250 ma with 52.4 micro volts peak to peak ripple
Figure 3.6b depicts the test circuit used in PSpice simulation.
Fig 3.6b. PSpice simulation circuit.
Figure 3.6c depicts the 300 millivolt ripple with 20 n volts at 10 KHZ noise that was introduced on the base *24 voltage. Spikes with amplitudes of *10 volts were also introduced (Figure 3.6d). The +15 volt output is depicted in Figure 3.6e shows the minimum, maximum, and shorted load results while Figure 3.6f is an enhanced wave form showing the output of the +15 volt supply with a 52 micro volt peek to peek ripple with a 10 micro volt spike.
Fig 3.6c Input 60 HZ 338 peak to peak ripple..
Fig 3.6d Input spikes (*10 volts, 250 ns. pulse width, 20 ms period).
Fig. 3.6e. Output voltage with minimum, maximum and shorted loads.
Fig 3.6f Output +15 volts with 53 micro volt ripple.
Test results from the simulation on the power supply shows that its configuration is sufficient to provide low noise, low ripple, and *15 volts output for the Programmable Bucking Source.
4. Front Panel
The CCM module front panel elements are divided into five categories:
* elements for OC1 signals: 5 Lemo type connectors for the following signals;
b) BUCK +
c) BUCK -
* elements for Bucking signals: 4 Lemo type connectors for the following signals;
a) INT +
b) INT -
c) EXT +
d) EXT -
* elements for OC2 signals: 5 Lemo type connectors for the following signals;
b) BUCK +
c) BUCK -
* coil input connector: 3M 3705/3706 series 34 pin EMI shielded, locking connector;
* module status elements : two LEDs, indicating the following module status:
MODSEL - module select;
ERRORST - VXI and module error indicator.
The module front panel will be painted Almond in color with black lettering.
Front panel dimensions and placement of components shown in Fig 4a.
Fig 4a CCM Front Panel
5. Combining CCMs
The CCMs can be combined together to provide additional source signals or bucking signals for magnetic measurements. For most cases two CCM are enough. Their interconnections are shown in Figure 5a. If more modules are to be connected EXT+ and EXT- connections must be used.
Fig 5a. CCM Interconnection
6. Application Note
The following circuits configurations depict three Probe configuration requested by MTF. Figure 6a shows a configuration Bucked Quadrupole Strength Measurement:
Fig 6a Buck Quadrupole Strength Measurement
Figure 6b shows the relay and Front panel configuration, for the circuit shown in Figure 6a.
Picture PLT1.DRW GOES HERE
Figure 6c shows a configuration Bucked Harmonic Measurement with Simultaneous Reference:
Fig 6c Bucked Harmonic Measurement with Simultaneous Reference
Figure 6d shows the relay and Front panel configuration, for the circuit shown in Figure 6c.
Picture PLT3.DRW GOES HERE
Figure 6e shows a configuration Quadrupole Buck Strength Measurement:
Figure 6f shows the relay and Front panel configuration, for the circuit shown in Figure 6e.
Picture PLT2.DRW GOES HERE
7. Appendix A...Register-Based Programming
The Coil Configuration Module (CCM) is a register-based device.
Register-based programming is a series of read and write directly to the CCM registers. This increases throughput speed since commands parsing is eliminated and the registers can be accessed from VXI backplaine.
This appendix containes the information you need for register-based programming. The contents include:
* Register Addressing
* Computer Configurations
* Register Descriptions Command Descriptions and Execution
Register addressing for register