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C-Size VXIbus

FNAL Coil Configuration Module 1001A

Installation and Operational Manual

RD Controls Special Project Note 14.0 Printed October 1994

Contents

CHAPTER 1. 1-1

Getting Started 1-1

Introduction 1-1

Module Description 1-2

Hardware Components 1-6

CHAPTER 2. 2-1

Preparing a VXIbus Card for Installation 2-1

CCM-1001A Logical Address 2-1

Setting I/O Addresses (DT9110, (U37)) 2-2

ID Register (READ ONLY) 2-2

Device Class 2-3

Address Space 2-3

Manufacturer ID: 2-3

Device Type Register 2-3

Required Memory 2-4

Model Code 2-4

Installing the VXI Card 2-6

Installation and Removal 2-6

CHAPTER 3. 3-1

CCM-1001A Register-Based Addressing 3-1

About Register-Based Programming 3-2

Addressing the Registers 3-2

Manufacturer ID (Read) Register 3-5

Device Type ( Read) Register 3-5

I/O Status (Read) / Control (Write) Register 3-5

Channel 1 (Write) Register 3-6

Channel 2 (Write) Register 3-6

Channel 3 (Write) Register 3-6

Channel 4 (Write) Register 3-6

Channel 5 (Write) Register 3-7

Channel 6 (Write) Register 3-7

Channel 7 (Write) Register 3-7

Channel 8 (Write) Register 3-8

Channel 9 (Write) Register 3-8

Channel 10 (Write) Register 3-8

Summing Resistor -- H1 & H2 (Write) Register 3-8

Summing Resistor -- F1 & F2 (Write) Register 3-9

Channel 1 & 2 Status (Read) Register 3-9

Channel 3 & 4 Status (Read) Register 3-9

Channel 5 & 6 Status (Read) Register 3-10

Channel 7 & 8 Status (Read) Register 3-10

Channel 9 & Summing Resistor OC1 Status (Read) Register 3-10

Channel 10 & Summing Resistor OC_2 Status (Read) Register 3-11

CCM Command (Read) Register 1 3-11

CCM Command (Read) Register 2 3-11

Board Serial Number (Read) Register 3-11

Reading the Registers 3-12

ID and Device Type Register 3-12

I/O Status Register 3-12

Channel 1 & 2 Status Register 3-13

Channel 3 & 4 Status Register 3-14

Channel 5 & 6 Status Register 3-15

Channel 7 & 8 Status Register 3-15

Channel 9 & Summing Resistor OC_1 Status Register 3-16

Channel 10 & Summing Resistor OC_2 Status Register 3-16

CCM Command Register 1 3-17

CCM Command Register 2 3-17

CCM Board Serial Number Register 3-18

Interrupt Request 3-19

Writing to the Registers 3-19

Channel 1 Set Register 3-20

Channel 2 Set Register 3-20

Channel 3 Set Register 3-21

Channel 4 Set Register 3-21

Channel 5 Set Register 3-22

Channel 6 Set Register 3-22

Channel 7 Set Register 3-23

Channel 8 Set Register 3-23

Channel 9 Set Register 3-24

Channel 10 Set Register 3-24

Summing Resistor OC_1 Register 3-24

Summing Resistor, OC_2 Register 3-25

CCM Command Register 1 3-25

CCM Command Register 2 3-26

Number of Boards Allowed 3-26

Serial Number 3-26

CHAPTER 4 4-1

Embedded Controllers 4-1

EPLD CCM Relay Controller One and Two (U38 & U39) 4-1

EPLD CCM Serial Number and Miscellaneous Controller (U40) 4-5

CHAPTER 5 5-1

CCM-1001A Calibration 5-1

Necessary Equipment 5-2

Calibrating the Four Summing Resistors 5-2

APPENDIX A 1

Replaceable Parts 1

Channel Configuration and Control Schematics 1

EPLD Pin Out 15

Printed Circuit Board Modifications 15

Connector J1 and J10 Pinouts 15

Table of

Figures and

Tables

Figure 1-1 Channel Interconnection 1-3

Figure 1-2 Shunting Disconnected Coil 1-4

Figure 1-3 Bucking Configuration 1-5

Figure 1-4 CCM-1001A Front Panel 1-7

Figure 2-1 Logical Address 2-3

Figure 2-2 ID/Device Type Register Configuration -6

Figure 3-1 CCM-1001A Registers within A16 Address Space 3-2

Figure 3-2 CCM-1001A Registers within A24 Address Space 3-3

Figure 4-1 Control Circuit Block Diagram 4-4

Figure 5-1 Summing Diagram 5-1

Figure 5-2 Summing Resistor PC Board Placement 5-3

Figure A-1 EPLD Pin Out for U38 and U39 Appendix A-3

Figure A-2 EPLD Pin Out for U40 Appendix A-3

Figure A-3 J1 Connector Pin Out Appendix A-4

Figure A-4 J10 Connector Pin Out Appendix A-5

Table 1-1 Summing Resistor Values 1-4

Table 3-1 VXI Interface Card Address 3-3

Chapter 1

Getting Started

Introduction

This manual is divided into five chapters and one appendix:

Chapter 1. Getting Started introduces the CCM-1001A C-Size VXIbus Coil Configuration Module and describes the hardware components.

Chapter 2. Installing the CCM-1001A describes how to install the module in the VXI C-Size Crate, and describes the Logical and I/O Addressing of the module.

Chapter 3. CCM-1001A Register-Based Addressing describes addressing of the CCM-1001A module.

Chapter 4. Embedded Controller describes the module embedded controllers.

Chapter 5. CCM-1001A Calibration describes calibration of the two (2) Summing Resistors.

Appendix A. Replaceable Parts list the parts and descriptions of replaceable parts for the CCM1001A and provides schematic diagrams and EPLD logic diagrams.

Module

Description

Chapter Contents

This chapter shows how the FNAL Coil Configuration Module 1001A (CCM-1001A) operates. The sections are as follows:

· CCM-1001A Description.................................................................. 1-2

1. What is Coil Configuration................................................... 1-2

2. What is Disconnect.............................................................. 1-4

3. What is Selection................................................................. 1-4

4. What is Summing................................................................. 1-4

5. What is Bucking................................................................... 1-5

CCM-1001A Description

The CCM-1001A is a register-based VXIbus C-size card that takes signals from up to 10 magnet test probes and directs them to one of three outputs. These go through Coil Configuration Channels (CCC) which are capable of performing the following functions;

* they can change the polarity of an incoming signal;

* they can configure incoming coil signals either as source coil signals or as bucking coils

What is Coil Configuration

Configuration is the arrangement of input signals who’s output signal creates a specific pattern. This is accomplished by selecting specific channels to be Source or Bucking inputs. All Coil Configuration Channels are chained in series as shown in Figure 1-1 and are connected to one of three output groups OC1, OC2 and Buck. Additional terminals are provided which duplicate some of the above mention output groups but have different names. It is done to facilitate combining several Coil Configuration Modules in one coil configuration unit.

Figure 1-1 Coil Configuration Channel Interconnections

What is Disconnect

All Channels have the Disconnect function, which is used to remove a coil from the configuration scheme. When Disconnect function is chosen, a 240 ohm 1/4 watt resistor (Figure 1-2 ) is placed across the unused coil to shunt voltages that can be developed across the disconnected coil during probe rotation. Signals coming from other channels are bypassed through the disconnected channel. With the Disconnect function the user has the option to choose an additional function called Bucking. This option will be explained later on in this Chapter.

Figure 1-2 Shunting disconnected coil

What is Selection

All channels have the Selection function. Through the use of this function the user can direct any number of coil signals to any of two output groups OC1 or OC2

What is Summing

Currents induced into the source coils are summed across a summing resistor with a value defined by summing relays. The summing resistors are placed in series with the source signals. This allows the user to place other coils in parallel with the summing resistor to Buck the source signal. The Bucking option will be explained later on in this Chapter.

Each of the outputs OC1 and OC2 has a summing resistor associated with its output. These resistors are arranged so that four combinations of summing resistor values can be derived (Figure 1-1). These derivations are provided by summing relays controlled by control signals SumH1, SumH2, for the summing resistor connected to the OC1 output group; and SumF1, SumF2 for the summing resistor connected to the OC2 output group. Table 1-2 shows the different values that can be derived by using the control signals SumH1 and SumH2. Here BYPASS means 0 value for the summing resistor.

SumH1 SumH2

BYPASS OFF OFF

15 Ohms ON OFF

10 Ohms OFF ON

5 Ohms ON ON

Table 1-1, Summing Resistor Values

What is Bucking

Only four channels are able to provide the Bucking function. They are channels 1 through 4. With the Bucking function the user can place one or more coils across the Summing resistor (Figure 1-3) to buck a chosen harmonic in the source signal. When the user selects the Bucking function a 50K 12-bit resistor array from the Bucking Source Module. (See RD Controls Special Project Note 13.0 Bucking Source Module for details.) is placed is series with the Bucking coil to adjust the Bucking current

Figure 1-3.

Hardware Components

The Coil Configuration Module contains a top shield, a bottom shield, and a relay temperature enclosure. To ensure the lowest noise rejection and temperature stability, the enclosure should be in place before operating this module.

Attention: The CCM-1001A must be in its upright position within 30 degrees of vertical before applying power to the module.

Because most of the relays in this module are Mercury-Wetted contact relays, disposal of this material should be handled with special precautions. Treat or dispose off these materials according to regulations under the Resource Conservation and Recovery Act as administered by the USEPA or appropriate state agency.

The CCM-1001A has a number of connectors available on the front panel. (Figure 1-2)

· OC1_SUM

· OC1_OUT

· OC1_IN

· OC2_SUM

· OC2_OUT

· OC2_IN

· Buck Series Resistor

· Probe Input

Connector's OC1_SUM, OC1_OUT, OC1_IN, OC2_SUM, OC2_OUT, and OC2_IN are standard LEMO single pin connectors. The outer shell of these connectors is isolated from the enclosure earth ground and carries shield signals from a Probe to a shield driving circuit. It can be grounded at users choice.

Figure 1-4. CCM-1001A Front Panel

OC1_Sum connector

Connector OC1_SUM is connected to the output of Summing Resistors SR1 and SR2 (Figure 1-1). In a single module setup this output would be one of the legs (for purposes of simplicity we will define it to be +) connect to high impedance front end circuit.

OC1_OUT connector

Connector OC1_OUT is the common point for of all the chained channels and would be the second leg (for purposes of simplicity we will define it to be - ) connected to the high impedance front end circuit.

OC1_IN connector

Connector OC1_IN is connected to the input of channel one and also Summing Resistors SR1 and SR2 (Figure 1-1). It is used when more than one CCM is needed.

OC2_Sum connector

Connector OC2_SUM is connected to the output of Summing Resistors SR3 and SR4 (Figure 1-1). In a single module setup this output would be one of the legs (for purposes of simplicity we will define it to be + ) of the OC2 output signal connected to the input of a second high impedance front end circuit.

OC2_OUT connector

Connector OC2_OUT is the common point for all the chained channels and would be the second leg (for purposes of simplicity we will define it to be - ) connected to the input of the second high impedance front end circuit.

OC2_IN connector

Connector OC2_IN is connected to the input of channel one and also Summing Resistors SR3 and SR4 (Figure 1-1). It is used when more than one CCM is needed.

Connector's Buck Series Resistor and Probe Input are AMP 40 pin shielded connectors. The shell of the connector is at earth ground. Probe shields are brought into the module via inner pins and feed to the LEMO connectors via printed circuit shield plane. Refer to Appendix A for the circuit Pinouts

Buck Series Resistor connector

This connector is used to connect the CCM-1001A module to the Bucking Source Module (BSM). (See RD Controls Special Project Note 14.0.) Refer to Appendix A for the circuit pinouts.

Probe Input connector

This connector is used to connect coils to the CCM-1001A card.

Refer to Appendix A for the connector pinouts.

Chapter 2

Preparing a VXIbus Card for Installation

Chapter Contents

This chapter describes the procedures for configuring CCM-1001A, installing the module, and using the Coil Configuration Module.

· CCM -1001A Logical Address................................................................ 2-1

· Setting I/O (DT9110 Addressing)........................................................... 2-2

· Preparing for Installation and Removal................................................. 2-6

CCM-1001A Logical Address

Each device in a system has a unique Logical Address. The value of the CCM-1001A’s Logical Address is set by switch SW1. If a value of FFhex is chosen as the module’s Logical Address then the CCM-1001A will become a dynamically configured (DC) device, meaning the value of its Logical Address register will be programmed automatically during initialization by the Resource Manager.

The CCM-1001A is shipped with the default Logical Address of 1 as shown in Figure 2-1.

Figure 2-1 Logical Address

If more than one Coil Configuration Module is used, then subsequent cards must be set to a different Logical Addresses.

Setting I/O Addresses (DT9110, (U37))

The CCM-1001A employs a DT-9110 VXI adapter card from Interface Technology. This card provides a complete VXI bus interface capable of performing all register based data transfers. The following are registers which have to be programmed by the user:

ID Register (READ ONLY)

BIT # 15<-14 13<-12 11<-0

CONTENTS DEVICE CLASS ADDRESS SPACE MANUFACTURER ID

DEVICE CLASS (Read Only)

This field indicates the classification of the DT9110 according to the following table. The default value is 11.

VALUE CLASS

00 Memory

01 Extended

10 Message Based

11 Register Based

ADDRESS SPACE (Read Only)

This field indicates the addressing mode(s) of the DT9110's operational registers according to the following table. The default value is 00.

VALUE MODE

00 A16 /A24

01 A16 /A32

10 RESERVED

11 A16 Only

Manufacturer ID (Read Only)

This number uniquely identifies the manufacturer of the device. The list of ID numbers is maintained by the VXIbus consortium. Each VXIbus device manufacturer has exactly one Manufacturer ID number. Numbers are assigned to manufacturers in decreasing order beginning with number 4095. See the VXIbus specifications for information on obtaining a manufacturer ID number. The manufacturer ID number for Fermilab is 3775

Device Type Register (Read Only)

The Device Type register is programmed by selectively setting switches RN1 and RN2 (See Fig. 2-2, ID/DEVICE TYPE REGISTER CONFIGURATION). The Device Type register fields are defined by the VXIbus specification as follows.

Device Type Register

BIT # 15 <- 12 11 <- 0

CONTENTS REQUIRED MEMORY MODEL CODE

REQUIRED MEMORY

This field is only required for A16/A24 and A16/A32 devices. These 4 bits contain a number m, which is between 0 and 15. The required amount of memory M is defined as

M=256 a * 2 23-m ,

where a is the value address space field in the ID register. This equation gives the amount of A24 VMEbus memory space (in bytes) resident on the device. The DT9110 will automatically decode the address bits to the corresponding resolution. The default value of this field is 0x0008, which corresponds to 32768 bytes (32 Kbytes) if the DT9110 is configured as an A16/A24 device, or 8388608 bytes ( 8 Mbytes) if the DT9110 is configured as an A16/A32 device. If the DT9110 is configured as an A16 only device, these four bits are the upper bits of the model code.

NOTE: If the DT9110 is configured as an A16/A24 device, the minimum size of the A24 memory is 256 bytes. The maximum size is 1/2 of the complete A24 VMEbus address space. If the DT9110 is configured as an A16/A32 device, the minimum size of the A32 memory is 65536 bytes (64 Kbytes). The maximum size is 1/2 of the complete A32 VMEbus address space. It is a good idea to limit the memory space of any one device to 1/4 of the available address space.

MODEL CODE

This field contains a unique card identifier that is defined by the manufacturer. In the case of an A16 only device, this field occupies all 16 bits of the Device Type register. Model code's 0-255 (0-FFHEX) are reserved for Slot 0 devices. The default value for this field is 0. Therefore, if the Device Type register value is not modified by the user, the system's Resource Manager may give a warning during initialization indicating "redundant Slot 0 capability", or other similar warning. Programming a model code value greater than 255 will eliminate this warning. The Model Code for the Coil Configuration Module is 1001.

Figure 2-2 ID/DEVICE TYPE REGISTER CONFIGURATION.

The default values for the ID register and Device Type register are as follows.

ID Register

BIT # 15 <- 14 13 <- 12 11 <- 0

BINARY VALUE 11 00 111010111111

DEFINITION DEVICE CLASS (register base) ADD. SPACE = A16/A24 MANUF. ID = 3775

Device Type Register

BIT # 15 <- 12 11 <- 0

BINARY VALUE 1000 001111101001

DEFINITION REQUIRED MEMORY32768 bytes (A24 register)or 8388608 bytes (A32 registers) MODEL CODE = 1001

Installing the VXI Card

Installation and Removal

Before beginning the installation make sure that the modules logical address and I/O controller card perimeters are set.

Installing the CCM-1001A into the crate

The CCM -1001A can be installed in any C-Size crate slot, except slot 0. VXIbus cards fit only one way into VXIbus crate and care must be taken to avoid misalignment of the module and bending the pin on the two connectors at the rear of the module.

Attention: Do not install the VXIbus card with power on the crate.

The installation should proceed in the following order:

1. Gently slide the VXIbus card into crate.

2. Use your thumb just under the extractor handles to firmly press the module into the crates P1 and P2 connectors.

3. Tighten the two front panel mounting screws

Removing the CCM-1001A from the crate.

Attention: Do not remove the VXIbus card from the crate while the crate power is turned-on.

1. Loosen the two front panel mounting screws.

2. Press down on the bottom extractor while pulling up on the top extractor,

3. Pull the module away from the crate

Once the CCM-1001A is away from the backplane connectors of the crate, the module can be easily pulled away from the crate.

Chapter 3

Addressing

CCM-1001A

Chapter Contents

This chapter describes the addressing parameters for the CCM-1001A card. The contents of this chapter are:

· About Register-Based Programming

· Addressing the Registers

· The Base Address

· Register Definitions

· Reading the Registers

· Interrupt Requests

· Writing to the Registers

· Number of boards allowed

· Serial number

About

Programming

The CCM-1001A module is a register-based module that allows the user to read and write directly to the module's registers. Register-based programming also allows the use of an embedded controller or 0 slot controller to access the VXIbus directly to increase throughput.

Addressing the

Registers

Each VXI register-based device is allocated addresses for 64 register. The DT9110 makes available only 32 registers. Addresses for the I/O device are located within the first 64K of memory in the A16 area. Addresses for the registers controlling the Coil Configuration Channels are located in the A24 area.

Figure's 3-1 and 3-2 show the Coil Configuration Module’s register address location within the A16 and A24 address space.

Figure 3-1. CCM-1001A Registers within A16 Address Space

Figure 3-2. CCM-1001A Registers within A24 Address Space

The DT9110 VXIbus Interface card incorporates all of the register based configuration registers required by the VXIbus specification and decodes the address lines to provide a select signal (DDSEL) for all A16 Device Dependent registers to a given logical address. All registers conform to the definitions and rules given in the VXIbus specification. The VXIbus register map is shown below in Table 3-1.

I/O (DT9110) VXIbus Interface Card Address

00h ID/Logical Address undefined

02h Device Type undefined

04h Status Register Control Register

06h Offset reserved

08h Device Dependent Command Register

0Ah Device Dependent Parameter Register

0Ch Device Dependent reserved

0Eh Device Dependent undefined

Table 3-1, VXI Interface Card Address

The Base Address

The base addresses for the DT9110's device registers is represented by A6. through A15 address lines and is determined by the device's unique logical address. The logical address is determined SW1, or is programmed by the system's Resource Manager if a value of FFH is placed on SW1. The logical address corresponds to bits 6 -13 of the device register base address. Bits 14 and 15 of the base address are both 1. VXIbus accesses to the DT9110's registers are automatically detected and controlled by the DT9110.

To read or write to specific registers, you must specify the register address either in hexadecimal or decimal number. This address consists of a base address plus a register offset (lower A1-A15 address lines).

Manufacturer ID (Read) Register ( b = base address; 00h = register offset; Returns EBFh = 3775)

b + 00h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Write undefined

Device Type (Read) Register (b = base address; 02h = register offset; Returns 3E9h = 1001 )

b + 02h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Write undefined

I/O Status (Read) / Control (Write) Register (b = base address; 04h = register offset; * Refer to “Writing to the Register” for an explanation of using the control register to reset module.)

b + 04h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

* Write A24/A32 MODID not used Ready Passed SYSFAILInhibit Reset

Read X X X X X X X X X X

Channel 1 (Write) Register (b = base address; 08h = register offset; * Refer to “Writing to the Register” for an explanation of using channel # 1 register.)

b + 08h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

* Write not used Dis.reset Dis.set Buckreset Buckset Sel.reset Sel.set Pol.reset Pol.set

Read not used

Channel 2 (Write) Register (b = base address; 0Ah = register offset; * Refer to “Writing to the Register” for an explanation of using channel # 2 register.)

b + 0Ah 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

* Write not used Dis.reset Dis.set Buckreset Buckset Sel.reset Sel.set Pol.reset Pol.set

Read not used

Channel 3 (Write) Register (b = base address; 0Ch = register offset; * Refer to “Writing to the Register” for an explanation of using channel # 3 register.)

b + 0Ch 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

* Write not used Dis.reset Dis.set Buckreset Buckset Sel.reset Sel.set Pol.reset Pol.set

Read not used

Channel 4 (Write) Register (b = base address; 0Eh = register offset; * Refer to “Writing to the Register” for an explanation of using channel # 4 register.)

b + 0Eh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

* Write not used Dis.reset Dis.set Buckreset Buckset Sel.reset Sel.set Pol.reset Pol.set

Read not used

Channel 5 (Write) Register (b = base address; 080h = register offset; * Refer to “Writing to the Register” for an explanation of using channel # 5 register.)

b + 080h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

* Write not used Dis.reset Dis.set notused notused Sel.reset Sel.set Pol.reset Pol.set

Read not used

Channel 6 (Write) Register (b = base address; 082h = register offset; * Refer to “Writing to the Register” for an explanation of using channel # 6 register.)

b + 082h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

* Write not used Dis.reset Dis.set notused notused Sel.reset Sel.set Pol.reset Pol.set

Read not used

Channel 7 (Write) Register (b = base address; 084h = register offset; * Refer to “Writing to the Register” for an explanation of using channel # 7 register.)

b + 084h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

* Write not used Dis.reset Dis.set notused notused Sel.reset Sel.set Pol.reset Pol.set

Read not used

Channel 8 (Write) Register (b = base address; 086h = register offset; * Refer to “Writing to the Register” for an explanation of using channel # 8 register.)

b + 086h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

* Write not used Dis.reset Dis.set notused notused Sel.reset Sel.set Pol.reset Pol.set

Read not used

Channel 9 (Write) Register (b = base address; 040h = register offset; * Refer to “Writing to the Register” for an explanation of using channel # 9 register.)

b + 040h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

* Write not used Dis.reset Dis.set notused notused Sel.reset Sel.set notused notused

Read not used

Channel 10 (Write) Register (b = base address; 0400h = register offset; * Refer to “Writing to the Register” for an explanation of using channel # 10 register.)

b + 0400h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

* Write not used Dis.reset Dis.set notused notused Sel.reset Sel.set notused notused

Read not used

Summing Resistor - H1 & H2 (Write) Register (b = base address; 042h = register offset; * Refer to “Writing to the Register” for an explanation of using summing - H1 & H2 register.) The Summing Resistor names H1 & H2 are reference names for relays.

b + 042h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

* Write not used SumH2Off SumH2On SumH1Off SumH1On

Read not used

Summing Resistor - F1 & F2 (Write) Register b = base address; 0402h = register offset; * Refer to “Writing to the Register” for an explanation of using summing - F1 & F2 register.) The Summing Resistor names L1 & L2 are reference names for relays.

b + 0402h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

* Write not used SumF2Off SumF2On SumF1Off SumF1On

Read not used

Channel 1 & 2 Status (Read) Register (b = base address; 010h = register offset

b + 010h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

* Write not used

Read not used Dis Buck Sel Pol Dis. Buck Sel. Pol.

Channel 2 Channel 1

Channel 3 & 4 Status (Read) Register (b = base address; 012h = register offset

b + 012h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

* Write not used

Read not used Dis Buck Sel Pol Dis. Buck Sel. Pol.

Channel 4 Channel 3

Channel 5 & 6 Status (Read) Register (b = base address; 0100h = register offset

b + 0100h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

* Write not used

Read not used Dis X Sel Pol Dis. X Sel. Pol.

Channel 6 Channel 5

Channel 7 & 8 Status (Read) Register (b = base address; 0102h = register offset

b + 0102h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

* Write not used

Read not used Dis X Sel Pol Dis. X Sel. Pol.

Channel 8 Channel 7

Channel 9 & Summing Resistor OC1 Status (Read) Register (b = base address; 014h = register offset

b + 014h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

* Write not used

Read not used X X X X SumH2 SumH1 Dis. Sel.

Sum Channel 9

Channel 10 & Summing Resistor OC_2 Status (Read) Register (b = base address; 0104h = register offset

b + 0104h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

* Write not used

Read not used X X X X SumF2 SumF1 Dis. Sel.

Sum Channel 10

CCM Command (Read) Register 1 (b = base address; 026h = register offset

b + 026h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

* Write not used

Read not used X X X X X AdjMode X MeasureMode

CCM Command (Read) Register 2 (b = base address; 0206h = register offset

b + 0206h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

* Write not used

Read not used X X X X X AdjMode X MeasureMode

Board Serial Number (Read) Register (b = base address; 3806h = register offset

b + 3806h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

* Write not used

Read X X X X X X X X 0 0 0 0 0 0 0 0

Reading the

Registers

You can read the following Coil Configuration registers:

1. Manufacturer’s ID Register (base + 00h)

2. Device Type Register (base + 02h)

3. I/O Status Register (base + 04h)

4. Channel 1 & 2 Status Register (base + 010h)

5. Channel 3 & 4 Status Register (base + 012h)

6. Channel 5 & 6 Status Register (base + 0100h)

7. Channel 7 & 8 Status Register (base + 0102h)

8. Channel 9 & Summing Resistor OC1 Status Register (base + 014h)

9. Channel 10 & Summing Resistor OC2 Status Register (base + 0104h)

10. CCM Command Register 1 (base + 026h)

11. CCM Command Register 2 (base + 0206h)

12. Board Serial Number (base + 3806h)

ID and Device Type

ID Register, reading the ID register returns EBFh which identifies the manufacturer as Fermi National Laboratory and indicates that the module is an A16/A24 register-based device.

Device Type Register, reading the Device Type register returns 3E9h which indicates the device as the CCM-1001A Coil Configuration Module.

I/O Status Register

Six bits (bit 0, 1, 2, 3, 14, and 15) of the I/O Status register (register 04h) provide information on the DT9110 interface board.

Bit No. BitMnemonic Comments

0 Reset This bit reflects the state of the RESET bit in the Control register

1 SYSFAIL This bit reflects the state of the SYSFAIL INHIBIT bit in the Control register

2 Passed The PASSED bit is normally used to indicate the success or failure of a device’s self test. Because the DT9110 doses not execute a self test, this bit is automatically set to 1 when the READY bit is set to 1.

3 Ready This bit is used to inform the system controller that the DT9110 is ready to begin operations.

14 MODID This bit is the inverted state of the MODID pin.

15 A16/A24 This bit is only valid for A16/A24 and A16/A32 devices. A one (1) in this field indicates that the DT9110’s A24 or A32 registers can be accessed.

Channel 1 & 2 Status Register

Eight bits (bit 0, 1, 2, 3, 4, 5, 6, and 7 of the Channel 1 & 2 Status register (register 010h) provide information about Channels 1 & 2.

Bits BitMnemonic Description

0 Polarity 0 - in this field indicates that Channel 1’s Polarity is set to FORWARD. 1 - indicates Polarity is set to REVERSE.

1 Selection 0 - in this field indicates that Channel 1’s Selection is set to output OC_1. 1 - indicates output is set to OC_2.

2 Bucking 0 - in this field indicates that Channel 1’s Bucking is not set. 1 - indicates that Bucking is selected.

3 Disconnect 0 - in this field indicates that Channel 1’s input is not disconnected. 1 - indicates Channel 1’s input is disconnected.

4 Polarity 0 - in this field indicates that Channel 2’s Polarity is set to FORWARD. 1 - indicates Polarity is set to REVERSE.

5 Selection 0 - in this field indicates that Channel 2’s Selection is set to output OC_1. 1 - indicates output is set to OC_2.

6 Bucking 0 - in this field indicates that Channel 2’s Bucking is not set. 1 - indicates that Bucking is selected.

7 Disconnect 0 - in this field indicates that Channel 2’s input is not disconnected. 1 - indicates Channel 2’s input is disconnected.

8-15 X not used

Channel 3 & 4 Status Register

Eight bits (bit 0, 1, 2, 3, 4, 5, 6, and 7 of the Channel 3 & 4 Status register (register 012h) provide information about Channels 3 & 4.

Bits BitMnemonic Description

0 Polarity 0 - in this field indicates that Channel 3’s Polarity is set to FORWARD. 1 - indicates Polarity is set to REVERSE.

1 Selection 0 - in this field indicates that Channel 3’s Selection is set to output OC_1. 1 - indicates output is set to OC_2.

2 Bucking 0 - in this field indicates that Channel 3’s Bucking is not set. 1 - indicates that Bucking is selected.

3 Disconnect 0 - in this field indicates that Channel 3’s input is not disconnected. 1 - indicates Channel 3’s input is disconnected.

4 Polarity 0 - in this field indicates that Channel 4’s Polarity is set to FORWARD. 1 - indicates Polarity is set to REVERSE.

5 Selection 0 - in this field indicates that Channel 4’s Selection is set to output OC_1. 1 - indicates output is set to OC_2.

6 Bucking 0 - in this field indicates that Channel 4’s Bucking is not set. 1 - indicates that Bucking is selected.

7 Disconnect 0 - in this field indicates that Channel 4’s input is not disconnected. 1 - indicates Channel 4’s input is disconnected.

8-15 X not used

Channel 5 & 6 Status Register

Six bits (bit 0, 1, 3, 4, 5, and 7 of the Channel 5 & 6 Status register (register 0100h) provide information about Channels 5 & 6.

Bits BitMnemonic Description

0 Polarity 0 - in this field indicates that Channel 5’s Polarity is set to FORWARD. 1 - indicates Polarity is set to REVERSE.

1 Selection 0 - in this field indicates that Channel 5’s Selection is set to output OC_1. 1 - indicates output is set to OC_2.

3 Disconnect 0 - in this field indicates that Channel 5’s input is not disconnected. 1 - indicates Channel 5’s input is disconnected.

4 Polarity 0 - in this field indicates that Channel 6’s Polarity is set to FORWARD. 1 - indicates Polarity is set to REVERSE.

5 Selection 0 - in this field indicates that Channel 6’s Selection is set to output OC_1. 1 - indicates output is set to OC_2.

7 Disconnect 0 - in this field indicates that Channel 6’s input is not disconnected. 1 - indicates Channel 6’s input is disconnected.

2,6,8-15 X not used

Channel 7 & 8 Status Register

Six bits (bit 0, 1, 3, 4, 5, and 7 of the Channel 7 & 8 Status register (register 0102h) provide information about Channels 7 & 8.

Bits BitMnemonic Description

0 Polarity 0 - in this field indicates that Channel 7’s Polarity is set to FORWARD. 1 - indicates Polarity is set to REVERSE.

1 Selection 0 - in this field indicates that Channel 7’s Selection is set to output OC_1. 1 - indicates output is set to OC_2.

3 Disconnect 0 - in this field indicates that Channel 7’s input is not disconnected. 1 - indicates Channel 7’s input is disconnected.

4 Polarity 0 - in this field indicates that Channel 8’s Polarity is set to FORWARD. 1 - indicates Polarity is set to REVERSE.

5 Selection 0 - in this field indicates that Channel 8’s Selection is set to output OC_1. 1 - indicates output is set to OC_2.

7 Disconnect 0 - in this field indicates that Channel 8’s input is not disconnected. 1 - indicates Channel 8’s input is disconnected.

2,6,8-15 X not used

Channel 9 & Summing Resistor OC_1 Status Register

Four bits (bit 0, 1, 2, and 3) of the Channel 9 & Summing Resistor OC_1 Status register (register 014h) provide information about Channel 9 & the Summing Resistors for OC_1

Bits BitMnemonic Description

0 Selection 0 - in this field indicates that Channel 9’s Selection is set to output OC_1. 1 - indicates output is set to OC_2.

1 Disconnect 0 - in this field indicates that Channel 9, input is not disconnected. 1 - indicates Channel 9’s input is disconnected.

2 SumH1 0 - on bit-2 and 3 indicates that summing resistor value is 5 ohms.0 - on bit-2 and a (1) on bit-3 indicates that summing resistor value is 10 ohms.1 - on bit-2 and a (0) on bit-3 indicates that summing resistor value is 15 ohms.

3 SumH2 1 - on bit-2 and a (1) on bit-3 indicates that summing resistor value is 0 ohms.

4-15 X not used

Channel 10 & Summing Resistor OC_2 Status Register

Four bits (bit 0, 1, 2, and 3) of the Channel 10 & Summing Resistor OC_2 Status register (register 0104h) provide information about Channel 10 and the Summing Resistors for OC_2

Bits BitMnemonic Description

0 Selection 0 - in this field indicates that Channel 10’s Selection is set to output OC_1. 1 - indicates output is set to OC_2.

1 Disconnect 0 - in this field indicates that Channel 10, input is not disconnected. 1 - indicates Channel 10’s input is disconnected.

2 SumF1 0 - on bit-2 and 3 indicates that summing resistor value is 5 ohms.0 - on bit-2 and a (1) on bit-3 indicates that summing resistor value is 10 ohms.1 - on bit-2 and a (0) on bit-3 indicates that summing resistor value is 15 ohms.

3 SumF2 1 - on bit-2 and a (1) on bit-3 indicates that summing resistor value is 0 ohms.

4-15 X not used

CCM Command Register 1

Four bits (bit 0, 1, 2, and 3) of the CCM Command register 1 (register 026h) provide information about which mode CCM is set to. Busy of register 1, read only Channels 1 - 4 (refer to CCM Command register 2 description).

Bits BitMnemonic Description

0 MeasureMode 1 - in this field indicates that Measurement Mode has been selected, and the front panels push button has been disabled.0 - on bit-0 and bit-2 indicates CCM is in IDLE Mode and front panel push button is enabled.

1 Busy 1 - in this field indicates that the relays are being set or reset and no action can be taken until a zero (0) has been read.

2 AdjustmentMode 1 - in this field indicates that Adjustment Mode has been selected, and the front panels push button has been disabled.0 - on bit-0 and bit-2 indicates CCM is in IDLE Mode and front panel push button is enabled.

3-6 X not used

7 ExtendedStatus 1 - in this field indicates that there are more than eight (8) status bits and they are displayed in bits 8 through 15. Default is zero (0).

8-15 X not used

CCM Command Register 2

Four bits (bit 0, 1, 2, and 3) of the CCM Command register 2 (register 0206h) provide information about which mode CCM is set to. Busy in this register is the sum of CCM Command Register 1’s Busy and CCM Command Register 2’s Busy.

Bits BitMnemonic Description

1 Busy 1 - in this field indicates that the relays are being set or reset and no action can be taken until a zero (0) has been read.

3-6 X not used

7 ExtendedStatus 1 - in this field indicates that there are more than eight (8) status bits and they are displayed in bits 8 through 15. Default is zero (0).

8-15 X not used

CM Board

Serial Number

Eight bits (bit 0 - 7) of the CCM Board Serial Number register (register 03806h) provide the board serial number.

Bits BitWeight Description

0 1 0 - in this field and a one (1) in bits-1 - 7 would indicate that the boards serial number is one (1).

1 2 0 - in this field and ones (1’s) in the remaining bits would indicate the boards serial number is two (2).

2 4 0 - in this field and ones (1’s) in the remaining bits would indicate the boards serial number is four (4).

3 8 0 - in this field and ones (1’s) in the remaining bits would indicate the boards serial number is eight (8).

4 16 0 - in this field and ones (1’s) in the remaining bits would indicate the boards serial number is sixteen (16).

5 32 0 - in this field and ones (1’s) in the remaining bits would indicate the boards serial number is thirty two (32).

6 64 0 - in this field and ones (1’s) in the remaining bits would indicate the boards serial number is sixty four (64).

7 128 0 - in this field and ones (1’s) in the remaining bits would indicate the boards serial number is one hundred and twenty eight (128).

8-15 X not used

Interrupt Request

The Coil Configuration Module generates an interrupt request by pulling low the appropriate interrupt line on the DT9110 I/O interface board. The Coil Configuration Module generates this interrupt when the front panels push button is activated to reset the module. This reset can only be activated if the module is in the IDLE mode configuration. The CCM-1001A uses IRQ-six (6) to indicate a reset. An interrupt of the CCM software services the interrupt. When a VXIbus interrupt acknowledge cycle occurs, the DT9110 will confirm that the interrupt acknowledge cycle applies to the DT9110’s interrupt request. If not, it will assert IACKOUT. When interrupt acknowledge cycle applies to the board, the DT9110 places the 16-bit STATUS/ID word onto the VXI data bus. Release of the interrupt request line and setting of the DTACK cycle is defined by VXI specification.

Writing to the

Registers

The following are Coil Configuration registers:

1. Channel 1 Set Register (base + 08h)

2. Channel 2 Set Register (base + 0Ah)

3. Channel 3 Set Register (base + 0Ch)

4. Channel 4 Set Register (base + 0Eh)

5. Channel 5 Set Register (base + 080h)

6. Channel 6 Set Register (base + 082h)

7. Channel 7 Set Register (base + 084h)

8. Channel 8 Set Register (base + 086h)

9. Channel 9 Set Register (base + 040h)

10. Channel 10 Set Register (base + 0400h)

11. Summing Resistor OC_1 Register (base + 042h)

12. Summing Resistor OC_2 Register (base + 0402h

13. CCM Command Register 1 (base + 026h)

14. CCM Command Register 2 (base + 0206h)

Channel 1

Set (Write) Register

Four bits (bit 0, 1, 2, and 3 of the Channel 1 Set register (register 08h) provide information about setting Channel 1.

Bits BitMnemonic Description

0 Polarity 0 - in this field resets Channel 1’s Polarity to FORWARD. 1 - sets Polarity to REVERSE.

1 Selection 0 - in this field resets Channel 1’s Selection to output OC_1.1 - sets Channel 1’s Selection to output OC_2.

2 Bucking 0 - in this field disables Bucking.1 - sets Channel 1 to Bucking mode.

3 Disconnect 0 - in this field resets Channel and connects input coil.1 - sets Channel 1 to disconnect and removes coil from channel.

4 - 15 X not used

Channel 2

Set (Write) Register

Four bits (bit 0, 1, 2, and 3 of the Channel 2 Set register (register 0Ah) provide information about setting Channel 2.

Bits BitMnemonic Description

0 Polarity 0 - in this field resets Channel 2’s Polarity to FORWARD. 1 - sets Polarity to REVERSE.

1 Selection 0 - in this field resets Channel 2’s Selection to output OC_1. 1 - sets Channel 2’s Selection to output OC_2.

2 Bucking 0 - in this field disables Bucking. 1 - sets Channel 1 to Bucking mode.

3 Disconnect 0 - in this field resets Channel and connects input coil.1 - sets Channel to disconnect and removes coil from channel.

4 - 15 X not used

Channel 3

Set (Write) Register

Four bits (bit 0, 1, 2, and 3 of the Channel 3 Set register (register 0Ch) provide information about setting Channel 3.

Bits BitMnemonic Description

0 Polarity 0 - in this field resets Channel 3’s Polarity to FORWARD. 1 - sets Polarity to REVERSE.

1 Selection 0 - in this field resets Channel 3’s Selection to output OC_1. 1 - sets Channel 3’s Selection to output OC_2.

2 Bucking 0 - in this field disables Bucking. 1 - sets Channel 3 to Bucking mode.

3 Disconnect 0 - in this field resets Channel and connects input coil.1 - sets Channel 3 to disconnect and removes coil from channel.

4 - 15 X not used

Channel 4

Set (Write) Register

Four bits (bit 0, 1, 2, and 3 of the Channel 4 Set register (register 0Eh) provide information about setting Channel 4.

Bits BitMnemonic Description

0 Polarity 0 - in this field resets Channel 4’s Polarity to FORWARD. 1 - sets Polarity to REVERSE.

1 Selection 0 - in this field resets Channel 4’s Selection to output OC_1. 1 - sets Channel 4’s Selection to output OC_2.

2 Bucking 0 - in this field disables Bucking. 1 - sets Channel 4 to Bucking mode.

3 Disconnect 0 - in this field resets Channel and connects input coil.1 - sets Channel 4 to disconnect and removes coil from channel.

4 - 15 X not used

Channel 5

Set (Write) Register

Three bits (bit 0, 1, and 3 of the Channel 5 Set register (register 080h) provide information about setting Channel 5.

Bits BitMnemonic Description

0 Polarity 0 - in this field resets Channel 5’s Polarity to FORWARD. 1 - sets Polarity to REVERSE.

1 Selection 0 - in this field resets Channel 5’s Selection to output OC_1. 1 - sets Channel 5’s Selection to output OC_2.

2 X not used

3 Disconnect 0 - in this field resets Channel and connects input coil.1 - sets Channel to disconnect and removes coil from channel.

4 - 15 X not used

Channel 6

Set (Write) Register

Three bits (bit 0, 1, and 3 of the Channel 6 Set register (register 082h) provide information about setting Channel 6.

Bits BitMnemonic Description

0 Polarity 0 - in this field resets Channel 6’s Polarity to FORWARD. 1 - sets Polarity to REVERSE.

1 Selection 0 - in this field resets Channel 6’s Selection to output OC_1. 1 - sets Channel 6’s Selection to output OC_2.

2 X not used

3 Disconnect 0 - in this field resets Channel 6 and connects input coil.1 - sets Channel 6 to disconnect and removes coil from channel.

4 - 15 X not used

Channel 7

Set (Write) Register

Three bits (bit 0, 1, and 3 of the Channel 7 Set register (register 084h) provide information about setting Channel 7.

Bits BitMnemonic Description

0 Polarity 0 - in this field resets Channel 7’s Polarity to FORWARD. 1 - sets Polarity to REVERSE.

1 Selection 0 - in this field resets Channel 7’s Selection to output OC_1. 1 - sets Channel 7’s Selection to output OC_2.

2 X not used

3 Disconnect 0 - in this field resets Channel 7 and connects input coil.1 - sets Channel 7 to disconnect and removes coil from channel.

4 - 15 X not used

Channel 8

Set (Write) Register

Three bits (bit 0, 1, and 3 of the Channel 8 Set register (register 086h) provide information about setting Channel 8.

Bits BitMnemonic Description

0 Polarity 0 - in this field resets Channel 68’s Polarity to FORWARD. 1 - sets Polarity to REVERSE.

1 Selection 0 - in this field resets Channel 8’s Selection to output OC_1. 1 - sets Channel 8’s Selection to output OC_2.

2 X not used

3 Disconnect 0 - in this field resets Channel 8 and connects input coil.1 - sets Channel 8 to disconnect and removes coil from channel.

4 - 15 X not used

Channel 9

Set (Write) Register

Four bits (bit 0, 1, 2, and 3 of the Channel 9 Set register (register 014h) provide information about setting Channel 9.

Bits BitMnemonic Description

0 X not used

1 Selection 0 - in this field resets Channel 9’s Selection to output OC_1. 1 - sets Channel 9’s Selection to output OC_2.

2 X not used

3 Disconnect 0 - in this field resets Channel and connects input coil.1 - sets Channel to disconnect and removes coil from channel.

4 - 15 X not used

Channel 10

Set (Write) Register

Four bits (bit 0, 1, 2, and 3 of the Channel 10 Set register (register 0104h) provide information about setting Channel 10.

Bits BitMnemonic Description

0 X not used

1 Selection 0 - in this field resets Channel 10’s Selection to output OC_1. 1 - sets Channel 10’s Selection to output OC_2.

2 X not used

3 Disconnect 0 - in this field resets Channel and connects input coil.1 - sets Channel to disconnect and removes coil from channel.

4 - 15 X not used

Summing Resistor

OC_1(Write) Register

Two bits (bit 0, and 1) of the Summing Resistor register (register 014h) provide information about setting the Summing resistors connected to OC_1 output.

Bits BitMnemonic Description

0 SumH1

1 SumH2 See Table 1-3 below

2 X

3 X

4 - 15 X not used

Summing Resistor

OC_2(Write) Register

Two bits (bit 0, and 1) of the Summing Resistor register (register 0104h) provide information about setting the Summing resistors connected to OC_2 output.

Bits BitMnemonic Description

0 SumF1

1 SumF1 See Table 1-3 below

2 X

3 X

4 - 15 X not used

Table 1-3 Summing Resistors

Mnemonic SumH1 or SumF1 SumH2 orSumF2

BYPASS OFF OFF

15 ohms ON OFF

10 Ohms OFF ON

5 Ohms ON ON

CCM Command (Write) Register 1

Two bits (bit 0, and 2 of the CCM Command register (register 026h) provide information about setting the three modes for the module.

Bits BitMnemonic Description

0 Meas-urementMode 1 - in this field will put the module in Measurement Mode and disable the front panel push button.

1 X not used

2 AdjustmentMode 1 - in this field will put the module in Adjustment Mode and disable the front panel push button.

3 - 15 X not used

CCM Command (Write) Register 2

Two bits (bit 0, and 2 of the CCM Command register (register 0206h) provide information about setting the three modes for the module.

Bits BitMnemonic Description

0 Meas-urementMode 1 - in this field will put the module in Measurement Mode and disable the front panel push button.

1 X not used

2 AdjustmentMode 1 - in this field will put the module in Adjustment Mode and disable the front panel push button.

3 - 15 X not used

Number of Boards Allowed

Because of software constraints, four (4) CCM-1001A modules can be used in one VXI enclosure. This number can be made larger with some software changes (refer to Terry Kiper PAFMS Software Document).

Serial Number

Each CCM-1001A module has a unique number assigned to it (1 - 256). This number is read by a EPLD on power up and the number is stored in its register. This number can be read at any time, Board Serial Number Register.

Chapter 4

Embedded Controllers

Chapter Contents

This Chapter describes the three embedded controllers that control functioning of the CCM-1001A module. They include:

· EPLD CCM Relay Controller one and two

· EPLD CCM Serial Number and Miscellaneous Controller

A block diagram in Figure 4-1 shows how the controllers are configured. The VXI bus includes READ, WRITE, UASEL, IACK, IRQ, MODID, and master reset (MRESET) control lines along with 16-bit Address bus and a 16-bit Data bus. The DT9110 interface is described in Chapters 2 and 3. Output from the DT9110 Interface Control supplies control signals, addresses and data to the embedded controllers. Each controller then directs addresses and data to the devices it controls.

EPLD CCM Relay Controller One and Two (U38 & U39 )

The EPLD Relay Controller one (U38) controls configuration of Channels 1, 2, 3, 4, 9 and summing resistors SumH1 and SumH2. The EPLD Relay Controller two (U39) controls configuration of Channels 5, 6, 7, 8, 10 and summing resistors SumF1 and SumF2. Each controller resides in a Altera EPM7128 high-density, high-performance CMOS EPLD. Both EPLD’s circuits are identical in circuit design. Their addressing differences are controlled by the selection circuitry which will be described further on in this document. The EPLD circuit includes into five logical sub circuits:

1. relay controller

2. address register

3. set/reset controller

4. read registers

5. chip selection circuit

The relay controller consists of a command register, timing circuit and module reset circuit. The command register receives data from the host computer and sets the module into one of the three modes: IDLE, ADJUSTMENT, or MEASUREMENT (refer to Chapter 3, “Writing to the Registers” for bit information).

When the circuit is placed in either ADJUSTMENT or MEASUREMENT mode, the module is locked out, meaning that data from the host computer and the signal from the front panel reset button will not be accepted and acted upon by the module unless data is directed to the command register.

This is to prevent someone from resetting the module by pushing the reset button on the front panel when the system is collecting data from the magnet field measurements. Placing the module in IDLE mode allows data to be loaded into the write registers. This also allows the front panel push button to be enabled.

The command registers can be written to and read from at any time during magnet field data collection. Care should be taken when writing to the command register to insure that field measurements are finished before changing the module mode setup.

The relays require from 1.25 to 3.5 ms minimum to switch from one position to the other. A timing circuit is needed to stretch the pulse driving the relays. The relays require from 1.25 to 3.5 ms minimum to switch from one position to the other. The timing circuit is 4.0 ms pulse to satisfy switching requirements.

The module reset circuit takes three inputs, Power Up Reset (POWRST), Push Button Reset (PBRST), and Master Reset (MRESET). These three input signals are OR’ed to accomplish two functions; clear all registers and reset all relays to a reset state.

1. Power Up Reset signal occurs when power is first applied to the module. Reset is kept active for a minimum of 250 ms to allow the power supply to stabilize.

2. The front panel Push Button is debounced through a debouncer circuit that also generates a 250 ms pulse.

3. Master Reset is asserted whenever the SYSRESET input is active or when the DT9110 has been placed into the Soft Reset state by the system controller.

On reset all read and write registers, counters, and address buffers are cleared. After all registers are cleared an internal address counter is activated to address all configuration channel relays, one at a time, and data is placed on the internal bus to reset all relays to a known state.

The Address register circuit arbitrates all read, write, and reset functions for setting and resetting the relays and registers.

The Set/Reset circuit receives data from the DT9110 data bus (BVD15..00). The first four (4) bits (BVD03...00) of the data bus are used to activate a particular relay. (refer to Chapter 3, “Writing to the Registers” for bit information). The circuitry is designed to prevent set and reset signals being active at the same time. Data is stored in the register until either new data is input, or the reset signal clears it out.

The read circuitry arranges data in bytes from the Set/Reset and command (refer to Chapter 3, “Reading the Registers”, for more information).

The Chip Selection is a hardware function which allows two identical EPLD circuits to reside on the same board. When a low (Signal) is placed on the select pin of EPLD U38 the addressing for this device allows access to Channels 1, 2, 3, 4, 9, and summing resistors SumH1 & SumH2. When a high (signal), is placed on the select pin of EPLD U39 the addressing for this device allows access to Channels 5, 6, 7, 8, 10, and summing resistors SumF1 & SumF2.

Figure 4-1, Control Circuit Block Diagram

EPLD CCM Serial Number and

Miscellaneous Controller (U40 )

The Serial Number and Miscellaneous Controller are built on an Altera EPM5064 EPLD. It is used to read and store the board’s unique serial number (1 - 256 ). This EPLD also is used to arbitrate reset functions that are used on the board. Its output is then used as inputs for Relay Controllers one and two.

Chapter 5

CCM-1001A

Calibration

Chapter Contents

This Chapter describes the procedure for calibrating the CCM-1001A module. It includes the following sections:

· necessary equipment

· calibrating the four summing resistors

It is assumed that the appropriate software has been written to operate the module from a Host Computer, or that an Embedded Processor residing in the slot zero is in place. To calibrate the module the user has to use the test programs provided with the module. A circuit diagram in Figure 5-1 shows the relationship between the pairs of summing resistors and the rest of the circuitry.

Figure 5-1, Summing Diagram

Necessary Equipment

A high quality five (5) digit multimeter should be used to calibrate the summing resistors. A thin bladed straight slotted screwdriver or a non metallic trimmer screwdriver is needed to adjust the 32-turn potentiometers RX1 - RX4.

Calibrating the

Four Summing Resistors

Each output OC1 and OC2 have associated with it a summing resistor circuit. For ease of explanation we will describe the adjustment for OC1 output summing resistors only. Figure 5-2 shows the placement of access holes for the four summing resistors on the module enclosure.

With the multimeter connected across OC1_Sum and OC1_in LEMO connectors, set the multimeter to its lowest OHMS setting. Next address the Summing Resistors for OC1 and set them to the off position. Check the reading on the multimeter; it should read one ohm or less. Next address the board again and set the summing value to 5 ohms. With the screwdriver adjust potentiometer RX1 to 5 ohms. Next, address the board and set the summing value to 10 ohms. With the screw driver adjust potentiometer RX2 to 10 ohms. Now address the board and set the summing value to 15 ohms; the value read on the multimeter should be the sum of RX1 and RX2. Repeat the same adjustment procedures for output OC2’s summing resistors using RX3 and RX4 resistors and OC2_Sum and OC2_in connectors. No other adjustments are needed for the board.

Figure 5-2, Summing Resistor PC Board Placement

Appendix A

Replaceable Parts

Contents

The contents of Appendix A is:

· replacement Parts List

· channel configuration and control schematics

· EPLD pinouts

· printed circuit board modifications

· connector pinouts

Caution

The circuit board assembly uses a 6-layer circuit board. Care must be exercised in removing and replacing parts, otherwise damage will result to the circuit board.

Replacement Parts List

The following is the parts list for CCM-1001A, it doses not contain such parts as screws, nuts, and assorted test pins.

CCM-1001A Replacement Parts

ReferenceDesignation Qty Part Description Mft. Mft. Part Number

U42-43 2 74als244 TI FNAL 1455-8244

RL8,9,17,18,26,27,35,36,75,76,77,78 12 Relay American Zettler AZ830P2-2C-5DSE

RL1-7RL10-16RL19-25RL28-34RL37-74 66 Relay Claire HGWM52212N00

1 VXI Hardware Kit ICS Elect. 113991

CCM-1001A Replacement Parts (continuation)

J1 & J10 2 Cable Ass. Amp 749201-1

1 Printed Circuit Board FNAL 1670-EB-329000

J1 & J10 2 40-pin connectors PC Board Amp 749830-4

J2,3,7 3 Twin Lemo Connectors Lemo EPY.00.250.NTN

U37 1 Interface Board Interface Tech-nology DT9110

L1 1 Inductor 130 - 150 hn @40 Amps Newark 5298

Sw1-5 5 Dip Switches 8 Poisson Newark 84F804 TYPE GDR08

Led 1,2 1 Dual Red LED Newark 50F6026 TYPE 553-0111

U38,39 2 PLCC Socket Newark QILE84P-410T

U40 1 PLCC Socket Newark QILE44P-410T

U38,39 2 EPLD Altera EPM7128C84-20

U40 1 EPLD Altera EPM5064JC-2

U4,5,6,9,10,15,16,20,21,34,29,30,23,24,26,25,27,28,31,32,33 21 Peripheral Relay Driver Allegro ULN2803A

U41 1 IC9602 one shot Newark DM9602

U44,45 2 IC DS1232 Newark

P1,2 2 VXI card edge connector 96 pin Newark DIN-96CPC-SR1-TR

F1 1 Fuse - Pico 3 amp Newark 28F136 TYPE 251003

BP1,28 28 IC Filter Cap’s 923CZ5U103M0508 Newark 65F929

SW2 1 Front Panel Push Button TPA11CG-RA0 Newark 13F3638

R1,11,21,31,41,42,43,44,45,46 10 Resistor 240 ohm 1/4 w FNAL

R47,48,49,50 4 Resistor 1K 1% 1/8 w FNAL

RX1, RX3 2 Pot 10 ohm 32 turn Newark 67F5821 TYPE 64W

RX2, RX4 2 Pot 20 ohm 32 turn Newark 67F5822 TYPE 64W

R56,58 2 Resistor 33K 1/4 w FNAL

R57,60 2 Resistor 4.7K 1/4 w FNAL

R55,59 2 Resistor 470 ohm 1/4 w FNAL

R62,63,64,65,66 5 Resistor 2.2K 1/4 w FNAL

RNSER 1 SIP Resistor 2.2K 1/4 w Newark

Channel Configuration and

Control Schematics

The following 12 schematics is broken up into Channels, Connectors, and Digital Circuitry parts.

EPLD Pin Out

The following Figures A1 and A2 show the pinouts for EPLD’s U38, 39 and 40. The EPLD’s are compiled on an IBM compatible computer using Altera MAX+Plus II software. File names for U38 and U39 are ccmrelay.gdf, and ccmrelay.sym. File name for U40 is ccmseral.gdf, and ccmseral.sym. The MAX+Plus II output file names are ccmrelay.pof, ccmseral.pof and requires a MAX+Plus II EPLD programmer to program the device. A Data I/O PAL programmer can also be used to program these devices.

Printed Circuit

Board Modifications

Changes to circuit design include three wires to be soldered to the back side of the printed circuit board. Care must be exercised not to overheat the board when soldering these wires.

1. Cut the trace on the non-component (bottom) of the board between C21 and C22 on the P1 connector.

2. Solder a wire between P1/C21 and D21 ( IACKIN ) of the DT9110 Interface Board.

3. Solder a wire between P1/C22 and D22 ( IACKOUT ) of the DT9110 Interface Board.

4. Solder a wire between U44 pin 6 and U45 pin 6.

Connector J1 and

J10 Pinouts

The two connectors J1 and J10 are Amplite 40 pin right angle receptacle headers with latching blocks. Connector J1 is the signal input connector from the magnet test probe . Connector J10 is the Bucking Resistor interconnect connector which brings the programmable Bucking resistor to the CCM-1001A module and places it in series with the chosen Bucking Coil. Figure's A-3 and A-4 show the signal (Net) names assigned to each pin.

D D S D P

R I I E I O

E S / e / S L S L

S C B / n e M C C C C

B E H U R C a n R H H H B H

V R 2 S E L i a E 1 5 4 V 4

D V S G Y G K V n i G S S S V S D R

0 A E E N I R 1 C p A n A N E E E C E 0 S

7 4 D T D N D 6 C 2 2 1 1 D T T T C T 4 T

-----------------------------------------------------------------_

/ 11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 |

BVD05 | 12 74 | POLCH4SET

VCC | 13 73 | BVD00

SELCH4SET | 14 72 | GND

DISCH5SET | 15 71 | POLCH2SET

SELCH5RST | 16 70 | POLCH2RST

DISCH5RST | 17 69 | POLCH3RST

BUCKCH4SET | 18 68 | POLCH3SET

GND | 19 67 | SUMH1_OFF

BUCKCH4RST | 20 66 | VCC

DISCH4RST | 21 65 | POLCH1SET

SELCH4RST | 22 EPM7128LC84 64 | POLCH1RST

BUCKCH2RST | 23 63 | SUMH1_ON

BUCKCH2SET | 24 62 | A6

BUCKCH3RST | 25 61 | /EXTRST

VCC | 26 60 | DISCH3RST

BUCKCH3SET | 27 59 | GND

DISCH2RST | 28 58 | SUMH2_ON

SELCH2RST | 29 57 | DISCH3SET

SELCH2SET | 30 56 | BVD06

BVD02 | 31 55 | BVD03

GND | 32 54 | SUMH2_OFF

|_ 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 _|

------------------------------------------------------------------

/ R A / B V A e e G V B D S G S B B S S V

U E 3 R U C 5 n n N C V I E N E U U E E C

A S E S C a a D C D S L D L C C L L C

S E G Y o o 0 C C C K K C C

E R W O u u 1 H H H C C H H

L V R U t t 1 1 1 H H 3 3

E T 2 1 R R S 1 1 S R

D S S E R S E S

T T T S E T T

T T

Figure A-1 U38, U39

R R / R R

E E E E E

S S X S / S

E E R S E R E B

R R E E R E R V

V V S V R R V G G V D

E E E C 0 S E N R E 0

D D T C 0 T D D D D 7

-----------------------------------_

/ 6 5 4 3 2 1 44 43 42 41 40 |

BVD03 | 7 39 | TIMEIN2

BVD02 | 8 38 | TIMEOUT1

GND | 9 37 | TIMEIN1

GND | 10 36 | VCC

A13 | 11 35 | A1

A12 | 12 EPM5064LC 34 | /UASEL

A11 | 13 33 | A2

VCC | 14 32 | GND

SER01 | 15 31 | GND

SER02 | 16 30 | BVD00

SER03 | 17 29 | BVD01

|_ 18 19 20 21 22 23 24 25 26 27 28 _|

------------------------------------

S S B G B B T V T S S

E E V N V V I C I E E

R R D D D D M C M R R

0 0 0 0 0 E E 0 0

5 4 6 5 4 I O 6 7

N U

3 T

Figure A-2 U40

J1 Description

1 SIGCH1+

2 SIGCH1-

3 SHIELD

4 SIGCH2+

5 SIGCH2-

6 SHIELD

7 SIGCH3+

8 SIGCH3-

9 SHIELD

10 SIGCH4+

11 SIGCH4-

12 SHIELD

13 SIGCH5+

14 SIGCH5-

15 SHIELD

16 SIGCH6+

17 SIGCH6-

18 SHIELD

19 SIGCH7+

20 SIGCH7-

21 SHIELD

22 SIGCH8+

23 SIGCH8-

24 SHIELD

25 SIGCH9+

26 SIGCH9-

27 SHIELD

28 SIGCH10+

29 SIGCH10-

30 SHIELD

Figure A - 3, Connector J1

J10 Description

1 BUCK_COIL3

2 BUCK_IN3

3 BUCK_OUT3

4 BUCK_SOURCE3

5 BUCK_COIL4

6 BUCK_IN4

7 BUCK_OUT4

8 BUCK_SOURCE4

9 BUCK_OUT2

10 BUCK_SOURCE2

11 BUCK_IN2

12 BUCK_COIL2

13 BUCK_OUT1

14 BUCK_SOURCE1

15 BUCK_IN1

16 BUCK_COIL1

17 OC1_BUCK+

18 OC1_BUCK-

19 OC2_BUCK+

20 OC2_BUCK-

30 DGND

31 DGND

Figure A - 4, Connector J10

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