C-Size VXIbus

FNAL Bucking Source Module 1002A

Installation and Operational Manual

RD Controls Special Project Note 15.0 Printed January 30, 1995

Contents

CHAPTER 1. 1-2

Getting Started 1-2

Introduction 1-2

Module Description 1-3

Modes of Operation 1-4

Measurement Mode 1-4

Test Mode 1-5

Adjustment Mode 1-5

Idle Mode 1-5

Module Reset 1-5

Channel Configuration 1-6

Hardware Components 1-8

CHAPTER 2. 2-1

Preparing a VXIbus Card for Installation 2-1

BSM-1002A Logical Address 2-1

Setting I/O Addresses (DT9110, (U19)) 2-2

ID Register (READ ONLY) 2-3

Device Class 2-3

Address Space 2-3

Manufacturer ID: 2-3

Device Type Register 2-3

Required Memory 2-4

Model Code 2-4

Installing the VXI Card 2-6

Installation and Removal 2-6

CHAPTER 3. 3-1

BSM-1002A Register-Based Addressing 3-1

About Register-Based Programming 3-2

Addressing the Registers 3-2

Register Definitions 3-5

Manufacturer ID (Read) Register 3-5

Device Type ( Read) Register 3-5

I/O Status (Read) / Control (Write) Register 3-5

Channel 1 (Read / Write) Set Register 3-5

Channel 2 (Read / Write) Set Register 3-6

Channel 3 (Read / Write) Set Register 3-6

Channel 4 (Read / Write) Set Register 3-6

Channel 5 (Read / Write) Set Register 3-7

Channel 6 (Read / Write) Set Register 3-7

Channel 7 (Read / Write) Set Register 3-7

Channel 8 (Read / Write) Set Register 3-8

Channel 1 (Read / Write) Reset Register 3-8

Channel 2 (Read / Write) Reset Register 3-8

Channel 3 (Read / Write) Reset Register 3-9

Channel 4 (Read / Write) Reset Register 3-9

Channel 5 (Read / Write) Reset Register 3-9

Channel 6 (Read / Write) Reset Register 3-10

Channel 7 (Read / Write) Reset Register 3-10

Channel 8 (Read / Write) Reset Register 3-11

BSM Command (Read / Write) Register 3-11

Status (Read ) Register 3-11

Status Type (Read ) Register 3-11

Board Serial Number (Read) Register 3-11

Reading the Registers 3-13

ID and Device Type Register 3-13

I/O Status (Read) Register 3-14

Channel 1 through 8 Status (Read) Registers 3-15

BSM Command (Read) Register 1 3-16

Status (Read) Register 3-16

Status Type (Read) Register 3-17

BSM Board Serial Number (Read) Register 3-18

Interrupt Request 3-19

Writing to the Registers 3-19

I/O Control (Write) Register 3-20

BSM Command (Write) Register 3-20

Channel 1 through 8 (Write) Registers 3-21

Number of Boards Allowed 3-22

Serial Number 3-22

CHAPTER 4 4-1

Embedded Controller 4-1

APPENDIX A 1

Replaceable Parts 1

Channel Configuration and Control Schematics 3

EPLD Pin Out 16

Printed Circuit Board Modifications 17

Connector J1 Pinout 18

Table of

Figures and

Tables

Figure 1-1 Typical BSM, CCM configuration 1-4

Figure 1-2 Binary weighted resistor array channel 1-7

Figure 2-1 Logical Address 2-2

Figure 2-2 ID/Device Type Register Configuration 2-5

Figure 3-1 BSM-1002A Registers within A16 Address Space 3-2

Figure 3-2 BSM-1002A Registers within A24 Address Space 3-3

Figure 4-1 BSM-1002A Logic block diagram 4-2

Figure A-1 EPLD Pin Out for U20 Appendix A-1

Figure A-2 EPLD Pin Out for U25 Appendix A-2

Table 3-1 VXI Interface Card Address 3-3

Table 1-1 Basic Resistor Values Appendix A -3

Table A-1 Bucking J-1 pin out Appendix A-4

Chapter 1

Getting Started

Introduction

This manual is divided into four chapters and one appendix:

Chapter 1. Getting Started introduces the BSM-1002A C-Size VXIbus Bucking Source Module and describes the hardware components.

Chapter 2. Preparing a VXIbus card for Installation describes how to install the module in the VXI C-Size Crate, and describes the Logical and I/O Addressing of the module.

Chapter 3. BSM-1002A Register-Based Addressing describes addressing of the BSM-1002A module.

Chapter 4. Embedded Controller describes the module embedded controller.

Appendix A. Replaceable Parts list the parts and descriptions of replaceable parts for the BSM-1002A and provides schematic diagrams and EPLD logic diagrams.

Module

Description

Chapter Contents

This chapter describes the FNAL Bucking Source Module (BSM-1002A) 8 - channel binary -weighted 12-bit resistor array module.

· BSM-1002A description

· Modes of operation

· Module reset

· Channel configuration

BSM-1002A Module

Description

The BSM-1002A module is a register-based VXIbus C-size card that contains eight (8) binary-weighted latched 12-bit resistor array channels. Each resistor in the array has a tolerance of 1% and a temperature coefficient of ± 50ppm/°C. Each channel has a maximum input voltage of ±10 Volts.

Each of the BSM-1002A channels has two multiplexed outputs; module select and output select. Module select gives the user the capability of selecting a particular CCM-1001A module in the system for any given BSM-1002A channel (for information on CCM-1001A , refer to - RD Controls Special Project Note 14.0). The user can also select which output, OC1 or OC2 in the CCM-1001A module the binary weighted 12-bit resistor array are attached to. Figure 1-1 shows a typical BSM-1002A and CCM-1001A configuration.

Figure 1-1.Typical BSM, CCM configuration

Modes of Operation

The BSM-1002A module has four Modes of operation:

· Measurement Mode

· Test Mode

· Adjustment Mode

· Idle Mode

Measurement Mode

Measurement Mode is set by the host computer after all channels have been configured in IDLE Mode and the magnet measurement system is ready to take data. The front panel push button is disabled in this mode so the module cannot be reset during data collection.

Test Mode

Test Mode is set by the host computer to test all relay drivers. This function is accomplished by placing a test code on the internal bus with a value of 5555h and AAAAh. This is sent to all relay driver, set and reset registers. The driver registers are then read back and compared with the code that was sent. If the return code doesn’t match, bit-1 (Error) of the Status register is then set to one (1) indicating a module Error. At the same time bit-2 (Test Error) of the STATUS TYPE register is set to one (1) to inform the user that an error has occurred during Test Mode, and the address of the relay driver register that fails to match is then placed into the STATUS TYPE register bit’s 3 through 6. The front panel push button is disabled in this mode so the module cannot be reset during relay driver testing.

Adjustment Mode

Adjustment Mode is set by the host computer after all channels have been configured in IDLE Mode. This mode is used primarily by the system to calibrate itself before magnet measurement data is taken. The front panel push button is disabled in this mode so the module cannot be reset during system calibration.

Idle Mode

Idle Mode is used to configure the BSM-1002A. It is the only Mode that allows data to be sent to the relay drivers which select which of the binary-weighted 12-bit resistors will be selected. The front panel push button is enabled in this mode so the module can be reset.

Module Reset

Module reset occurs when the BSM-1002A is powered on or reset by the host computer or by the front panel push button. All eight channels are then set to bypass, meaning no resistors are chosen. In addition all module registers are set to zero (0) and the module is then set to IDLE mode.

Channel Configuration

Figure 1-2 shows how each resistor is placed in relationship with each other. A two coil latching, double pole double throw relay is used with a maximum contact resistance of 60mW. These relays are used to place each resistor in series or in bypass at user’s discretion. A total resistor value of 50,837.7W with a tolerance of 1% can be attained with all bits set to a decimal value of 4095. Each resistor is 1/8 watt 1% metal film with excellent low noise and voltage coefficient characteristics. Table 1-1 shows the basic values which apply to this module.

Bit Resistor

0 12.1

1 24.3

2 48.7

3 97.6

4 196

5 392

6 787

7 1.58K

8 3.16K

9 6.34K

10 12.7K

11 25.5K

Table 1-1, Basic Resistor Values

Hardware Components

Hardware Components

The Bucking Source Module contains a top shield and a bottom shield. To ensure the lowest noise rejection and temperature stability, the shields should be in place before operating this module.

Chapter 2

Preparing a VXIbus Card for Installation

Chapter Contents

This chapter describes the procedures for configuring, installing the module, and using the BSM-1002A Bucking Source Module.

· BSM -1002A Logical Address................................................... 2-1

· Setting I/O (DT9110 Addressing)............................................. 2-2

· Preparing for Installation and Removal...................................... 2-6

BSM-1002A Logical Address

Each device in a system has a unique Logical Address. The value of the BSM-1002A’s Logical Address is set by switch SW1. If a value of FFhex is chosen as the module’s Logical Address, the BSM-1002A will become a dynamically configured (DC) device, meaning the value of its Logical Address register will be programmed automatically during initialization by the Resource Manager.

The BSM-1002A is shipped with the default Logical Address of 1 as shown in Figure 2-1.

Figure 2-1 Logical Address

If more than one Bucking Source Module is used, then subsequent cards must be set to a different Logical Addresses.

Setting I/O Addresses (DT9110, (U19))

The BSM-1002A employs a DT-9110 VXI adapter card from Interface Technology. This card provides a complete VXI bus interface capable of performing all register based data transfers. The following are registers which have to be programmed by the user:

ID Register (READ ONLY)

BIT # 15<-14 13<-12 11<-0

CONTENTS DEVICE CLASS ADDRESS SPACE MANUFACTURER ID

DEVICE CLASS (Read Only)

This field indicates the classification of the DT9110 according to the following table. The default value is 11.

VALUE CLASS

00 Memory

01 Extended

10 Message Based

11 Register Based

ADDRESS SPACE (Read Only)

This field indicates the addressing mode(s) of the DT9110's operational registers according to the following table. The default value is 00.

VALUE MODE

00 A16 /A24

01 A16 /A32

10 RESERVED

11 A16 Only

Manufacturer ID (Read Only)

This number uniquely identifies the manufacturer of the device. The list of ID numbers is maintained by the VXIbus consortium. Each VXIbus device manufacturer has exactly one Manufacturer ID number. Numbers are assigned to manufacturers in decreasing order beginning with number 4095. See the VXIbus specifications for information on obtaining a manufacturer ID number. The manufacturer ID number for Fermilab is 3775

Device Type Register (Read Only)

The Device Type register is programmed by selectively setting switches RN1 and RN2 (See Fig. 2-2, ID/DEVICE TYPE REGISTER CONFIGURATION). The Device Type register fields are defined by the VXIbus specification as follows.

Device Type Register

BIT # 15 <- 12 11 <- 0

CONTENTS REQUIRED MEMORY MODEL CODE

REQUIRED MEMORY

This field is only required for A16/A24 and A16/A32 devices. These 4 bits contain a number m, which is between 0 and 15. The required amount of memory M is defined as

M=256 a * 2 23-m ,

where a is the value address space field in the ID register. This equation gives the amount of A24 VMEbus memory space (in bytes) resident on the device. The DT9110 will automatically decode the address bits to the corresponding resolution. The default value of this field is 0x0008, which corresponds to 32768 bytes (32 Kbytes) if the DT9110 is configured as an A16/A24 device, or 8388608 bytes ( 8 Mbytes) if the DT9110 is configured as an A16/A32 device. If the DT9110 is configured as an A16 only device, these four bits are the upper bits of the model code.

NOTE: If the DT9110 is configured as an A16/A24 device, the minimum size of the A24 memory is 256 bytes. The maximum size is 1/2 of the complete A24 VMEbus address space. If the DT9110 is configured as an A16/A32 device, the minimum size of the A32 memory is 65536 bytes (64 Kbytes). The maximum size is 1/2 of the complete A32 VMEbus address space. It is a good idea to limit the memory space of any one device to 1/4 of the available address space.

MODEL CODE

This field contains a unique card identifier that is defined by the manufacturer. In the case of an A16 only device, this field occupies all 16 bits of the Device Type register. Model code's 0-255 (0-FFHEX) are reserved for Slot 0 devices. The default value for this field is 0. Therefore, if the Device Type register value is not modified by the user, the system's Resource Manager may give a warning during initialization indicating "redundant Slot 0 capability", or other similar warning. Programming a model code value greater than 255 will eliminate this warning. The Model Code for the Bucking Source Module is 1002.

Figure 2-2 ID/DEVICE TYPE REGISTER CONFIGURATION.

The default values for the ID register and Device Type register are as follows.

ID Register

BIT # 15 <- 14 13 <- 12 11 <- 0

BINARY VALUE 11 00 111010111111

DEFINITION DEVICE CLASS (register base) ADD. SPACE = A16/A24 MANUF. ID = 3775

Device Type Register

BIT # 15 <- 12 11 <- 0

BINARY VALUE 1000 001111101001

DEFINITION REQUIRED MEMORY32768 bytes (A24 register)or 8388608 bytes (A32 registers) MODEL CODE = 1002

Installing the VXI Card

Installation and Removal

Before beginning the installation make sure that the modules logical address and I/O controller card perimeters are set.

Installing the BSM-1002A into the crate.

The BSM-1002A can be installed in any C-Size crate slot, except slot 0. VXIbus cards fit only one way into VXIbus crate and care must be taken to avoid misalignment of the module and bending the pin on the two connectors at the rear of the module.

Attention: Do not install the VXIbus card with power on the crate.

The installation should proceed in the following order:

1. Gently slide the VXIbus card into crate.

2. Use your thumb just under the extractor handles to firmly press the module into the crates P1 and P2 connectors.

3. Tighten the two front panel mounting screws

Removing the BSM-1002A from the crate.

Attention: Do not remove the VXIbus card from the crate while the crate power is turned-on.

1. Loosen the two front panel mounting screws,

2. Press down on the bottom extractor while pulling up on the top extractor,

3. Pull the module away from the crate.

Once the BSM-1002A is away from the backplane connectors of the crate, the module can be easily pulled away from the crate.

Chapter 3

Addressing

BSM-1002A

Chapter Contents

This chapter describes the addressing parameters for the BSM-1002A card. The contents of this chapter are:

· About Register-Based Programming

· Addressing the Registers

· The Base Address

· Register Definitions

· Reading the Registers

· Interrupt Requests

· Writing to the Registers

· Number of boards allowed

· Serial number

About

Register-Based

Programming

The BSM-1002A module is a register-based module that allows the user to read and write directly to the module's registers. Register-based programming also allows the use of an embedded controller or 0 slot controller to access the VXIbus directly to increase throughput.

Addressing the

Registers

Each VXI register-based device is allocated addresses for 64 register. The DT9110 makes available only 32 registers. Addresses for the I/O device are located within the first 64K of memory in the A16 area (base1 = 0). Addresses for the registers controlling the Bucking Source Module are located in the A24 area (base2 = 20000).

Figure's 3-1 and 3-2 show the Bucking Source Module’s register address location within the A16 and A24 address space.

Figure 3-1. BSM-1002A Registers within A16 Address Space

Figure 3-2. BSM-1002A Registers within A24 Address Space

The DT9110 VXIbus Interface card incorporates all of the register based configuration registers required by the VXIbus specification and decodes the address lines to provide a select signal (DDSEL) for all A16 Device Dependent registers to a given logical address. All registers conform to the definitions and rules given in the VXIbus specification. The VXIbus register map is shown below in Table 3-1.

I/O (DT9110) VXIbus Interface Card Address

Register Offset Read Registers Write Registers

00h ID/Logical Address undefined

02h Device Type undefined

04h Status Register Control Register

06h Offset reserved

08h Device Dependent Command Register

0Ah Device Dependent Parameter Register

0Ch Device Dependent reserved

0Eh Device Dependent undefined

Table 3-1, VXI Interface Card Address

The Base Address

The base addresses for the DT9110's device registers is represented by A6. through A15 address lines and is determined by the device's unique logical address. The logical address is determined SW1, or is programmed by the system's Resource Manager if a value of FFH is placed on SW1. The logical address corresponds to bits 6 -13 of the device register base address. Bits 14 and 15 of the base address are both 1. VXIbus accesses to the DT9110's registers are automatically detected and controlled by the DT9110.

To read or write to specific registers, you must specify the register address either in hexadecimal or decimal number. This address consists of a base address plus a register offset (lower A1-A15 address lines).

Register Definitions

Manufacturer ID (Read) Register ( b = base1 address; 00h = register offset; Returns EBFh = 3775)

b + 00h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Write undefined

Read 0 0 0 0 1 1 1 0 1 0 1 1 1 1 1 1

Device Type (Read) Register (b = base1 address; 02h = register offset; Returns 3EAh = 1002 )

b + 02h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Write undefined

Read 0 0 0 0 0 0 1 1 1 1 1 0 1 0 1 0

I/O Status (Read) / Control (Write) Register (b = base1 address; 04h = register offset; * Refer to “Writing to the Register” for an explanation of using the control register to reset module.)

b + 04h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

* Write A24/A32 MODID not used

Read X X X X X X X X X X Ready Passed SYSFAILInhibit Reset

Channel 1 (Read / Write) Set Register (b = base address; 00h = register offset; * Refer to “Writing to the Register” for an explanation of using channel # 1 register.)

b + 00h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Write OutputSelection Mod Selection bit-12 bit-11 bit-10 bit-9 bit-8 bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1

Read not used

Channel 2 (Read / Write) Set Register (b = base2 address; 02h = register offset; * Refer to “Writing to the Register” for an explanation of using channel # 2 register.)

b + 02h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Write OutputSelection Mod Selection bit-12 bit-11 bit-10 bit-9 bit-8 bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1

Read not used

Channel 3 (Read / Write) Set Register (b = base2 address; 04h = register offset; * Refer to “Writing to the Register” for an explanation of using channel # 3 register.)

b + 04h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Write OutputSelection Mod Selection bit-12 bit-11 bit-10 bit-9 bit-8 bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1

Read not used

Channel 4 (Read / Write) Set Register (b = base2 address; 06h = register offset; * Refer to “Writing to the Register” for an explanation of using channel # 4 register.)

b + 06h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Write OutputSelection Mod Selection bit-12 bit-11 bit-10 bit-9 bit-8 bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1

Read not used

Channel 5 (Read / Write) Set Register (b = base2 address; 08h = register

offset; * Refer to “Writing to the Register” for an explanation of using channel # 5 register.)

b + 08h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Write OutputSelection Mod Selection bit-12 bit-11 bit-10 bit-9 bit-8 bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1

Read not used

Channel 6 (Read / Write) Set Register (b = base2 address; 0Ah = register offset; * Refer to “Writing to the Register” for an explanation of using channel # 6 register.)

b + 0Ah 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Write OutputSelection Mod Selection bit-12 bit-11 bit-10 bit-9 bit-8 bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1

Read not used

Channel 7 (Read / Write) Set Register (b = base2 address; 0Ch = register offset; * Refer to “Writing to the Register” for an explanation of using channel # 7 register.)

b + 0Ch 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Write OutputSelection Mod Selection bit-12 bit-11 bit-10 bit-9 bit-8 bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1

Read not used

Channel 8 (Read / Write) Set Register (b = base2 address; 0Eh = register offset; * Refer to “Writing to the Register” for an explanation of using channel # 8 register.)

b + 0Eh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Write OutputSelection Mod Selection bit-12 bit-11 bit-10 bit-9 bit-8 bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1

Read not used

Channel 1 (Read / Write) Reset Register (b = base2 address; 010h = register offset; * Refer to “Writing to the Register” for an explanation of using channel # 1 register.)

b + 010h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Write OutputSelection Mod Selection bit-12 bit-11 bit-10 bit-9 bit-8 bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1

Read not used

Channel 2 (Read / Write) Reset Register (b = base2 address; 012h = register offset; * Refer to “Writing to the Register” for an explanation of using channel # 2 register.)

b + 012h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Write OutputSelection Mod Selection bit-12 bit-11 bit-10 bit-9 bit-8 bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1

Read not used

Channel 3 (Read / Write) Reset Register (b = base2 address; 014h = register offset; * Refer to “Writing to the Register” for an explanation of using channel # 3 register.)

b + 014h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Write OutputSelection Mod Selection bit-12 bit-11 bit-10 bit-9 bit-8 bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1

Read not used

Channel 4 (Read / Write) Reset Register (b = base2 address; 016h = register offset; * Refer to “Writing to the Register” for an explanation of using channel # 4 register.)

b + 016h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Write OutputSelection Mod Selection bit-12 bit-11 bit-10 bit-9 bit-8 bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1

Read not used

Channel 5 (Read / Write) Reset Register (b = base2 address; 018h = register

offset; * Refer to “Writing to the Register” for an explanation of using channel # 5 register.)

b + 018h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Write OutputSelection Mod Selection bit-12 bit-11 bit-10 bit-9 bit-8 bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1

Read not used

Channel 6 (Read / Write) Reset Register (b = base2 address; 01Ah = register offset; * Refer to “Writing to the Register” for an explanation of using channel # 6 register.)

b + 01Ah 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Write OutputSelection Mod Selection bit-12 bit-11 bit-10 bit-9 bit-8 bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1

Read not used

Channel 7 (Read / Write) Reset Register (b = base2 address; 01Ch = register offset; * Refer to “Writing to the Register” for an explanation of using channel # 7 register.)

b + 01Ch 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Write OutputSelection Mod Selection bit-12 bit-11 bit-10 bit-9 bit-8 bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1

Read not used

Channel 8 (Read / Write) Reset Register (b = base2 address; 01Eh = register offset; * Refer to “Writing to the Register” for an explanation of using channel # 8 register.)

b + 01Eh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Write OutputSelection Mod Selection bit-12 bit-11 bit-10 bit-9 bit-8 bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1

Read not used

BSM Command (Read / Write) Register (b = base2 address; 020h = register offset.

b + 020h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Write Idle Adjustment Test MeasureMode

Read not used

Status (Read ) Register (b = base2 address; 022h = register offset.

b + 022h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Write not used

Read X X X X X X X X ExtendedStatus X X X X X Error Busy

Status Type (Read ) Register (b = base2 address; 024h = register offset.

b + 024h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Write not used

Read X X X X X TestCycle SetCycle ResetCycle X Add.Errorbit-3 Add.Errorbit-2 Add.Errorbit-1 Add.Errorbit-0 TestError DataError ModeError

Board Serial Number (Read) Register (b = base2 address; 026h = register offset

b + 026h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

* Write not used

Read X X X X X X X X Data

Reading the

Registers

You can read the following Bucking Source registers:

1. Manufacturer’s ID Register (base1 + 00h)

2. Device Type Register (base1 + 02h)

3. I/O Status Register (base1 + 04h)

4. Channel 1 Status Set Register (base2 + 000h)

5. Channel 2 Status Set Register (base2 + 002h)

6. Channel 3 Status Set Register (base2 + 004h)

7. Channel 4 Status Set Register (base2 + 006h)

8. Channel 5 Status Set Register (base2 + 008h)

9. Channel 6 Status Set Register (base2 + 00Ah)

10. Channel 7 Status Set Register (base2 + 00Ch)

11. Channel 8 Status Set Register (base2 + 00Eh)

12. Channel 1 Status Reset Register (base2 + 010h)

13. Channel 2 Status Reset Register (base2 + 012h)

14. Channel 3 Status Reset Register (base2 + 014h)

15. Channel 4 Status Reset Register (base2 + 016h)

16. Channel 5 Status Reset Register (base2 + 018h)

17. Channel 6 Status Reset Register (base2 + 01Ah)

18. Channel 7 Status Reset Register (base2 + 01Ch)

19. Channel 8 Status Reset Register (base2 + 01Eh)

20. BSM Command Register (base2 + 020h)

21. Status Register (base2 + 022h)

22. Status Type Register (base2 + 024h)

22. Board Serial Number (base2 + 026h)

ID and Device Type

Register

ID Register, reading the ID register returns EBFh which identifies the manufacturer as Fermi National Laboratory and indicates that the module is an A16/A24 register-based device.

Device Type Register, reading the Device Type register returns 3EAh which indicates the device as the BSM-1002A Bucking Source Module.

I/O Status Register

Six bits (bit 0, 1, 2, 3, 14, and 15) of the I/O Status (Read) register (register 04h) provide information on the DT9110 interface board.

Bit No. BitMnemonic Comments

0 Reset This bit reflects the state of the RESET bit in the Control register

1 SYSFAIL This bit reflects the state of the SYSFAIL INHIBIT bit in the Control register

2 Passed The PASSED bit is normally used to indicate the success or failure of a device’s self test. Because the DT9110 doses not execute a self test, this bit is automatically set to 1 when the READY bit is set to 1.

3 Ready This bit is used to inform the system controller that the DT9110 is ready to begin operations.

14 MODID This bit is the inverted state of the MODID pin.

15 A16/A24 This bit is only valid for A16/A24 and A16/A32 devices. A one (1) in this field indicates that the DT9110’s A24 or A32 registers can be accessed.

Note: Because Channels 1 through 8 have the same definitions, only one register definition table is presented.

Channel 1 through 8 Status (Read) Registers

Thirteen bit’s (bit 0, through 12 of the Channel 1 through 8 Status (Read) register provide information about Channels 1 through 8. Addresses for the eight channels SET and RESET registers can be found on page 3-13 of this Chapter.

Bits Resistor Description

0 12.1 Ohm’s 0 - bypassed 1 - selected

1 24.3 Ohm’s 0 - bypassed 1 - selected

2 48.7 Ohm’s 0 - bypassed 1 - selected

3 97.6 Ohm’s 0 - bypassed 1 - selected

4 196 Ohm’s 0 - bypassed 1 - selected

5 392 Ohm’s 0 - bypassed 1 - selected

6 787 Ohm’s 0 - bypassed 1 - selected

7 1.58K Ohm’s 0 - bypassed 1 - selected

8 3.16K Ohm’s 0 - bypassed 1 - selected

9 6.34K Ohm’s 0 - bypassed 1 - selected

10 12.7K Ohm’s 0 - bypassed 1 - selected

11 25.5K Ohm’s 0 - bypassed 1 - selected

12 ModuleSelect 0 - Module one (1) is selected 1 - Module two (2) has been selected

13 OutputSelect 0 - OC1 is selected1 - OC2 has been selected

14-15 X not used

BSM Command (Read) Register

Four bits (bit 0, 1, 2, and 3) of the BSM Command register (register 020h) provide information about which mode BSM is set to.

Bits BitMnemonic Description

0 MeasureMode 0 - this field not selected.1 - in this field indicates that Measurement Mode has been selected, and the front panel push button has been disabled.

1 Test 0 - this field not selected.1 - in this field indicates that Test Mode for internal bus and logic testing has been selected, and the front panel push button has been disabled.

2 AdjustmentMode 0 - this field not selected.1 - in this field indicates that Adjustment Mode has been selected, and the front panel push button has been disabled.

3 Idle 0 - this field not selected.1 - in this field indicates that Idle Mode has been selected, and the front panel push button has been enabled.

4-15 X not used

Status (Read) Register

Three bits (bit 0, 1, and 7) of the Status register (register 022h) provide information about the status of BSM.

Bits BitMnemonic Description

0 Busy 0 - in this field indicates the module is not busy.1 - in this field indicates that the relays are being set or reset and no action can be take until a (0) is read.

1 Error 0 - in this field indicates no error1 - in this field indicates a module error has occurred and to read the STATUS TYPE REGISTER for more info.

2-6 X not used

7 ExtendedStatus 0 - in this field indicates only (8) status bits are available1 - in this field indicates more than (8) status bits.

8-15 X not used

Status Type (Read) Register

Three bits (bit 0, 1, and 7) of the Status Type register (register 022h) provide information about the status type for BSM.

Bits BitMnemonic Description

0 ModeError 1 - in this field indicates that more than one valid Mode has been selected and that it is an illegal operation.

1 DataError 1 - in this field indicates that what was sent by the host computer and what was read back from the channels read register does not compare.

2 TestError 1 - in this field indicates that a pre assigned bit pattern was sent to a channels set or reset register and then read back does not compare.

3 ErrorAddress Address of Module System Error bit-0

4 ErrorAddress Address of Module System Error bit-1

5 ErrorAddress Address of Module System Error bit-2

6 ErrorAddress Address of Module System Error bit-3

7 X not used

8 ResetCycle 1 - in this field indicates the Module is in the process or has just finished a Reset Cycle.

9 SetCycle 1 - in this field indicates the Module is in the process or has just finished a Set Cycle.

10 TestCycle 1 - in this field indicates the Module is in the process or has just finished a Test Cycle.

11-15 X not used

BSM Board

Serial Number

(Read) Register

Eight bits (bit 0 - 7) of the BSM Board Serial Number register (register 026h) provide the board serial number.

Bits BitWeight Description

0 1 0 - in this field and a one (1) in bits-1 - 7 would indicate that the boards serial number is one (1).

1 2 0 - in this field and ones (1’s) in the remaining bits would indicate the boards serial number is two (2).

2 4 0 - in this field and ones (1’s) in the remaining bits would indicate the boards serial number is four (4).

3 8 0 - in this field and ones (1’s) in the remaining bits would indicate the boards serial number is eight (8).

4 16 0 - in this field and ones (1’s) in the remaining bits would indicate the boards serial number is sixteen (16).

5 32 0 - in this field and ones (1’s) in the remaining bits would indicate the boards serial number is thirty two (32).

6 64 0 - in this field and ones (1’s) in the remaining bits would indicate the boards serial number is sixty four (64).

7 128 0 - in this field and ones (1’s) in the remaining bits would indicate the boards serial number is one hundred and twenty eight (128).

8-15 X not used

Interrupt Request

The Bucking Source Module generates an interrupt request by pulling low the appropriate interrupt line on the DT9110 I/O interface board. The Bucking Source Module generates two interrupts. The first occurs when the front panel push button is activated to reset the module. This reset can only be activated if the module is in the IDLE mode configuration. The second interrupt occurs if an error occurs in the EPLD U20 (Flex 8000) during circuit configuration, the FLEX 8000 device pulls and holds its nSTATUS pin low, indicating a configuration error. The push button and FLEX configuration signals are ANDed to drive the interrupt line on the DT9110 I/O interface board. The BSM-1002A uses IRQ-six (6) to indicate a push button reset and IRQ-seven (7) for FLEX configuration error. Interrupts are serviced by BSM interrupt software services. When a VXIbus interrupt acknowledge cycle occurs, the DT9110 will confirm that the interrupt acknowledge cycle applies to the DT9110’s interrupt request. If not, it will assert IACKOUT. When an interrupt acknowledge cycle applies to the board, the DT9110 places the 16-bit STATUS/ID word onto the VXI data bus. Release of the interrupt request line and setting of the DTACK cycle is defined by VXI specification.

Writing to the

Registers

The following are Bucking Source register

1. I/O Control (Write) Register (base1 + 004h)

2. Channel 1 Set Register (base2 + 00h)

3. Channel 2 Set Register (base2+ 02h)

4. Channel 3 Set Register (base2 + 04h)

5. Channel 4 Set Register (base2 + 06h)

6. Channel 5 Set Register (base2+ 08h)

7. Channel 6 Set Register (base2 + 0Ah)

8. Channel 7 Set Register (base2+ 0Ch)

9. Channel 8 Set Register (base2 + 0Eh)

10. Channel 1 Reset Register (base2 + 010h)

11. Channel 2 Reset Register (base2 + 012h)

12. Channel 3 Reset Register (base2 + 014h)

13. Channel 4 Reset Register (base2 + 016h)

14. Channel 5 Reset Register (base2 + 018h)

15. Channel 6 Reset Register (base2 + 01Ah)

16. Channel 7 Reset Register (base2 + 01Ch)

17. Channel 8 Reset Register (base2 + 01Eh)

18. BSM Command Register (base2 + 020h)

I/O Control (Write) Register

Three bits (bit 0, 1, and 15) of the I/O Control (Write) register (register 04h) provide information on the DT9110 interface board.

Bit No. BitMnemonic Comments

0 Reset A one (1) in this field forces the device into a soft reset state

1 SYSFAILInhibit A one (1) in this field disables the device from driving the SYSFAIL line

2-14 X not used

15 A16/A24 This bit is only valid for A16/A24 and A16/A32 devices. A one (1) in this field indicates that the DT9110’s A24 or A32 registers can be accessed.

BSM Command (Write) Register

Four bits (bit 0, 1, 2, and 3) of the BSM Command register (register 020h) provide information about which mode BSM is set to.

Bits4 BitMnemonic Description

0 MeasureMode 0 - this field not selected.1 - in this field indicates that Measurement Mode has been selected, and the front panel push button has been disabled.

1 Test 0 - this field not selected.1 - in this field indicates that Test Mode for internal bus and logic testing has been selected, and the front panel push button has been disabled.

2 AdjustmentMode 0 - this field not selected.1 - in this field indicates that Adjustment Mode has been selected, and the front panel push button has been disabled.

3 Idle 0 - this field not selected.1 - in this field indicates that Idle Mode has been selected, and the front panel push button has been enabled.

4-15 X not used

Note: Because Channels 1 through 8 have the same definitions, only one register definition table is presented.

Channel 1 through 8 Write Registers

Thirteen bit’s (bit 0, through 12 of the Channel 1 through 8 (Write) register provide information about Channels 1 through 8. Addresses for the eight Channels of SET and RESET registers can be found on the previous page.

Bits Resistor Description

0 12.1 Ohm’s 0 - bypassed 1 - selected

1 24.3 Ohm’s 0 - bypassed 1 - selected

2 48.7 Ohm’s 0 - bypassed 1 - selected

3 97.6 Ohm’s 0 - bypassed 1 - selected

4 196 Ohm’s 0 - bypassed 1 - selected

5 392 Ohm’s 0 - bypassed 1 - selected

6 787 Ohm’s 0 - bypassed 1 - selected

7 1.58K Ohm’s 0 - bypassed 1 - selected

8 3.16K Ohm’s 0 - bypassed 1 - selected

9 6.34K Ohm’s 0 - bypassed 1 - selected

10 12.7K Ohm’s 0 - bypassed 1 - selected

11 25.5K Ohm’s 0 - bypassed 1 - selected

12 ModuleSelect 0 - Module one (1) is selected 1 - Module two (2) has been selected

13 OutputSelect 0 - OC1 is selected1 - OC2 has been selected

14-15 X not used

Number of Boards Allowed

Because of software constraints, only two (2) BSM-1002A modules can be used in one VXI enclosure. This number can be made larger with some software changes (refer to Terry Kiper PAFMS Software Document).

Serial Number

Each BSM-1002A module has a unique number assigned to it (1 - 256). This number is read by an EPLD on power up and the number is stored in its register. This number can be read at any time, from the Board Serial Number Register.

Chapter 4

Embedded Controller

Chapter Contents

This Chapter describes the embedded controller of the BSM-1002A module.

A block diagram in Figure 4-1 shows how the controller is configured. The VXI bus includes READ, WRITE, UASEL, IACK, IRQ, MODID, and master reset (MRESET) control lines along with 16-bit Address bus and a 16-bit Data bus. The DT9110 interface is described in Chapters 2 and 3. Output from the DT9110 Interface Controller supplies control signals, addresses and data to the embedded controller. The embedded controller is SRAM Flex EPF8820 Altera programmable logic device.

Figure 4-1, BSM-1002A Logic block diagram

Appendix A

Contents

The contents of Appendix A is:

· replacement Parts List

· channel configuration and control schematics

· EPLD pinouts

· printed circuit board modifications

· connector pinouts

Caution

The circuit board assembly uses a 6-layer circuit board. Care must be exercised in removing and replacing parts, otherwise damage will result to the circuit board.

Replacement Parts List

The following is the parts list for BSM-1002A, it doses not contain such parts as screws, nuts, and assorted test pins.

BSM-1002A Replacement Parts

ReferenceDesignation Qty Part Description Mft. Mft. Part Number

U17-18 2 74als244 TI FNAL 1455-8244

RL1,120 120 Relay Aromat TN2E-L2-5V

1 VXI Hardware Kit ICS Elect. 113991

BSM-1002A Replacement Parts (continuation)

1 Printed Circuit Board FNAL 1670-EB-329027

J1 1 40-pin connectors PC Board Amp 749830-4

U19 1 Interface Board Interface Technology DT9110

L1 1 Inductor 130 - 150 hn @40 Amps Newark 5298

Sw1-5 5 Dip Switches 8 Poisson Newark 84F804 TYPE GDR08

Led 1,4 4 Dual Red LED Newark 50F6026 TYPE 553-0111

U20 1 PLCC Socket AUGAT PGM208-1A1717-V

U1-16 16 PLCC Socket Newark QILE84P-410T

U20 1 EPLD Altera EPF8820-GC192-3

U26 1 EPLD Altera EPC1213-P-C8

U25 1 EPLD Altera EPM5032

U1-16 16 Peripheral Relay Driver Allegro UCN5881EP

U41 2 IC9602 one shot Newark DM9602

U24 1 IC DS1232 Newark

P1,2 2 VXI card edge connector 96 pin Newark DIN-96CPC-SR1-TR

F1 1 Fuse - Pico 3 amp Newark 28F136 TYPE 251003

BP1,28 28 IC Filter Cap’s 923CZ5U103M0508 Newark 65F929

SW2 1 Front Panel Push Button TPA11CG-RA0 Newark 13F3638

R1,13,25,37,49,61,73,85 8 Resistor 12.1 1% Newark 58F005 RN-55C

R2,14,26,38,50,62,74,86 8 Resistor 24.3 1% Newark 58F005 RN-55C

R3,15,27,39,51,63,75,87 8 Resistor 48.7 1% Newark 58F005 RN-55C

R4,16,28,40,52,64,76,88 8 Resistor 97.6 1% Newark 58F005 RN-55C

R5,17,29,41,53,65,77,89 8 Resistor 196 1% Newark 58F005 RN-55C

R6,18,30,42,54,66,78,90 8 Resistor 392 1% Newark 58F005 RN-55C

R7,19,31,43,55,66,78,91 8 Resistor 787 1% Newark 58F005 RN-55C

R8,20,32,44,56,67,79,92 8 Resistor 1.58K 1% Newark 58F005 RN-55C

R9,21,33,45,57,68,80,93 8 Resistor 3.16K 1% Newark 58F005 RN-55C

R10,22,34,46,58,69,81,94 8 Resistor 6.34K 1% Newark 58F005 RN-55C

R11,23,35,47,59,70,82,95 8 Resistor 12.7K 1% Newark 58F005 RN-55C

R12,24,36,47,60,71,83,96 8 Resistor 25.5K 1% Newark 58F005 RN-55C

R111,113 2 Resistor 1K 1/4 watt FNAL

R103,117,110,107,112 5 Resistor 2.2K 1/4 watt FNAL

R99,102,106,114 4 Resistor 470 1/4 watt FNAL

R97,100,104,115 4 Resistor 33.3K 1/4 watt FNAL

R98,101,105,116 4 Resistor 4.7K 1/4 watt FNAL

C1-4 4 Capacitor 1uf FNAL

RNSER 2 SIP Resistor 2.2K 1/4 w Newark

Channel Configuration and

Control Schematics

The following 10 schematics is broken up into Channels, Connectors, and Digital Circuitry parts.

EPLD Pin Out

The following Figures A1 and A2 show the pinouts for EPLD’s U20, U25 and U26. The EPLD’s are compiled on an IBM compatible computer using Altera MAX+Plus II software. File names for U20 are bsm_cntr.gdf and bsm_cntr.sym. File names for U25 are loader.gdf, and loader.sym. The MAX+Plus II output file names are bsm_cntr.pof used with U26 EPC1213, and loader.pof used with U25 EPM5032 and requires a MAX+Plus II EPLD programmer or Data I/O PAL programmer to program the device. The EPLD 5032 U25 is used to down load the Flex configuration program during initial module commissioning. It is not used during normal module use and must be removed from the board so conflicts will not occur with the Flex configuration pins. If the Flex serial EPC1213 U26 is not going to be used then configuration program bsm_cntr.pof must be recompiled and set into the Passive Mode . Refer to Altera Flex 8000 manual for details on how to set up these devices.

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Figure A1, U20 EPF8820GC192

Lower left corner is notch location

Device: EPM5032

- - - - -

GND -|1 28|- GND

CLK -|2 27|- GND

RESERVED -|3 26|- spair2

VA1 -|4 25|- conf

VA15 -|5 24|- RESERVED

BVD02 -|6 23|- CONF_DONE

VCC -|7 22|- VCC

GND -|8 21|- GND

BVD03 -|9 20|- NCONF2

nSTATUS -|10 19|- DCLK0

/REGRD -|11 18|- DATA1

BVD00 -|12 17|- BVD01

/UASEL -|13 16|- VA2

/REGWR -|14 15|- VA3

- - - - -

Figure A2, U25 EPM5032 external Flex serial loader

Printed Circuit

Board Modifications

Changes to circuit design include seventeen wires to be soldered to the back side of the printed circuit board. Care must be exercised not to overheat the board when soldering these wires.

Items 2 through 16 refer to the installation of two pull up sip resistors RN1 and RN2 to the internal 16-bit bus supplying data to the relay drivers U1 through U16. Pin one (1) of sip’s RN1 and RN2 is connected to VCC (+5V).

1. Solder a wire between U20 J2 and U22 pin 11

2. Solder a wire between U1 pin 8 and sip 1 pin 2

3. Solder a wire between U2 pin 7 and sip 1 pin 3

4. Solder a wire between U3 pin 6 and sip 1 pin 4

5. Solder a wire between U4 pin 5 and sip 1 pin 5

6. Solder a wire between U5 pin 4 and sip 1 pin 6

7. Solder a wire between U6 pin 3 and sip 1 pin 7

8. Solder a wire between U7 pin 2 and sip 1 pin 8

9. Solder a wire between U8 pin 1 and sip 1 pin 9

10. Solder a wire between U1 pin 37 and sip 1 pin 10

11. Solder a wire between U2 pin 38 and sip 2 pin 2

12. Solder a wire between U3 pin 39 and sip 2 pin 3

13. Solder a wire between U4 pin 40 and sip 2 pin 4

14. Solder a wire between U5 pin 41 and sip 2 pin 5

15. Solder a wire between U6 pin 42 and sip 2 pin 6

16. Solder a wire between U7 pin 43 and sip 2 pin 7

17. Solder a wire between U8 pin 42 and sip 2 pin 8

Connector J1

Pinout

Connector J1 is a Amplite 40 pin right angle receptacle headers with latching blocks. Table A-1 show the signal (Net) names assigned to each pin.

BSM - J1 Description BSM - J1 Description

1 Buck_Coil3 21 Buck_Coil7

2 Buck_In3 22 Buck_In7

3 Buck_Out3 23 Buck_Out7

4 Buck_Source3 24 Buck_Source7

5 Buck_Coil4 25 Buck_Coil8

6 Buck_In4 26 Buck_In8

7 Buck_Out4 27 Buck_Out8

8 Buck_Source4 28 Buck_Out6

9 Buck_Out2 29 Buck_Out6

10 Buck_Source2 30 Buck_Source6

11 Buck_In2 31 Buck_In6

12 Buck_Coil2 32 Buck_Coil6

13 Buck_Out1 33 Buck_In5

14 Buck_Source1 34 Buck_Source5

15 Buck_In1 35 Buck_In5

16 Buck_Coil1 36 buck_Coil5

17 IN_M1_OC1 37 IN_M2_OC1

18 OUT_M1_OC1 38 OUT_M2_OC1

19 IN_M1_OC2 39 IN_M2_OC2

20 OUT_M1_OC2 40 OUT_M2_OC2

Table A - 1 Bucking J-1 pin out

 

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