Signal Descriptions

Table of Contents

AD CAMAC Link

The AD CAMAC link is a 10MHz modified manchester signal. A signal transition always occurs at the beginning of the 100 nanosecond bit cell. A transition within the cell indicates a "1" and no transition indicates a "0".

AD CAMAC PIOX

PIOX Frame 1
H1H215.......................0807........00T1T2
00CRATE ADDRESS P1
H2 being 0 indicates a 16 bit data frame.

PIOX Frame 2
H1H215...............................111009....................060504...........................00T1T2
00N16...N8...N4...N2...N11A8...A4...A2...A11F16...F8...F4...F2...F1P1

If the second frame indicates a dataway write operation, a third frame is transmitted as follows:

PIOX Write Frame 3
H1 H223...................00 T1 T2
0 1 W24(MSB) --- W1P1
H2 being 1 indicates a 24 bit data frame.

If the second frame denotes a BTR function set up [N(24)A(15)F(16)], additional third and fourth frames are transmitted as follows:

BTR Setup Frame 3
H1H215...............1110 09.......0605 04............00T1T2
0 0 N16 N8 N4 N2 N1 0A8 A4 A2 A1 0 F16 F8 F4 F2 F1 P 1

BTR Setup Frame 4
H1H215.................0807................00 T1 T2
01 32,768 - BTR Word Count - 1 128 - BTR Maximum No Q - 1 P 1

The third frame contains the NAF code that is to be repeatedly cycled by the BTR function. N must range N(0-23) and F must range F(0-7).

In the fourth frame, Word Count can range from zero to 65,535 with resultant word returns ranging from 1 to 65,536 respectively. Maximum No Q can range from 0 to 255.

AD CAMAC PIOR

The first two frames of the Port A PIOR response are always as follows

PIOR Frame 1
H1H223...............16 15...........08 07..............00 T1T2
0 1ECHO CRATE ADDRESSSTATUS BYTE 1STATUS BYTE 2P1

PIOR Frame 2
H1H223......1615..........111009............060504.............00T1T2
01STATUS BYTE 3N16 N8 N4 N2 N11A8 A4 A2 A11F16 F8 F4 F2 F1P1

The Crate Address and NAF data are considered as echo data. The Crate Address is generated from the T SCC address selector switch whereas NAF is directly reflected from the second PIOX transmission.

Status Byte data are as follows:

STATUS BYTE 1
76543210
Q X I BP/AIP CRLAM CRA NRA CRB

QQ indicates that a target module returned Q during a dataway cycle.
XX indicates that a target module returned X during a dataway cycle.
II indicates the state of the Inhibit line.
BP/AIPThis indicates the state of the Beam Permit/ Abort in Progress status line from the CAMAC dataway.
CRLAMThis indicates if any LAM is raised in the crate.
CRAIndicates that Port A has the crate reserved.
NRAIndicates that Port A has a slot reserved.
CRBIndicates that Port B has the crate reserved.

STATUS BYTE 2
76543210
NRBCRBTNRBTBTAPAN=PBNPAXENAFOKPA SR2P

NRBIndicates that Port B has a slot reserved.
CRBTIndicates that CRB was terminated by a Port A operation.
NRBTIndicates that NRB was terminated by a Port A operation.
BTAIndicates that the Block Transfer function is active.
PAN=PBNIndicates that the slot currently addressed by Port A equals the last slot addressed by Port B.
PAXEIndicates a detected protocol error on the Port a PIOX line for the second or subsequent frames.
NAFOKPAIndicates that the second PIOX transmission was properly received with l's separating the NAF fields and a N that ranged between 0 and 24.
SR2PIndicates that service request level 2 was raised and permitted to cycle the dataway if appropriate. This line also indicates the acceptance of arbitration requests.

STATUS BYTE 3
76543210
PARDFPALDFPAN=BTNANAFOKBTN(24)QFAGRCZ

PARDFThis is the REad Data Flag for Port A and indicates that there will be a third response frame which will contain readf data or retransmitted write data.
PALDFThis is the LAM Data Flag for Port A and indicates that there will nen a a third frame response which will contain the status of LAMs for slots 1 thru 24. L22 and L23 are always false.
PAN=BTNAThis indicates that the slot addresses by Port A was the same slot being addressed by an active Block Transfer function. The crate controller will not have completed the requested operation.
NAFOKBTThis line indicates a properly received NAF frame for the Block Transfer operation in response to a N(24)A(15)F(16) operation. Reciept of a N that ranged from 0 to 23, a F that ranged from 0 to 7, and 0's seperating the NAF fields is implied.
N(24)QThis indicates that a N(24) operation to the TSCC was executed. This line is largely irrelevant to the N(24)A(0)F(0) operation which always results in a return of LAM status.
FAGRThis is the only crate controller LAM and indicates a failed Aggragate Command. This line is reset only by a Port A read of LAM status
CThis indicates the state of the dataway Clear line during the last executed cycele. It is expected to be present onle during a Poiryt A induced CS2 cycle
ZThis indicates the state of the dataway Initialize line during the last executed cycle. It is expected tobe present only during a Port A induced ZS2 cycle.

The third frame of a Port A PIOR response, if present, is indicated by the assertion of PARDF or PALDF in Status Byte 3. It contains 24 bits of read data, echo write data, or LAM status.

PIOR Frame 3
H1H223.................0T1T2
01R24 - READ DATA - R1 01
W24 - ECHO WRITE DATA - W1
L24 - LAM STATUS - L1

AD CAMAC BTR

The first and last frame of a Block Transfer response is always as follows.

BTR First/Last Frame
H1H223.........................1615...1312....87...43210T1T2
10CRATE ADDRESS000BTN16 BTN8 BTN4 BTN2 BTN10000BTABTTWCBTTNQBTTTOP1

BTNIndicates the target slot of the Block Transfer operation.
BTAIndicates that the Block Transfer function is active.
BTTWCIndicates that the Block Transfer function was terminated by decrement of the desired word count to zero.
BTTNQIndicates that the Block Transfer function was terminated by decrement of the preset maximum no Q count to zero.
BTTTOIndicates that the Block Transfer function was terminated by the TSCC because a Time Out occurred. The internal Time Out value is approximately 1/2 second.
These last four bits of status are mutually exclusive. If none is present, it is implied that the BT function was programmed off by the N(24)A(15)F(20) Port A operation. Intervening frames on the BTR line contain the read data from successful dataway operations to the target module. They are structured as follows:

BTR Data Frame
H1H223..............00T1T2
11R24 - BT DATA - R1P1

The maximum transfer rate accommodated by Block Transfer is 750 kbyte/sec. This corresponds to a CAMAC dataway cycle every 4 microseconds. Maximum block length for BT is 65K CAMAC words. Port A and B may freely communicate with crate modules other than the BT target module throughout a Block Transfer operation.

Old AD CAMAC SLD Status Bits

Old AD CAMAC SLD Status Bits
15141312111098
BUSYQ_X_SRPNO_QOP_DENIEDARBCONNO_Q_OR_XTIMEOUTLINK_ERROR
 
76543210
RF1CKRF2CKRF3CKCACKNAFCKEDCKPADRVCRLAM

BUSY?
Q_X_SRP?
NO_Q?
OP_DENIED?
ARBCON?
NO_Q_OR_X?
TIMEOUT?
LINK_ERROR ?
RF1CK?
RF2CK?
RF3CK?
CACK?
NAFCK?
EDCK?
PADRV?
CRLAM?

RD CAMAC Link

RD XD

RD CAMAC XD
6968...6160..575655545352..4847..4443..39383736
1CRATE NQRETRYAUXLOCKOUT  SLOTSUBADDRESSFUNCTONCP11

3534..11109876543210
1Write DataWP1111111111

CRATEDuh
NQRETRYIf 1, repeats the function up to three times locally
AUXLOCKOUTLocks out auxillary crate processor (C1001)
SLOTN
SUBADDRESSA
FUNCTIONF
CPCommand Parity
WPWrite data Parity

RD RD

3534..11109876543210
1READ DATARP11QDXOFFL0XPEP1

RPRead data Parity
QQ response
DCrate LAM
XX response
OFFLCrate offline
XPETransmit Parity error

MDAT

The MDAT serial frame is 28 bits in length, self clocking, and operates at a 10 MBit per second rate. The frame consists of a two bit header, an eight bit type code, sixteen bits of data, and a two bit trailer which contains a frame parity. A signal transition always occurs at the beginning of the 100 nanosecond bit cell. A transition within the cell indicates a "1" and no transition indicates a "0". Parity is such that the frame is always 2.75 microseconds in length.

MDAT Frame Protocol
H1H223..................1615.....0T1T2
10MSB - Type Code - LSBMSB - MDAT Data - LSBP1

Frames are generally transmitted at ten microsecond intervals synchronous to TCLK event $07 (720 Hz). More detailed information concerning active frames is available in spreadsheet format.

TCLK and BSCLK

The TCLK and BSCLK serial frame is 12 bits in length, self clocking, and operates at a 10 MBit per second rate for TCLK and approximately 7.5 MBit per second for BSCLK. The frame consists of a one bit header, an eight bit event code, a parity bit, and a two bit trailer. A signal transition always occurs at the beginning of the bit cell. A transition within the cell indicates a "1" and no transition indicates a "0". TCLK bit cells are 100 nanoseconds wide and BSCLK bit cells are approximately 133 nanoseconds wide.

TCLK/BSCLK Frame Protocol
H17..................00PT1T2
0MSB - EVENT - LSB P11

More detailed information concerning tclk events is available in spreadsheet format.

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